Update copyright years.

[thirdparty/gcc.git] / gcc / config / arm / cortex-a8.md

diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md
index ed0b351365c8ef363fbecf476e23f25c4e17cc08..9032cb3709e4771d2925f2abf6fc6a854ef991d0 100644 (file)
--- a/gcc/config/arm/cortex-a8.md
+++ b/gcc/config/arm/cortex-a8.md
@@ -1,5 +1,5 @@
 ;; ARM Cortex-A8 scheduling description.
-;; Copyright (C) 2007-2013 Free Software Foundation, Inc.
+;; Copyright (C) 2007-2020 Free Software Foundation, Inc.
 ;; Contributed by CodeSourcery.
 
 ;; This file is part of GCC.
@@ -86,11 +86,11 @@
 (define_insn_reservation "cortex_a8_alu" 2
   (and (eq_attr "tune" "cortexa8")
        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
-                        alu_reg,alus_reg,logic_reg,logics_reg,\
+                        alu_sreg,alus_sreg,logic_reg,logics_reg,\
                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
-                        adr,bfm,clz,rbit,rev,\
+                        adr,bfm,clz,rbit,rev,alu_dsp_reg,\
                         shift_imm,shift_reg,\
-                        multiple,no_insn"))
+                        multiple"))
   "cortex_a8_default")
 
 (define_insn_reservation "cortex_a8_alu_shift" 2
@@ -111,7 +111,8 @@
 (define_insn_reservation "cortex_a8_mov" 1
   (and (eq_attr "tune" "cortexa8")
        (eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\
-                        mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
+                        mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
+                        mrs"))
   "cortex_a8_default")
 
 ;; Exceptions to the default latencies for data processing instructions.
@@ -197,7 +198,7 @@
 ;; We assume 64-bit alignment for doubleword loads.
 (define_insn_reservation "cortex_a8_load1_2" 3
   (and (eq_attr "tune" "cortexa8")
-       (eq_attr "type" "load1,load2,load_byte"))
+       (eq_attr "type" "load_4,load_8,load_byte"))
   "cortex_a8_load_store_1")
 
 (define_bypass 2 "cortex_a8_load1_2"
@@ -220,7 +221,7 @@
 ;; issued as two micro-ops.
 (define_insn_reservation "cortex_a8_load3_4" 5
   (and (eq_attr "tune" "cortexa8")
-       (eq_attr "type" "load3,load4"))
+       (eq_attr "type" "load_12,load_16"))
   "cortex_a8_load_store_2")
 
 (define_bypass 4 "cortex_a8_load3_4"
@@ -237,12 +238,12 @@
 
 (define_insn_reservation "cortex_a8_store1_2" 0
   (and (eq_attr "tune" "cortexa8")
-       (eq_attr "type" "store1,store2"))
+       (eq_attr "type" "store_4,store_8"))
   "cortex_a8_load_store_1")
 
 (define_insn_reservation "cortex_a8_store3_4" 0
   (and (eq_attr "tune" "cortexa8")
-       (eq_attr "type" "store3,store4"))
+       (eq_attr "type" "store_12,store_16"))
   "cortex_a8_load_store_2")
 
 ;; An ALU instruction acting as a producer for a store instruction