;; ARM Cortex-A9 pipeline description
-;; Copyright (C) 2008-2013 Free Software Foundation, Inc.
+;; Copyright (C) 2008-2020 Free Software Foundation, Inc.
;; Originally written by CodeSourcery for VFP.
;;
;; Rewritten by Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
;; which can go down E2 without any problem.
(define_insn_reservation "cortex_a9_dp" 2
(and (eq_attr "tune" "cortexa9")
- (ior (and (eq_attr "type" "alu_reg,simple_alu_imm")
- (eq_attr "neon_type" "none"))
- (and (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift")
- (eq_attr "insn" "mov"))
- (eq_attr "neon_type" "none"))))
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_sreg,alus_sreg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,clz,rbit,rev,alu_dsp_reg,\
+ shift_imm,shift_reg,\
+ mov_imm,mov_reg,mvn_imm,mvn_reg,\
+ mov_shift_reg,mov_shift,\
+ mrs,multiple"))
"cortex_a9_p0_default|cortex_a9_p1_default")
;; An instruction using the shifter will go down E1.
(define_insn_reservation "cortex_a9_dp_shift" 3
(and (eq_attr "tune" "cortexa9")
- (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift")
- (not (eq_attr "insn" "mov"))))
+ (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
+ extend,mvn_shift,mvn_shift_reg"))
"cortex_a9_p0_shift | cortex_a9_p1_shift")
;; Loads have a latency of 4 cycles.
(define_insn_reservation "cortex_a9_load1_2" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "load1, load2, load_byte, f_loads, f_loadd"))
+ (eq_attr "type" "load_4, load_8, load_byte, f_loads, f_loadd"))
"cortex_a9_ls")
;; Loads multiples and store multiples can't be issued for 2 cycles in a
(define_insn_reservation "cortex_a9_load3_4" 5
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "load3, load4"))
+ (eq_attr "type" "load_12, load_16"))
"cortex_a9_ls, cortex_a9_ls")
(define_insn_reservation "cortex_a9_store1_2" 0
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "store1, store2, f_stores, f_stored"))
+ (eq_attr "type" "store_4, store_8, f_stores, f_stored"))
"cortex_a9_ls")
;; Almost all our store multiples use an auto-increment
(define_insn_reservation "cortex_a9_store3_4" 0
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "store3, store4"))
+ (eq_attr "type" "store_12, store_16"))
"cortex_a9_ls+(cortex_a9_p0_default | cortex_a9_p1_default), cortex_a9_ls")
;; We get 16*16 multiply / mac results in 3 cycles.
(define_insn_reservation "cortex_a9_mult16" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "insn" "smulxy"))
+ (eq_attr "type" "smulxy"))
"cortex_a9_mult16")
;; The 16*16 mac is slightly different that it
;; reserves M1 and M2 in the same cycle.
(define_insn_reservation "cortex_a9_mac16" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "insn" "smlaxy"))
+ (eq_attr "type" "smlaxy"))
"cortex_a9_mac16")
(define_insn_reservation "cortex_a9_multiply" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "insn" "mul,smmul,smmulr"))
+ (eq_attr "type" "mul,smmul,smmulr"))
"cortex_a9_mult")
(define_insn_reservation "cortex_a9_mac" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "insn" "mla,smmla"))
+ (eq_attr "type" "mla,smmla"))
"cortex_a9_mac")
(define_insn_reservation "cortex_a9_multiply_long" 5
(and (eq_attr "tune" "cortexa9")
- (eq_attr "insn" "smull,umull,smulls,umulls,smlal,smlals,umlal,umlals"))
+ (eq_attr "type" "smull,umull,smulls,umulls,smlal,smlals,umlal,umlals"))
"cortex_a9_mult_long")
;; An instruction with a result in E2 can be forwarded
;; Pipelining for VFP instructions.
;; Issue happens either along load store unit or the VFP / Neon unit.
;; Pipeline Instruction Classification.
-;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r
+;; FPS - fmov, ffariths, ffarithd,f_mcr,f_mcrr,f_mrc,f_mrrc
;; FP_ADD - fadds, faddd, fcmps (1)
;; FPMUL - fmul{s,d}, fmac{s,d}, ffma{s,d}
;; FPDIV - fdiv{s,d}
;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle.
(define_insn_reservation "cortex_a9_fps" 2
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd, r_2_f, f_2_r, f_flag"))
+ (eq_attr "type" "fmov, fconsts, fconstd, ffariths, ffarithd,\
+ f_mcr, f_mcrr, f_mrc, f_mrrc, f_flag"))
"ca9_issue_vfp_neon + ca9fps")
(define_bypass 1
(define_insn_reservation "cortex_a9_fadd" 4
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "fadds, faddd, f_cvt"))
+ (eq_attr "type" "fadds, faddd, f_cvt, f_cvtf2i, f_cvti2f"))
"ca9fp_add")
(define_insn_reservation "cortex_a9_fcmp" 1
;; Division pipeline description.
(define_insn_reservation "cortex_a9_fdivs" 15
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "fdivs"))
+ (eq_attr "type" "fdivs, fsqrts"))
"ca9fp_ds1 + ca9_issue_vfp_neon, nothing*14")
(define_insn_reservation "cortex_a9_fdivd" 25
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "fdivd"))
+ (eq_attr "type" "fdivd, fsqrtd"))
"ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24")
;; Include Neon pipeline description
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