;; Marvell ARM Processor Pipeline Description
-;; Copyright (C) 2010-2013 Free Software Foundation, Inc.
+;; Copyright (C) 2010-2020 Free Software Foundation, Inc.
;; Contributed by Marvell.
;; This file is part of GCC.
(define_insn_reservation "pj4_alu" 1
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
+ (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\
+ logic_imm,logics_imm,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,alu_dsp_reg,\
+ shift_imm,shift_reg")
(not (eq_attr "conds" "set")))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_conds" 4
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
+ (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\
+ logic_imm,logics_imm,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,alu_dsp_reg,\
+ shift_imm,shift_reg")
(eq_attr "conds" "set"))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_shift" 1
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
+ (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
+ alus_shift_imm,logics_shift_imm,\
+ alu_shift_reg,logic_shift_reg,\
+ alus_shift_reg,logics_shift_reg,\
+ extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")
(not (eq_attr "conds" "set"))
(eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
+ (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
+ alus_shift_imm,logics_shift_imm,\
+ alu_shift_reg,logic_shift_reg,\
+ alus_shift_reg,logics_shift_reg,\
+ extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")
(eq_attr "conds" "set")
(eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_shift" 1
(and (eq_attr "tune" "marvell_pj4")
(not (eq_attr "conds" "set"))
- (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
+ (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
+ alus_shift_imm,logics_shift_imm,\
+ alu_shift_reg,logic_shift_reg,\
+ alus_shift_reg,logics_shift_reg,\
+ extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
"pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "conds" "set")
- (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
+ (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
+ alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\
+ extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
"pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_ir_mul" 3
(and (eq_attr "tune" "marvell_pj4")
(ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes")))
- "pj4_is,pj4_mul,nothing*2,pj4_cp")
+ (eq_attr "widen_mul64" "yes")))
+ "pj4_is,pj4_mul,nothing*2,pj4_cp")
(define_insn_reservation "pj4_ir_div" 20
(and (eq_attr "tune" "marvell_pj4")
(define_insn_reservation "pj4_ldr" 3
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "load_byte,load1"))
+ (eq_attr "type" "load_byte,load_4"))
"pj4_is,pj4_alu1,nothing*2,pj4_cp")
(define_insn_reservation "pj4_ldrd" 3
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "load2"))
+ (eq_attr "type" "load_8"))
"pj4_is,pj4_alu1,nothing*2,pj4_cpb")
(define_insn_reservation "pj4_str" 1
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "store1"))
+ (eq_attr "type" "store_4"))
"pj4_is,pj4_alu1,nothing*2,pj4_cp")
(define_insn_reservation "pj4_strd" 1
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "store2"))
+ (eq_attr "type" "store_8"))
"pj4_is,pj4_alu1,nothing*2,pj4_cpb")
(define_insn_reservation "pj4_ldm" 4
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "load3,load4")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp")
+ (eq_attr "type" "load_12,load_16")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp")
(define_insn_reservation "pj4_stm" 2
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "store3,store4")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp")
+ (eq_attr "type" "store_12,store_16")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp")
;; Loads forward at WR-stage to ALU pipes
(define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu")
(define_insn_reservation "pj4_vfp_divs" 20
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "fdivs")) "pj4_is,nothing*2,vissue,vdiv*18,nothing")
+ (eq_attr "type" "fdivs, fsqrts")) "pj4_is,nothing*2,vissue,vdiv*18,nothing")
(define_insn_reservation "pj4_vfp_divd" 34
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "fdivd")) "pj4_is,nothing*2,vissue,vdiv*32,nothing")
+ (eq_attr "type" "fdivd, fsqrtd")) "pj4_is,nothing*2,vissue,vdiv*32,nothing")
(define_insn_reservation "pj4_vfp_mac" 9
(and (eq_attr "tune" "marvell_pj4")
(define_insn_reservation "pj4_vfp_cpy" 4
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\
- fcmps,fcmpd,f_cvt")) "pj4_is,nothing*2,vissue,vfast,nothing*2")
+ (eq_attr "type" "fmov,ffariths,ffarithd,fconsts,fconstd,\
+ fcmps,fcmpd,f_cvt,f_cvtf2i,f_cvti2f"))
+"pj4_is,nothing*2,vissue,vfast,nothing*2")
;; Enlarge latency, and wish that more nondependent insns are
;; scheduled immediately after VFP load.
(define_insn_reservation "pj4_vfp_to_core" 7
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "f_2_r,f_flag")) "pj4_isb,nothing,nothing,vissue,vfast,nothing*2")
+ (eq_attr "type" "f_mrc,f_mrrc,f_flag")) "pj4_isb,nothing,nothing,vissue,vfast,nothing*2")
(define_insn_reservation "pj4_core_to_vfp" 2
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "r_2_f")) "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp")
+ (eq_attr "type" "f_mcr,f_mcrr")) "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp")
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