;; Arm M-profile Vector Extension Machine Description
-;; Copyright (C) 2019-2020 Free Software Foundation, Inc.
+;; Copyright (C) 2019-2022 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF])
-(define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
-(define_mode_iterator MVE_0 [V8HF V4SF])
-(define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI])
-(define_mode_iterator MVE_3 [V16QI V8HI])
-(define_mode_iterator MVE_2 [V16QI V8HI V4SI])
-(define_mode_iterator MVE_5 [V8HI V4SI])
-(define_mode_iterator MVE_6 [V8HI V4SI])
-
-(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
- VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
- VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S VQNEGQ_S
- VCVTQ_TO_F_U VREV16Q_S VREV16Q_U VADDLVQ_S VMVNQ_N_S
- VMVNQ_N_U VCVTAQ_S VCVTAQ_U VREV64Q_S VREV64Q_U
- VQABSQ_S VNEGQ_S VMVNQ_S VMVNQ_U VDUPQ_N_U VDUPQ_N_S
- VCLZQ_U VCLZQ_S VCLSQ_S VADDVQ_S VADDVQ_U VABSQ_S
- VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S
- VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S
- VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
- VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT
- VCREATEQ_F VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U VBRSRQ_N_F
- VSUBQ_N_F VCREATEQ_U VCREATEQ_S VSHRQ_N_S VSHRQ_N_U
- VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U VADDLVQ_P_S
- VADDLVQ_P_U VCMPNEQ_U VCMPNEQ_S VSHLQ_S VSHLQ_U VABDQ_S
- VADDQ_N_S VADDVAQ_S VADDVQ_P_S VANDQ_S VBICQ_S
- VBRSRQ_N_S VCADDQ_ROT270_S VCADDQ_ROT90_S VCMPEQQ_S
- VCMPEQQ_N_S VCMPNEQ_N_S VEORQ_S VHADDQ_S VHADDQ_N_S
- VHSUBQ_S VHSUBQ_N_S VMAXQ_S VMAXVQ_S VMINQ_S VMINVQ_S
- VMLADAVQ_S VMULHQ_S VMULLBQ_INT_S VMULLTQ_INT_S VMULQ_S
- VMULQ_N_S VORNQ_S VORRQ_S VQADDQ_S VQADDQ_N_S VQRSHLQ_S
- VQRSHLQ_N_S VQSHLQ_S VQSHLQ_N_S VQSHLQ_R_S VQSUBQ_S
- VQSUBQ_N_S VRHADDQ_S VRMULHQ_S VRSHLQ_S VRSHLQ_N_S
- VRSHRQ_N_S VSHLQ_N_S VSHLQ_R_S VSUBQ_S VSUBQ_N_S
- VABDQ_U VADDQ_N_U VADDVAQ_U VADDVQ_P_U VANDQ_U VBICQ_U
- VBRSRQ_N_U VCADDQ_ROT270_U VCADDQ_ROT90_U VCMPEQQ_U
- VCMPEQQ_N_U VCMPNEQ_N_U VEORQ_U VHADDQ_U VHADDQ_N_U
- VHSUBQ_U VHSUBQ_N_U VMAXQ_U VMAXVQ_U VMINQ_U VMINVQ_U
- VMLADAVQ_U VMULHQ_U VMULLBQ_INT_U VMULLTQ_INT_U VMULQ_U
- VMULQ_N_U VORNQ_U VORRQ_U VQADDQ_U VQADDQ_N_U VQRSHLQ_U
- VQRSHLQ_N_U VQSHLQ_U VQSHLQ_N_U VQSHLQ_R_U VQSUBQ_U
- VQSUBQ_N_U VRHADDQ_U VRMULHQ_U VRSHLQ_U VRSHLQ_N_U
- VRSHRQ_N_U VSHLQ_N_U VSHLQ_R_U VSUBQ_U VSUBQ_N_U
- VCMPGEQ_N_S VCMPGEQ_S VCMPGTQ_N_S VCMPGTQ_S VCMPLEQ_N_S
- VCMPLEQ_S VCMPLTQ_N_S VCMPLTQ_S VHCADDQ_ROT270_S
- VHCADDQ_ROT90_S VMAXAQ_S VMAXAVQ_S VMINAQ_S VMINAVQ_S
- VMLADAVXQ_S VMLSDAVQ_S VMLSDAVXQ_S VQDMULHQ_N_S
- VQDMULHQ_S VQRDMULHQ_N_S VQRDMULHQ_S VQSHLUQ_N_S
- VCMPCSQ_N_U VCMPCSQ_U VCMPHIQ_N_U VCMPHIQ_U VABDQ_M_S
- VABDQ_M_U VABDQ_F VADDQ_N_F VANDQ_F VBICQ_F
- VCADDQ_ROT270_F VCADDQ_ROT90_F VCMPEQQ_F VCMPEQQ_N_F
- VCMPGEQ_F VCMPGEQ_N_F VCMPGTQ_F VCMPGTQ_N_F VCMPLEQ_F
- VCMPLEQ_N_F VCMPLTQ_F VCMPLTQ_N_F VCMPNEQ_F VCMPNEQ_N_F
- VCMULQ_F VCMULQ_ROT180_F VCMULQ_ROT270_F VCMULQ_ROT90_F
- VEORQ_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F VMAXNMVQ_F
- VMINNMAQ_F VMINNMAVQ_F VMINNMQ_F VMINNMVQ_F VMULQ_F
- VMULQ_N_F VORNQ_F VORRQ_F VSUBQ_F VADDLVAQ_U
- VADDLVAQ_S VBICQ_N_U VBICQ_N_S VCTP8Q_M VCTP16Q_M
- VCTP32Q_M VCTP64Q_M VCVTBQ_F16_F32 VCVTTQ_F16_F32
- VMLALDAVQ_U VMLALDAVXQ_U VMLALDAVXQ_S VMLALDAVQ_S
- VMLSLDAVQ_S VMLSLDAVXQ_S VMOVNBQ_U VMOVNBQ_S
- VMOVNTQ_U VMOVNTQ_S VORRQ_N_S VORRQ_N_U VQDMULLBQ_N_S
- VQDMULLBQ_S VQDMULLTQ_N_S VQDMULLTQ_S VQMOVNBQ_U
- VQMOVNBQ_S VQMOVUNBQ_S VQMOVUNTQ_S VRMLALDAVHXQ_S
- VRMLSLDAVHQ_S VRMLSLDAVHXQ_S VSHLLBQ_S
- VSHLLBQ_U VSHLLTQ_U VSHLLTQ_S VQMOVNTQ_U VQMOVNTQ_S
- VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_U VSHLLTQ_N_S
- VRMLALDAVHQ_U VRMLALDAVHQ_S VMULLTQ_POLY_P
- VMULLBQ_POLY_P VBICQ_M_N_S VBICQ_M_N_U VCMPEQQ_M_F
- VCVTAQ_M_S VCVTAQ_M_U VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U
- VQRSHRNBQ_N_U VQRSHRNBQ_N_S VQRSHRUNBQ_N_S
- VRMLALDAVHAQ_S VABAVQ_S VABAVQ_U VSHLCQ_S VSHLCQ_U
- VRMLALDAVHAQ_U VABSQ_M_S VADDVAQ_P_S VADDVAQ_P_U
- VCLSQ_M_S VCLZQ_M_S VCLZQ_M_U VCMPCSQ_M_N_U
- VCMPCSQ_M_U VCMPEQQ_M_N_S VCMPEQQ_M_N_U VCMPEQQ_M_S
- VCMPEQQ_M_U VCMPGEQ_M_N_S VCMPGEQ_M_S VCMPGTQ_M_N_S
- VCMPGTQ_M_S VCMPHIQ_M_N_U VCMPHIQ_M_U VCMPLEQ_M_N_S
- VCMPLEQ_M_S VCMPLTQ_M_N_S VCMPLTQ_M_S VCMPNEQ_M_N_S
- VCMPNEQ_M_N_U VCMPNEQ_M_S VCMPNEQ_M_U VDUPQ_M_N_S
- VDUPQ_M_N_U VDWDUPQ_N_U VDWDUPQ_WB_U VIWDUPQ_N_U
- VIWDUPQ_WB_U VMAXAQ_M_S VMAXAVQ_P_S VMAXVQ_P_S
- VMAXVQ_P_U VMINAQ_M_S VMINAVQ_P_S VMINVQ_P_S VMINVQ_P_U
- VMLADAVAQ_S VMLADAVAQ_U VMLADAVQ_P_S VMLADAVQ_P_U
- VMLADAVXQ_P_S VMLAQ_N_S VMLAQ_N_U VMLASQ_N_S VMLASQ_N_U
- VMLSDAVQ_P_S VMLSDAVXQ_P_S VMVNQ_M_S VMVNQ_M_U
- VNEGQ_M_S VPSELQ_S VPSELQ_U VQABSQ_M_S VQDMLAHQ_N_S
- VQDMLAHQ_N_U VQNEGQ_M_S VQRDMLADHQ_S VQRDMLADHXQ_S
- VQRDMLAHQ_N_S VQRDMLAHQ_N_U VQRDMLASHQ_N_S
- VQRDMLASHQ_N_U VQRDMLSDHQ_S VQRDMLSDHXQ_S VQRSHLQ_M_N_S
- VQRSHLQ_M_N_U VQSHLQ_M_R_S VQSHLQ_M_R_U VREV64Q_M_S
- VREV64Q_M_U VRSHLQ_M_N_S VRSHLQ_M_N_U VSHLQ_M_R_S
- VSHLQ_M_R_U VSLIQ_N_S VSLIQ_N_U VSRIQ_N_S VSRIQ_N_U
- VQDMLSDHXQ_S VQDMLSDHQ_S VQDMLADHXQ_S VQDMLADHQ_S
- VMLSDAVAXQ_S VMLSDAVAQ_S VMLADAVAXQ_S
- VCMPGEQ_M_F VCMPGTQ_M_N_F VMLSLDAVQ_P_S VRMLALDAVHAXQ_S
- VMLSLDAVXQ_P_S VFMAQ_F VMLSLDAVAQ_S VQSHRUNBQ_N_S
- VQRSHRUNTQ_N_S VCMLAQ_F VMINNMAQ_M_F VFMASQ_N_F
- VDUPQ_M_N_F VCMPGTQ_M_F VCMPLTQ_M_F VRMLSLDAVHQ_P_S
- VQSHRUNTQ_N_S VABSQ_M_F VMAXNMAVQ_P_F VFMAQ_N_F
- VRMLSLDAVHXQ_P_S VREV32Q_M_F VRMLSLDAVHAQ_S
- VRMLSLDAVHAXQ_S VCMPLTQ_M_N_F VCMPNEQ_M_F VRNDAQ_M_F
- VRNDPQ_M_F VADDLVAQ_P_S VQMOVUNBQ_M_S VCMPLEQ_M_F
- VCMLAQ_ROT180_F VMLSLDAVAXQ_S VRNDXQ_M_F VFMSQ_F
- VMINNMVQ_P_F VMAXNMVQ_P_F VPSELQ_F VCMLAQ_ROT90_F
- VQMOVUNTQ_M_S VREV64Q_M_F VNEGQ_M_F VRNDMQ_M_F
- VCMPLEQ_M_N_F VCMPGEQ_M_N_F VRNDNQ_M_F VMINNMAVQ_P_F
- VCMPNEQ_M_N_F VRMLALDAVHQ_P_S VRMLALDAVHXQ_P_S
- VCMPEQQ_M_N_F VCMLAQ_ROT270_F VMAXNMAQ_M_F VRNDQ_M_F
- VMLALDAVQ_P_U VMLALDAVQ_P_S VQMOVNBQ_M_S VQMOVNBQ_M_U
- VMOVLTQ_M_U VMOVLTQ_M_S VMOVNBQ_M_U VMOVNBQ_M_S
- VRSHRNTQ_N_U VRSHRNTQ_N_S VORRQ_M_N_S VORRQ_M_N_U
- VREV32Q_M_S VREV32Q_M_U VQRSHRNTQ_N_U VQRSHRNTQ_N_S
- VMOVNTQ_M_U VMOVNTQ_M_S VMOVLBQ_M_U VMOVLBQ_M_S
- VMLALDAVAQ_S VMLALDAVAQ_U VQSHRNBQ_N_U VQSHRNBQ_N_S
- VSHRNBQ_N_U VSHRNBQ_N_S VRSHRNBQ_N_S VRSHRNBQ_N_U
- VMLALDAVXQ_P_U VMLALDAVXQ_P_S VQMOVNTQ_M_U VQMOVNTQ_M_S
- VMVNQ_M_N_U VMVNQ_M_N_S VQSHRNTQ_N_U VQSHRNTQ_N_S
- VMLALDAVAXQ_S VMLALDAVAXQ_U VSHRNTQ_N_S VSHRNTQ_N_U
- VCVTBQ_M_F16_F32 VCVTBQ_M_F32_F16 VCVTTQ_M_F16_F32
- VCVTTQ_M_F32_F16 VCVTMQ_M_S VCVTMQ_M_U VCVTNQ_M_S
- VCVTPQ_M_S VCVTPQ_M_U VCVTQ_M_N_FROM_F_S VCVTNQ_M_U
- VREV16Q_M_S VREV16Q_M_U VREV32Q_M VCVTQ_M_FROM_F_U
- VCVTQ_M_FROM_F_S VRMLALDAVHQ_P_U VADDLVAQ_P_U
- VCVTQ_M_N_FROM_F_U VQSHLUQ_M_N_S VABAVQ_P_S
- VABAVQ_P_U VSHLQ_M_S VSHLQ_M_U VSRIQ_M_N_S
- VSRIQ_M_N_U VSUBQ_M_U VSUBQ_M_S VCVTQ_M_N_TO_F_U
- VCVTQ_M_N_TO_F_S VQADDQ_M_U VQADDQ_M_S
- VRSHRQ_M_N_S VSUBQ_M_N_S VSUBQ_M_N_U VBRSRQ_M_N_S
- VSUBQ_M_N_F VBICQ_M_F VHADDQ_M_U VBICQ_M_U VBICQ_M_S
- VMULQ_M_N_U VHADDQ_M_S VORNQ_M_F VMLAQ_M_N_S VQSUBQ_M_U
- VQSUBQ_M_S VMLAQ_M_N_U VQSUBQ_M_N_U VQSUBQ_M_N_S
- VMULLTQ_INT_M_S VMULLTQ_INT_M_U VMULQ_M_N_S VMULQ_M_N_F
- VMLASQ_M_N_U VMLASQ_M_N_S VMAXQ_M_U VQRDMLAHQ_M_N_U
- VCADDQ_ROT270_M_F VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S
- VQRSHLQ_M_S VMULQ_M_F VRHADDQ_M_U VSHRQ_M_N_U
- VRHADDQ_M_S VMULQ_M_S VMULQ_M_U VQRDMLASHQ_M_N_S
- VRSHLQ_M_S VRSHLQ_M_U VRSHRQ_M_N_U VADDQ_M_N_F
- VADDQ_M_N_S VADDQ_M_N_U VQRDMLASHQ_M_N_U VMAXQ_M_S
- VQRDMLAHQ_M_N_S VORRQ_M_S VORRQ_M_U VORRQ_M_F
- VQRSHLQ_M_U VRMULHQ_M_U VRMULHQ_M_S VMINQ_M_S VMINQ_M_U
- VANDQ_M_F VANDQ_M_U VANDQ_M_S VHSUBQ_M_N_S VHSUBQ_M_N_U
- VMULHQ_M_S VMULHQ_M_U VMULLBQ_INT_M_U
- VMULLBQ_INT_M_S VCADDQ_ROT90_M_F
- VSHRQ_M_N_S VADDQ_M_U VSLIQ_M_N_U
- VQADDQ_M_N_S VBRSRQ_M_N_F VABDQ_M_F VBRSRQ_M_N_U
- VEORQ_M_F VSHLQ_M_N_S VQDMLAHQ_M_N_U VQDMLAHQ_M_N_S
- VSHLQ_M_N_U VMLADAVAQ_P_U VMLADAVAQ_P_S VSLIQ_M_N_S
- VQSHLQ_M_U VQSHLQ_M_S VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S
- VORNQ_M_U VORNQ_M_S VQSHLQ_M_N_S VQSHLQ_M_N_U VADDQ_M_S
- VHADDQ_M_N_S VADDQ_M_F VQADDQ_M_N_U VEORQ_M_S VEORQ_M_U
- VHSUBQ_M_S VHSUBQ_M_U VHADDQ_M_N_U VHCADDQ_ROT90_M_S
- VQRDMLSDHQ_M_S VQRDMLSDHXQ_M_S VQRDMLADHXQ_M_S
- VQDMULHQ_M_S VMLADAVAXQ_P_S VQDMLADHXQ_M_S
- VQRDMULHQ_M_S VMLSDAVAXQ_P_S VQDMULHQ_M_N_S
- VHCADDQ_ROT270_M_S VQDMLSDHQ_M_S VQDMLSDHXQ_M_S
- VMLSDAVAQ_P_S VQRDMLADHQ_M_S VQDMLADHQ_M_S
- VMLALDAVAQ_P_U VMLALDAVAQ_P_S VMLALDAVAXQ_P_U
- VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S VQRSHRNTQ_M_N_S
- VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S VQSHRNTQ_M_N_S
- VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S VRSHRNTQ_M_N_U
- VSHLLBQ_M_N_U VSHLLBQ_M_N_S VSHLLTQ_M_N_U VSHLLTQ_M_N_S
- VSHRNBQ_M_N_S VSHRNBQ_M_N_U VSHRNTQ_M_N_S VSHRNTQ_M_N_U
- VMLALDAVAXQ_P_S VQRSHRNTQ_M_N_U VQSHRNTQ_M_N_U
- VRSHRNTQ_M_N_S VQRDMULHQ_M_N_S VRMLALDAVHAQ_P_S
- VMLSLDAVAQ_P_S VMLSLDAVAXQ_P_S VMULLBQ_POLY_M_P
- VMULLTQ_POLY_M_P VQDMULLBQ_M_N_S VQDMULLBQ_M_S
- VQDMULLTQ_M_N_S VQDMULLTQ_M_S VQRSHRUNBQ_M_N_S
- VQRSHRUNTQ_M_N_SVQSHRUNBQ_M_N_S VQSHRUNTQ_M_N_S
- VRMLALDAVHAQ_P_U VRMLALDAVHAXQ_P_S VRMLSLDAVHAQ_P_S
- VRMLSLDAVHAXQ_P_S VQRSHRUNTQ_M_N_S VQSHRUNBQ_M_N_S
- VCMLAQ_M_F VCMLAQ_ROT180_M_F VCMLAQ_ROT270_M_F
- VCMLAQ_ROT90_M_F VCMULQ_M_F VCMULQ_ROT180_M_F
- VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F VFMAQ_M_F
- VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F
- VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U
- VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U VLDRBQGO_S
- VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U
- VLD1Q_F VLD1Q_S VLD1Q_U VLDRHQ_F VLDRHQGO_S
- VLDRHQGO_U VLDRHQGSO_S VLDRHQGSO_U VLDRHQ_S VLDRHQ_U
- VLDRWQ_F VLDRWQ_S VLDRWQ_U VLDRDQGB_S VLDRDQGB_U
- VLDRDQGO_S VLDRDQGO_U VLDRDQGSO_S VLDRDQGSO_U
- VLDRHQGO_F VLDRHQGSO_F VLDRWQGB_F VLDRWQGO_F
- VLDRWQGO_S VLDRWQGO_U VLDRWQGSO_F VLDRWQGSO_S
- VLDRWQGSO_U VSTRHQ_F VST1Q_S VST1Q_U VSTRHQSO_S
- VSTRHQSO_U VSTRHQSSO_S VSTRHQSSO_U VSTRHQ_S
- VSTRHQ_U VSTRWQ_S VSTRWQ_U VSTRWQ_F VST1Q_F VSTRDQSB_S
- VSTRDQSB_U VSTRDQSO_S VSTRDQSO_U VSTRDQSSO_S
- VSTRDQSSO_U VSTRWQSO_S VSTRWQSO_U VSTRWQSSO_S
- VSTRWQSSO_U VSTRHQSO_F VSTRHQSSO_F VSTRWQSB_F
- VSTRWQSO_F VSTRWQSSO_F VDDUPQ VDDUPQ_M VDWDUPQ
- VDWDUPQ_M VIDUPQ VIDUPQ_M VIWDUPQ VIWDUPQ_M
- VSTRWQSBWB_S VSTRWQSBWB_U VLDRWQGBWB_S VLDRWQGBWB_U
- VSTRWQSBWB_F VLDRWQGBWB_F VSTRDQSBWB_S VSTRDQSBWB_U
- VLDRDQGBWB_S VLDRDQGBWB_U VADCQ_U VADCQ_M_U VADCQ_S
- VADCQ_M_S VSBCIQ_U VSBCIQ_S VSBCIQ_M_U VSBCIQ_M_S
- VSBCQ_U VSBCQ_S VSBCQ_M_U VSBCQ_M_S VADCIQ_U VADCIQ_M_U
- VADCIQ_S VADCIQ_M_S VLD2Q VLD4Q VST2Q SRSHRL SRSHR
- URSHR URSHRL SQRSHR UQRSHL UQRSHLL_64 VSHLCQ_M_U
- UQRSHLL_48 SQRSHRL_64 SQRSHRL_48 VSHLCQ_M_S])
-
-(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI")
- (V4SF "V4SI")])
-
-(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
- (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u")
- (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s")
- (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u")
- (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s")
- (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u")
- (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s")
- (VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")
- (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s")
- (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u")
- (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
- (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")
- (VCVTQ_N_TO_F_S "s") (VCVTQ_N_TO_F_U "u")
- (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s")
- (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u")
- (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s")
- (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s")
- (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s")
- (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u")
- (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VANDQ_S "s")
- (VANDQ_U "u") (VBICQ_S "s") (VBICQ_U "u")
- (VBRSRQ_N_S "s") (VBRSRQ_N_U "u") (VCADDQ_ROT270_S "s")
- (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s")
- (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u")
- (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s")
- (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u")
- (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
- (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u")
- (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
- (VMAXVQ_S "s") (VMAXVQ_U "u") (VMINQ_S "s") (VMINQ_U "u")
- (VMINVQ_S "s") (VMINVQ_U "u") (VMLADAVQ_S "s")
- (VMLADAVQ_U "u") (VMULHQ_S "s") (VMULHQ_U "u")
- (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s")
- (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u")
- (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s")
- (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s")
- (VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u")
- (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s")
- (VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u")
- (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s")
- (VQSHLQ_U "u") (VQSUBQ_N_S "s") (VQSUBQ_N_U "u")
- (VQSUBQ_S "s") (VQSUBQ_U "u") (VRHADDQ_S "s")
- (VRHADDQ_U "u") (VRMULHQ_S "s") (VRMULHQ_U "u")
- (VRSHLQ_N_S "s") (VRSHLQ_N_U "u") (VRSHLQ_S "s")
- (VRSHLQ_U "u") (VRSHRQ_N_S "s") (VRSHRQ_N_U "u")
- (VSHLQ_N_S "s") (VSHLQ_N_U "u") (VSHLQ_R_S "s")
- (VSHLQ_R_U "u") (VSUBQ_N_S "s") (VSUBQ_N_U "u")
- (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s")
- (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u")
- (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u")
- (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s")
- (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u")
- (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u")
- (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s")
- (VQMOVNTQ_U "u") (VSHLLBQ_N_U "u") (VSHLLBQ_N_S "s")
- (VSHLLTQ_N_U "u") (VSHLLTQ_N_S "s") (VRMLALDAVHQ_U "u")
- (VRMLALDAVHQ_S "s") (VBICQ_M_N_S "s") (VBICQ_M_N_U "u")
- (VCVTAQ_M_S "s") (VCVTAQ_M_U "u") (VCVTQ_M_TO_F_S "s")
- (VCVTQ_M_TO_F_U "u") (VQRSHRNBQ_N_S "s")
- (VQRSHRNBQ_N_U "u") (VABAVQ_S "s") (VABAVQ_U "u")
- (VRMLALDAVHAQ_U "u") (VRMLALDAVHAQ_S "s") (VSHLCQ_S "s")
- (VSHLCQ_U "u") (VADDVAQ_P_S "s") (VADDVAQ_P_U "u")
- (VCLZQ_M_S "s") (VCLZQ_M_U "u") (VCMPEQQ_M_N_S "s")
- (VCMPEQQ_M_N_U "u") (VCMPEQQ_M_S "s") (VCMPEQQ_M_U "u")
- (VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u") (VCMPNEQ_M_S "s")
- (VCMPNEQ_M_U "u") (VDUPQ_M_N_S "s") (VDUPQ_M_N_U "u")
- (VMAXVQ_P_S "s") (VMAXVQ_P_U "u") (VMINVQ_P_S "s")
- (VMINVQ_P_U "u") (VMLADAVAQ_S "s") (VMLADAVAQ_U "u")
- (VMLADAVQ_P_S "s") (VMLADAVQ_P_U "u") (VMLAQ_N_S "s")
- (VMLAQ_N_U "u") (VMLASQ_N_S "s") (VMLASQ_N_U "u")
- (VMVNQ_M_S "s") (VMVNQ_M_U "u") (VPSELQ_S "s")
- (VPSELQ_U "u") (VQDMLAHQ_N_S "s") (VQDMLAHQ_N_U "u")
- (VQRDMLAHQ_N_S "s") (VQRDMLAHQ_N_U "u")
- (VQRDMLASHQ_N_S "s") (VQRDMLASHQ_N_U "u")
- (VQRSHLQ_M_N_S "s") (VQRSHLQ_M_N_U "u")
- (VQSHLQ_M_R_S "s") (VQSHLQ_M_R_U "u") (VSRIQ_N_S "s")
- (VREV64Q_M_S "s") (VREV64Q_M_U "u") (VSRIQ_N_U "u")
- (VRSHLQ_M_N_S "s") (VRSHLQ_M_N_U "u") (VSHLQ_M_R_S "s")
- (VSHLQ_M_R_U "u") (VSLIQ_N_S "s") (VSLIQ_N_U "u")
- (VMLALDAVQ_P_S "s") (VQMOVNBQ_M_S "s") (VMOVLTQ_M_S "s")
- (VMOVNBQ_M_S "s") (VRSHRNTQ_N_S "s") (VORRQ_M_N_S "s")
- (VREV32Q_M_S "s") (VQRSHRNTQ_N_S "s") (VMOVNTQ_M_S "s")
- (VMOVLBQ_M_S "s") (VMLALDAVAQ_S "s") (VQSHRNBQ_N_S "s")
- (VSHRNBQ_N_S "s") (VRSHRNBQ_N_S "s") (VMLALDAVXQ_P_S "s")
- (VQMOVNTQ_M_S "s") (VMVNQ_M_N_S "s") (VQSHRNTQ_N_S "s")
- (VMLALDAVAXQ_S "s") (VSHRNTQ_N_S "s") (VMLALDAVQ_P_U "u")
- (VQMOVNBQ_M_U "u") (VMOVLTQ_M_U "u") (VMOVNBQ_M_U "u")
- (VRSHRNTQ_N_U "u") (VORRQ_M_N_U "u") (VREV32Q_M_U "u")
- (VREV16Q_M_S "s") (VREV16Q_M_U "u")
- (VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u")
- (VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u")
- (VRSHRNBQ_N_U "u") (VMLALDAVXQ_P_U "u")
- (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VMLALDAVAXQ_U "u")
- (VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s")
- (VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u")
- (VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s")
- (VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s")
- (VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u")
- (VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u")
- (VCVTQ_M_N_FROM_F_S "s") (VABAVQ_P_U "u")
- (VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u")
- (VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s")
- (VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s")
- (VCVTQ_M_N_TO_F_U "u") (VADDQ_M_N_U "u")
- (VSHLQ_M_N_S "s") (VMAXQ_M_U "u") (VHSUBQ_M_N_U "u")
- (VMULQ_M_N_S "s") (VQSHLQ_M_U "u") (VRHADDQ_M_S "s")
- (VEORQ_M_U "u") (VSHRQ_M_N_U "u") (VCADDQ_ROT90_M_U "u")
- (VMLADAVAQ_P_U "u") (VEORQ_M_S "s") (VBRSRQ_M_N_S "s")
- (VMULQ_M_U "u") (VQRDMLAHQ_M_N_S "s") (VHSUBQ_M_N_S "s")
- (VQRSHLQ_M_S "s") (VMULQ_M_N_U "u")
- (VMULQ_M_S "s") (VQSHLQ_M_N_U "u") (VSLIQ_M_N_U "u")
- (VMLADAVAQ_P_S "s") (VQRSHLQ_M_U "u")
- (VMULLBQ_INT_M_U "u") (VSHLQ_M_N_U "u") (VQSUBQ_M_U "u")
- (VQRDMLASHQ_M_N_U "u") (VRSHRQ_M_N_S "s")
- (VORNQ_M_S "s") (VCADDQ_ROT270_M_S "s") (VRHADDQ_M_U "u")
- (VRSHRQ_M_N_U "u") (VMLASQ_M_N_U "u") (VHSUBQ_M_U "u")
- (VQSUBQ_M_N_S "s") (VMULLTQ_INT_M_S "s")
- (VORRQ_M_S "s") (VQDMLAHQ_M_N_U "u") (VRSHLQ_M_S "s")
- (VHADDQ_M_U "u") (VHADDQ_M_N_S "s") (VMULLTQ_INT_M_U "u")
- (VORRQ_M_U "u") (VHADDQ_M_S "s") (VHADDQ_M_N_U "u")
- (VQDMLAHQ_M_N_S "s") (VMAXQ_M_S "s") (VORNQ_M_U "u")
- (VCADDQ_ROT270_M_U "u") (VQADDQ_M_U "u")
- (VQRDMLASHQ_M_N_S "s") (VBICQ_M_U "u") (VMINQ_M_U "u")
- (VSUBQ_M_N_S "s") (VMULLBQ_INT_M_S "s") (VQSUBQ_M_S "s")
- (VCADDQ_ROT90_M_S "s") (VRMULHQ_M_S "s") (VANDQ_M_U "u")
- (VMULHQ_M_S "s") (VADDQ_M_S "s") (VQRDMLAHQ_M_N_U "u")
- (VMLASQ_M_N_S "s") (VHSUBQ_M_S "s") (VRMULHQ_M_U "u")
- (VQADDQ_M_N_S "s") (VSHRQ_M_N_S "s") (VANDQ_M_S "s")
- (VABDQ_M_U "u") (VQSHLQ_M_S "s") (VABDQ_M_S "s")
- (VSUBQ_M_N_U "u") (VMLAQ_M_N_S "s") (VBRSRQ_M_N_U "u")
- (VADDQ_M_U "u") (VRSHLQ_M_U "u") (VSLIQ_M_N_S "s")
- (VQADDQ_M_N_U "u") (VADDQ_M_N_S "s") (VQSUBQ_M_N_U "u")
- (VMLAQ_M_N_U "u") (VMINQ_M_S "s") (VMULHQ_M_U "u")
- (VQADDQ_M_S "s") (VBICQ_M_S "s") (VQSHLQ_M_N_S "s")
- (VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u")
- (VSHRNTQ_M_N_U "u") (VSHRNTQ_M_N_S "s")
- (VSHRNBQ_M_N_S "s") (VSHRNBQ_M_N_U "u")
- (VSHLLTQ_M_N_S "s") (VSHLLTQ_M_N_U "u")
- (VSHLLBQ_M_N_S "s") (VSHLLBQ_M_N_U "u")
- (VRSHRNTQ_M_N_S "s") (VRSHRNTQ_M_N_U "u")
- (VRSHRNBQ_M_N_U "u") (VRSHRNBQ_M_N_S "s")
- (VQSHRNTQ_M_N_U "u") (VQSHRNTQ_M_N_S "s")
- (VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u")
- (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u")
- (VQRSHRNBQ_M_N_S "s") (VQRSHRNBQ_M_N_U "u")
- (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u")
- (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u")
- (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s")
- (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")
- (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s")
- (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")
- (VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s")
- (VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U "u")
- (VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s")
- (VLDRWQ_U "u") (VLDRDQGB_S "s") (VLDRDQGB_U "u")
- (VLDRDQGO_S "s") (VLDRDQGO_U "u") (VLDRDQGSO_S "s")
- (VLDRDQGSO_U "u") (VLDRWQGO_S "s") (VLDRWQGO_U "u")
- (VLDRWQGSO_S "s") (VLDRWQGSO_U "u") (VST1Q_S "s")
- (VST1Q_U "u") (VSTRHQSO_S "s") (VSTRHQSO_U "u")
- (VSTRHQSSO_S "s") (VSTRHQSSO_U "u") (VSTRHQ_S "s")
- (VSTRHQ_U "u") (VSTRWQ_S "s") (VSTRWQ_U "u")
- (VSTRDQSB_S "s") (VSTRDQSB_U "u") (VSTRDQSO_S "s")
- (VSTRDQSO_U "u") (VSTRDQSSO_S "s") (VSTRDQSSO_U "u")
- (VSTRWQSO_U "u") (VSTRWQSO_S "s") (VSTRWQSSO_U "u")
- (VSTRWQSSO_S "s") (VSTRWQSBWB_S "s") (VSTRWQSBWB_U "u")
- (VLDRWQGBWB_S "s") (VLDRWQGBWB_U "u") (VLDRDQGBWB_S "s")
- (VLDRDQGBWB_U "u") (VSTRDQSBWB_S "s") (VADCQ_M_S "s")
- (VSTRDQSBWB_U "u") (VSBCQ_U "u") (VSBCQ_M_U "u")
- (VSBCQ_S "s") (VSBCQ_M_S "s") (VSBCIQ_U "u")
- (VSBCIQ_M_U "u") (VSBCIQ_S "s") (VSBCIQ_M_S "s")
- (VADCQ_U "u") (VADCQ_M_U "u") (VADCQ_S "s")
- (VADCIQ_U "u") (VADCIQ_M_U "u") (VADCIQ_S "s")
- (VADCIQ_M_S "s") (SQRSHRL_64 "64") (SQRSHRL_48 "48")
- (UQRSHLL_64 "64") (UQRSHLL_48 "48") (VSHLCQ_M_S "s")
- (VSHLCQ_M_U "u")])
-
-(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
- (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
- (VCTP32Q_M "32") (VCTP64Q_M "64")])
-(define_mode_attr MVE_pred2 [(V16QI "mve_imm_8") (V8HI "mve_imm_16")
- (V4SI "mve_imm_32")
- (V8HF "mve_imm_16") (V4SF "mve_imm_32")])
-(define_mode_attr MVE_constraint2 [(V16QI "Rb") (V8HI "Rd") (V4SI "Rf")
- (V8HF "Rd") (V4SF "Rf")])
-(define_mode_attr MVE_LANES [(V16QI "16") (V8HI "8") (V4SI "4")])
-(define_mode_attr MVE_constraint [ (V16QI "Ra") (V8HI "Rc") (V4SI "Re")])
-(define_mode_attr MVE_pred [ (V16QI "mve_imm_7") (V8HI "mve_imm_15")
- (V4SI "mve_imm_31")])
-(define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")])
-(define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")])
-(define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")])
-(define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")])
-(define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")])
-(define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")])
-(define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI "h") (V4SI "w") (V8HF "h")
- (V4SF "w")])
-(define_mode_attr V_extr_elem [(V16QI "u8") (V8HI "u16") (V4SI "32")
- (V8HF "u16") (V4SF "32")])
-
-(define_mode_attr earlyclobber_32 [(V16QI "=w") (V8HI "=w") (V4SI "=&w")
- (V8HF "=w") (V4SF "=&w")])
-
-(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
-(define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
-(define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
-(define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U])
-(define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S])
-(define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S])
-(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S])
-(define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S])
-(define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S])
-(define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S])
-(define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S])
-(define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U])
-(define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S])
-(define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U])
-(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
-(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
-(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
-(define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
-(define_int_iterator VCTPQ_M [VCTP8Q_M VCTP16Q_M VCTP32Q_M VCTP64Q_M])
-(define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U])
-(define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S])
-(define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U])
-(define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U])
-(define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U])
-(define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S])
-(define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U])
-(define_int_iterator VABDQ [VABDQ_S VABDQ_U])
-(define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U])
-(define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U])
-(define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S])
-(define_int_iterator VANDQ [VANDQ_U VANDQ_S])
-(define_int_iterator VBICQ [VBICQ_S VBICQ_U])
-(define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S])
-(define_int_iterator VCADDQ_ROT270 [VCADDQ_ROT270_S VCADDQ_ROT270_U])
-(define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S])
-(define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
-(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
-(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
-(define_int_iterator VEORQ [VEORQ_U VEORQ_S])
-(define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
-(define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
-(define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
-(define_int_iterator VHSUBQ_N [VHSUBQ_N_U VHSUBQ_N_S])
-(define_int_iterator VMAXQ [VMAXQ_U VMAXQ_S])
-(define_int_iterator VMAXVQ [VMAXVQ_U VMAXVQ_S])
-(define_int_iterator VMINQ [VMINQ_S VMINQ_U])
-(define_int_iterator VMINVQ [VMINVQ_U VMINVQ_S])
-(define_int_iterator VMLADAVQ [VMLADAVQ_U VMLADAVQ_S])
-(define_int_iterator VMULHQ [VMULHQ_S VMULHQ_U])
-(define_int_iterator VMULLBQ_INT [VMULLBQ_INT_U VMULLBQ_INT_S])
-(define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S])
-(define_int_iterator VMULQ [VMULQ_U VMULQ_S])
-(define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S])
-(define_int_iterator VORNQ [VORNQ_U VORNQ_S])
-(define_int_iterator VORRQ [VORRQ_S VORRQ_U])
-(define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S])
-(define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U])
-(define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U])
-(define_int_iterator VQRSHLQ_N [VQRSHLQ_N_S VQRSHLQ_N_U])
-(define_int_iterator VQSHLQ [VQSHLQ_S VQSHLQ_U])
-(define_int_iterator VQSHLQ_N [VQSHLQ_N_S VQSHLQ_N_U])
-(define_int_iterator VQSHLQ_R [VQSHLQ_R_U VQSHLQ_R_S])
-(define_int_iterator VQSUBQ [VQSUBQ_U VQSUBQ_S])
-(define_int_iterator VQSUBQ_N [VQSUBQ_N_S VQSUBQ_N_U])
-(define_int_iterator VRHADDQ [VRHADDQ_S VRHADDQ_U])
-(define_int_iterator VRMULHQ [VRMULHQ_S VRMULHQ_U])
-(define_int_iterator VRSHLQ [VRSHLQ_S VRSHLQ_U])
-(define_int_iterator VRSHLQ_N [VRSHLQ_N_U VRSHLQ_N_S])
-(define_int_iterator VRSHRQ_N [VRSHRQ_N_S VRSHRQ_N_U])
-(define_int_iterator VSHLQ_N [VSHLQ_N_U VSHLQ_N_S])
-(define_int_iterator VSHLQ_R [VSHLQ_R_S VSHLQ_R_U])
-(define_int_iterator VSUBQ [VSUBQ_S VSUBQ_U])
-(define_int_iterator VSUBQ_N [VSUBQ_N_S VSUBQ_N_U])
-(define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U])
-(define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U])
-(define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S])
-(define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S])
-(define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S])
-(define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U])
-(define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S])
-(define_int_iterator VQMOVNBQ [VQMOVNBQ_U VQMOVNBQ_S])
-(define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S])
-(define_int_iterator VSHLLBQ_N [VSHLLBQ_N_S VSHLLBQ_N_U])
-(define_int_iterator VSHLLTQ_N [VSHLLTQ_N_U VSHLLTQ_N_S])
-(define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S])
-(define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U])
-(define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U])
-(define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U])
-(define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S])
-(define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U])
-(define_int_iterator VSHLCQ [VSHLCQ_S VSHLCQ_U])
-(define_int_iterator VRMLALDAVHAQ [VRMLALDAVHAQ_S VRMLALDAVHAQ_U])
-(define_int_iterator VADDVAQ_P [VADDVAQ_P_S VADDVAQ_P_U])
-(define_int_iterator VCLZQ_M [VCLZQ_M_S VCLZQ_M_U])
-(define_int_iterator VCMPEQQ_M_N [VCMPEQQ_M_N_S VCMPEQQ_M_N_U])
-(define_int_iterator VCMPEQQ_M [VCMPEQQ_M_S VCMPEQQ_M_U])
-(define_int_iterator VCMPNEQ_M_N [VCMPNEQ_M_N_S VCMPNEQ_M_N_U])
-(define_int_iterator VCMPNEQ_M [VCMPNEQ_M_S VCMPNEQ_M_U])
-(define_int_iterator VDUPQ_M_N [VDUPQ_M_N_S VDUPQ_M_N_U])
-(define_int_iterator VMAXVQ_P [VMAXVQ_P_S VMAXVQ_P_U])
-(define_int_iterator VMINVQ_P [VMINVQ_P_S VMINVQ_P_U])
-(define_int_iterator VMLADAVAQ [VMLADAVAQ_S VMLADAVAQ_U])
-(define_int_iterator VMLADAVQ_P [VMLADAVQ_P_S VMLADAVQ_P_U])
-(define_int_iterator VMLAQ_N [VMLAQ_N_S VMLAQ_N_U])
-(define_int_iterator VMLASQ_N [VMLASQ_N_S VMLASQ_N_U])
-(define_int_iterator VMVNQ_M [VMVNQ_M_S VMVNQ_M_U])
-(define_int_iterator VPSELQ [VPSELQ_S VPSELQ_U])
-(define_int_iterator VQDMLAHQ_N [VQDMLAHQ_N_S VQDMLAHQ_N_U])
-(define_int_iterator VQRDMLAHQ_N [VQRDMLAHQ_N_S VQRDMLAHQ_N_U])
-(define_int_iterator VQRDMLASHQ_N [VQRDMLASHQ_N_S VQRDMLASHQ_N_U])
-(define_int_iterator VQRSHLQ_M_N [VQRSHLQ_M_N_S VQRSHLQ_M_N_U])
-(define_int_iterator VQSHLQ_M_R [VQSHLQ_M_R_S VQSHLQ_M_R_U])
-(define_int_iterator VREV64Q_M [VREV64Q_M_S VREV64Q_M_U])
-(define_int_iterator VRSHLQ_M_N [VRSHLQ_M_N_S VRSHLQ_M_N_U])
-(define_int_iterator VSHLQ_M_R [VSHLQ_M_R_S VSHLQ_M_R_U])
-(define_int_iterator VSLIQ_N [VSLIQ_N_S VSLIQ_N_U])
-(define_int_iterator VSRIQ_N [VSRIQ_N_S VSRIQ_N_U])
-(define_int_iterator VMLALDAVQ_P [VMLALDAVQ_P_U VMLALDAVQ_P_S])
-(define_int_iterator VQMOVNBQ_M [VQMOVNBQ_M_S VQMOVNBQ_M_U])
-(define_int_iterator VMOVLTQ_M [VMOVLTQ_M_U VMOVLTQ_M_S])
-(define_int_iterator VMOVNBQ_M [VMOVNBQ_M_U VMOVNBQ_M_S])
-(define_int_iterator VRSHRNTQ_N [VRSHRNTQ_N_U VRSHRNTQ_N_S])
-(define_int_iterator VORRQ_M_N [VORRQ_M_N_S VORRQ_M_N_U])
-(define_int_iterator VREV32Q_M [VREV32Q_M_S VREV32Q_M_U])
-(define_int_iterator VREV16Q_M [VREV16Q_M_S VREV16Q_M_U])
-(define_int_iterator VQRSHRNTQ_N [VQRSHRNTQ_N_U VQRSHRNTQ_N_S])
-(define_int_iterator VMOVNTQ_M [VMOVNTQ_M_U VMOVNTQ_M_S])
-(define_int_iterator VMOVLBQ_M [VMOVLBQ_M_U VMOVLBQ_M_S])
-(define_int_iterator VMLALDAVAQ [VMLALDAVAQ_S VMLALDAVAQ_U])
-(define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S])
-(define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S])
-(define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U])
-(define_int_iterator VMLALDAVXQ_P [VMLALDAVXQ_P_U VMLALDAVXQ_P_S])
-(define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S])
-(define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S])
-(define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S])
-(define_int_iterator VMLALDAVAXQ [VMLALDAVAXQ_S VMLALDAVAXQ_U])
-(define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U])
-(define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U])
-(define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U])
-(define_int_iterator VCVTPQ_M [VCVTPQ_M_S VCVTPQ_M_U])
-(define_int_iterator VCVTQ_M_N_FROM_F [VCVTQ_M_N_FROM_F_S VCVTQ_M_N_FROM_F_U])
-(define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S])
-(define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U])
-(define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S])
-(define_int_iterator VABAVQ_P [VABAVQ_P_S VABAVQ_P_U])
-(define_int_iterator VSHLQ_M [VSHLQ_M_S VSHLQ_M_U])
-(define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U])
-(define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S])
-(define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S])
-(define_int_iterator VHSUBQ_M [VHSUBQ_M_S VHSUBQ_M_U])
-(define_int_iterator VSLIQ_M_N [VSLIQ_M_N_U VSLIQ_M_N_S])
-(define_int_iterator VRSHLQ_M [VRSHLQ_M_S VRSHLQ_M_U])
-(define_int_iterator VMINQ_M [VMINQ_M_S VMINQ_M_U])
-(define_int_iterator VMULLBQ_INT_M [VMULLBQ_INT_M_U VMULLBQ_INT_M_S])
-(define_int_iterator VMULHQ_M [VMULHQ_M_S VMULHQ_M_U])
-(define_int_iterator VMULQ_M [VMULQ_M_S VMULQ_M_U])
-(define_int_iterator VHSUBQ_M_N [VHSUBQ_M_N_S VHSUBQ_M_N_U])
-(define_int_iterator VHADDQ_M_N [VHADDQ_M_N_S VHADDQ_M_N_U])
-(define_int_iterator VORRQ_M [VORRQ_M_S VORRQ_M_U])
-(define_int_iterator VRMULHQ_M [VRMULHQ_M_U VRMULHQ_M_S])
-(define_int_iterator VQADDQ_M [VQADDQ_M_U VQADDQ_M_S])
-(define_int_iterator VRSHRQ_M_N [VRSHRQ_M_N_S VRSHRQ_M_N_U])
-(define_int_iterator VQSUBQ_M_N [VQSUBQ_M_N_U VQSUBQ_M_N_S])
-(define_int_iterator VADDQ_M [VADDQ_M_U VADDQ_M_S])
-(define_int_iterator VORNQ_M [VORNQ_M_U VORNQ_M_S])
-(define_int_iterator VRHADDQ_M [VRHADDQ_M_U VRHADDQ_M_S])
-(define_int_iterator VQSHLQ_M [VQSHLQ_M_U VQSHLQ_M_S])
-(define_int_iterator VANDQ_M [VANDQ_M_U VANDQ_M_S])
-(define_int_iterator VBICQ_M [VBICQ_M_U VBICQ_M_S])
-(define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U])
-(define_int_iterator VCADDQ_ROT270_M [VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
-(define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S])
-(define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S])
-(define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U])
-(define_int_iterator VMAXQ_M [VMAXQ_M_S VMAXQ_M_U])
-(define_int_iterator VQSUBQ_M [VQSUBQ_M_U VQSUBQ_M_S])
-(define_int_iterator VMLASQ_M_N [VMLASQ_M_N_U VMLASQ_M_N_S])
-(define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S])
-(define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S])
-(define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S])
-(define_int_iterator VCADDQ_ROT90_M [VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S])
-(define_int_iterator VMULLTQ_INT_M [VMULLTQ_INT_M_S VMULLTQ_INT_M_U])
-(define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U])
-(define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U])
-(define_int_iterator VSUBQ_M_N [VSUBQ_M_N_S VSUBQ_M_N_U])
-(define_int_iterator VHADDQ_M [VHADDQ_M_S VHADDQ_M_U])
-(define_int_iterator VABDQ_M [VABDQ_M_S VABDQ_M_U])
-(define_int_iterator VMLAQ_M_N [VMLAQ_M_N_S VMLAQ_M_N_U])
-(define_int_iterator VQSHLQ_M_N [VQSHLQ_M_N_S VQSHLQ_M_N_U])
-(define_int_iterator VMLALDAVAQ_P [VMLALDAVAQ_P_U VMLALDAVAQ_P_S])
-(define_int_iterator VMLALDAVAXQ_P [VMLALDAVAXQ_P_U VMLALDAVAXQ_P_S])
-(define_int_iterator VQRSHRNBQ_M_N [VQRSHRNBQ_M_N_U VQRSHRNBQ_M_N_S])
-(define_int_iterator VQRSHRNTQ_M_N [VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U])
-(define_int_iterator VQSHRNBQ_M_N [VQSHRNBQ_M_N_U VQSHRNBQ_M_N_S])
-(define_int_iterator VQSHRNTQ_M_N [VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U])
-(define_int_iterator VRSHRNBQ_M_N [VRSHRNBQ_M_N_U VRSHRNBQ_M_N_S])
-(define_int_iterator VRSHRNTQ_M_N [VRSHRNTQ_M_N_U VRSHRNTQ_M_N_S])
-(define_int_iterator VSHLLBQ_M_N [VSHLLBQ_M_N_U VSHLLBQ_M_N_S])
-(define_int_iterator VSHLLTQ_M_N [VSHLLTQ_M_N_U VSHLLTQ_M_N_S])
-(define_int_iterator VSHRNBQ_M_N [VSHRNBQ_M_N_S VSHRNBQ_M_N_U])
-(define_int_iterator VSHRNTQ_M_N [VSHRNTQ_M_N_S VSHRNTQ_M_N_U])
-(define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U])
-(define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U])
-(define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U])
-(define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U])
-(define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U])
-(define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U])
-(define_int_iterator VLD1Q [VLD1Q_S VLD1Q_U])
-(define_int_iterator VLDRHGOQ [VLDRHQGO_S VLDRHQGO_U])
-(define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U])
-(define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U])
-(define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U])
-(define_int_iterator VLDRDGBQ [VLDRDQGB_S VLDRDQGB_U])
-(define_int_iterator VLDRDGOQ [VLDRDQGO_S VLDRDQGO_U])
-(define_int_iterator VLDRDGSOQ [VLDRDQGSO_S VLDRDQGSO_U])
-(define_int_iterator VLDRWGOQ [VLDRWQGO_S VLDRWQGO_U])
-(define_int_iterator VLDRWGSOQ [VLDRWQGSO_S VLDRWQGSO_U])
-(define_int_iterator VST1Q [VST1Q_S VST1Q_U])
-(define_int_iterator VSTRHSOQ [VSTRHQSO_S VSTRHQSO_U])
-(define_int_iterator VSTRHSSOQ [VSTRHQSSO_S VSTRHQSSO_U])
-(define_int_iterator VSTRHQ [VSTRHQ_S VSTRHQ_U])
-(define_int_iterator VSTRWQ [VSTRWQ_S VSTRWQ_U])
-(define_int_iterator VSTRDSBQ [VSTRDQSB_S VSTRDQSB_U])
-(define_int_iterator VSTRDSOQ [VSTRDQSO_S VSTRDQSO_U])
-(define_int_iterator VSTRDSSOQ [VSTRDQSSO_S VSTRDQSSO_U])
-(define_int_iterator VSTRWSOQ [VSTRWQSO_S VSTRWQSO_U])
-(define_int_iterator VSTRWSSOQ [VSTRWQSSO_S VSTRWQSSO_U])
-(define_int_iterator VSTRWSBWBQ [VSTRWQSBWB_S VSTRWQSBWB_U])
-(define_int_iterator VLDRWGBWBQ [VLDRWQGBWB_S VLDRWQGBWB_U])
-(define_int_iterator VSTRDSBWBQ [VSTRDQSBWB_S VSTRDQSBWB_U])
-(define_int_iterator VLDRDGBWBQ [VLDRDQGBWB_S VLDRDQGBWB_U])
-(define_int_iterator VADCIQ [VADCIQ_U VADCIQ_S])
-(define_int_iterator VADCIQ_M [VADCIQ_M_U VADCIQ_M_S])
-(define_int_iterator VSBCQ [VSBCQ_U VSBCQ_S])
-(define_int_iterator VSBCQ_M [VSBCQ_M_U VSBCQ_M_S])
-(define_int_iterator VSBCIQ [VSBCIQ_U VSBCIQ_S])
-(define_int_iterator VSBCIQ_M [VSBCIQ_M_U VSBCIQ_M_S])
-(define_int_iterator VADCQ [VADCQ_U VADCQ_S])
-(define_int_iterator VADCQ_M [VADCQ_M_U VADCQ_M_S])
-(define_int_iterator UQRSHLLQ [UQRSHLL_64 UQRSHLL_48])
-(define_int_iterator SQRSHRLQ [SQRSHRL_64 SQRSHRL_48])
-(define_int_iterator VSHLCQ_M [VSHLCQ_M_S VSHLCQ_M_U])
-
(define_insn "*mve_mov<mode>"
[(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Ux,w")
- (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,Uxi,r,Dm,w,Ul"))]
+ (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,UxUi,r,Dm,w,Ul"))]
"TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
{
if (which_alternative == 3 || which_alternative == 6)
if (which_alternative == 4 || which_alternative == 7)
{
- rtx ops[2];
- int regno = (which_alternative == 7)
- ? REGNO (operands[1]) : REGNO (operands[0]);
-
- ops[0] = operands[0];
- ops[1] = operands[1];
- if (<MODE>mode == V2DFmode || <MODE>mode == V2DImode)
- {
- if (which_alternative == 7)
- {
- ops[1] = gen_rtx_REG (DImode, regno);
- output_asm_insn ("vstr.64\t%P1, %E0",ops);
- }
- else
- {
- ops[0] = gen_rtx_REG (DImode, regno);
- output_asm_insn ("vldr.64\t%P0, %E1",ops);
- }
- }
- else if (<MODE>mode == TImode)
+ if (<MODE>mode == V2DFmode || <MODE>mode == V2DImode || <MODE>mode == TImode)
{
if (which_alternative == 7)
- output_asm_insn ("vstr.64\t%q1, %E0",ops);
+ output_asm_insn ("vstrw.32\t%q1, %E0", operands);
else
- output_asm_insn ("vldr.64\t%q0, %E1",ops);
+ output_asm_insn ("vldrw.u32\t%q0, %E1",operands);
}
else
{
if (which_alternative == 7)
- {
- ops[1] = gen_rtx_REG (TImode, regno);
- output_asm_insn ("vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0",ops);
- }
+ output_asm_insn ("vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0", operands);
else
- {
- ops[0] = gen_rtx_REG (TImode, regno);
- output_asm_insn ("vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1",ops);
- }
+ output_asm_insn ("vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1", operands);
}
return "";
}
(set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*,*")
(set_attr "neg_pool_range" "*,*,*,*,996,*,*,*,*")])
-(define_insn "*mve_mov<mode>"
- [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w")
- (vec_duplicate:MVE_types
- (match_operand:SI 1 "nonmemory_operand" "r,i")))]
+(define_insn "*mve_vdup<mode>"
+ [(set (match_operand:MVE_vecs 0 "s_register_operand" "=w")
+ (vec_duplicate:MVE_vecs
+ (match_operand:<V_elem> 1 "s_register_operand" "r")))]
"TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
-{
- if (which_alternative == 0)
- return "vdup.<V_sz_elem>\t%q0, %1";
- return "vmov.<V_sz_elem>\t%q0, %1";
-}
- [(set_attr "length" "4,4")
- (set_attr "type" "mve_move,mve_move")])
+ "vdup.<V_sz_elem>\t%q0, %1"
+ [(set_attr "length" "4")
+ (set_attr "type" "mve_move")])
;;
;; [vst4q])
(define_insn "mve_vnegq_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
- VNEGQ_F))
+ (neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vneg.f%#<V_sz_elem> %q0, %q1"
(define_insn "mve_vabsq_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
- VABSQ_F))
+ (abs:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vabs.f%#<V_sz_elem> %q0, %q1"
(define_insn "mve_vnegq_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
- VNEGQ_S))
+ (neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
"vneg.s%#<V_sz_elem> %q0, %q1"
;;
;; [vmvnq_u, vmvnq_s])
;;
-(define_insn "mve_vmvnq_<supf><mode>"
+(define_insn "mve_vmvnq_u<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
- VMVNQ))
+ (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
- "vmvn %q0, %q1"
+ "vmvn\t%q0, %q1"
[(set_attr "type" "mve_move")
])
+(define_expand "mve_vmvnq_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand")
+ (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand")))
+ ]
+ "TARGET_HAVE_MVE"
+)
;;
;; [vdupq_n_u, vdupq_n_s])
;;
;; [vclzq_u, vclzq_s])
;;
-(define_insn "mve_vclzq_<supf><mode>"
+(define_insn "@mve_vclzq_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
- VCLZQ))
+ (clz:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
"vclz.i%#<V_sz_elem> %q0, %q1"
[(set_attr "type" "mve_move")
])
+(define_expand "mve_vclzq_u<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand")
+ (clz:MVE_2 (match_operand:MVE_2 1 "s_register_operand")))
+ ]
+ "TARGET_HAVE_MVE"
+)
;;
;; [vclsq_s])
;;
;; [vaddvq_s, vaddvq_u])
;;
-(define_insn "mve_vaddvq_<supf><mode>"
+(define_insn "@mve_vaddvq_<supf><mode>"
[
(set (match_operand:SI 0 "s_register_operand" "=Te")
(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
(define_insn "mve_vabsq_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
- VABSQ_S))
+ (abs:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
"vabs.s%#<V_sz_elem>\t%q0, %q1"
[(set_attr "type" "mve_move")
])
+(define_insn "mve_vec_unpack<US>_lo_<mode>"
+ [(set (match_operand:<V_unpack> 0 "register_operand" "=w")
+ (SE:<V_unpack> (vec_select:<V_HALF>
+ (match_operand:MVE_3 1 "register_operand" "w")
+ (match_operand:MVE_3 2 "vect_par_constant_low" ""))))]
+ "TARGET_HAVE_MVE"
+ "vmovlb.<US>%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")]
+)
+
+(define_insn "mve_vec_unpack<US>_hi_<mode>"
+ [(set (match_operand:<V_unpack> 0 "register_operand" "=w")
+ (SE:<V_unpack> (vec_select:<V_HALF>
+ (match_operand:MVE_3 1 "register_operand" "w")
+ (match_operand:MVE_3 2 "vect_par_constant_high" ""))))]
+ "TARGET_HAVE_MVE"
+ "vmovlt.<US>%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")]
+)
+
;;
;; [vcvtpq_s, vcvtpq_u])
;;
;;
;; [vshrq_n_s, vshrq_n_u])
;;
+;; Version that takes an immediate as operand 2.
(define_insn "mve_vshrq_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
[(set_attr "type" "mve_move")
])
+;; Versions that take constant vectors as operand 2 (with all elements
+;; equal).
+(define_insn "mve_vshrq_n_s<mode>_imm"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (ashiftrt:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "imm_for_neon_rshift_operand" "i")))
+ ]
+ "TARGET_HAVE_MVE"
+ {
+ return neon_output_shift_immediate ("vshr", 's', &operands[2],
+ <MODE>mode,
+ VALID_NEON_QREG_MODE (<MODE>mode),
+ true);
+ }
+ [(set_attr "type" "mve_move")
+])
+(define_insn "mve_vshrq_n_u<mode>_imm"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (lshiftrt:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "imm_for_neon_rshift_operand" "i")))
+ ]
+ "TARGET_HAVE_MVE"
+ {
+ return neon_output_shift_immediate ("vshr", 'u', &operands[2],
+ <MODE>mode,
+ VALID_NEON_QREG_MODE (<MODE>mode),
+ true);
+ }
+ [(set_attr "type" "mve_move")
+])
+
;;
;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
;;
(set_attr "length""8")])
;;
-;; [vcmpneq_u, vcmpneq_s])
+;; [vcmpneq_, vcmpcsq_, vcmpeqq_, vcmpgeq_, vcmpgtq_, vcmphiq_, vcmpleq_, vcmpltq_])
;;
-(define_insn "mve_vcmpneq_<supf><mode>"
+(define_insn "@mve_vcmp<mve_cmp_op>q_<mode>"
[
(set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPNEQ))
+ (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
- "vcmp.i%#<V_sz_elem> ne, %q1, %q2"
+ "vcmp.<mve_cmp_type>%#<V_sz_elem> <mve_cmp_op>, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
-;; [vshlq_s, vshlq_u])
+;; [vcmpcsq_n_, vcmpeqq_n_, vcmpgeq_n_, vcmpgtq_n_, vcmphiq_n_, vcmpleq_n_, vcmpltq_n_, vcmpneq_n_])
;;
-(define_insn "mve_vshlq_<supf><mode>"
+(define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>"
[
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VSHLQ))
+ (set (match_operand:HI 0 "vpr_register_operand" "=Up")
+ (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:<V_elem> 2 "s_register_operand" "r")))
]
"TARGET_HAVE_MVE"
- "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
+ "vcmp.<mve_cmp_type>%#<V_sz_elem> <mve_cmp_op>, %q1, %2"
[(set_attr "type" "mve_move")
])
+;;
+;; [vshlq_s, vshlq_u])
+;; See vec-common.md
+
;;
;; [vabdq_s, vabdq_u])
;;
;;
;; [vandq_u, vandq_s])
;;
-(define_insn "mve_vandq_<supf><mode>"
+;; signed and unsigned versions are the same: define the unsigned
+;; insn, and use an expander for the signed one as we still reference
+;; both names from arm_mve.h.
+;; We use the same code as in neon.md (TODO: avoid this duplication).
+(define_insn "mve_vandq_u<mode>"
[
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VANDQ))
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w,w")
+ (and:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0")
+ (match_operand:MVE_2 2 "neon_inv_logic_op2" "w,DL")))
]
"TARGET_HAVE_MVE"
- "vand %q0, %q1, %q2"
+ "@
+ vand\t%q0, %q1, %q2
+ * return neon_output_logic_immediate (\"vand\", &operands[2], <MODE>mode, 1, VALID_NEON_QREG_MODE (<MODE>mode));"
[(set_attr "type" "mve_move")
])
+(define_expand "mve_vandq_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand")
+ (and:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
+ (match_operand:MVE_2 2 "neon_inv_logic_op2")))
+ ]
+ "TARGET_HAVE_MVE"
+)
;;
;; [vbicq_s, vbicq_u])
;;
-(define_insn "mve_vbicq_<supf><mode>"
+(define_insn "mve_vbicq_u<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VBICQ))
+ (and:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand" "w"))
+ (match_operand:MVE_2 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
- "vbic %q0, %q1, %q2"
+ "vbic\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
+(define_expand "mve_vbicq_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand")
+ (and:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand"))
+ (match_operand:MVE_2 1 "s_register_operand")))
+ ]
+ "TARGET_HAVE_MVE"
+)
+
;;
;; [vbrsrq_n_u, vbrsrq_n_s])
;;
])
;;
-;; [vcaddq_rot270_s, vcaddq_rot270_u])
+;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270])
;;
-(define_insn "mve_vcaddq_rot270_<supf><mode>"
+(define_insn "mve_vcaddq<mve_rot><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
- VCADDQ_ROT270))
- ]
- "TARGET_HAVE_MVE"
- "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #270"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcaddq_rot90_u, vcaddq_rot90_s])
-;;
-(define_insn "mve_vcaddq_rot90_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCADDQ_ROT90))
- ]
- "TARGET_HAVE_MVE"
- "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #90"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpcsq_n_u])
-;;
-(define_insn "mve_vcmpcsq_n_u<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPCSQ_N_U))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.u%#<V_sz_elem> cs, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpcsq_u])
-;;
-(define_insn "mve_vcmpcsq_u<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPCSQ_U))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.u%#<V_sz_elem> cs, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpeqq_n_s, vcmpeqq_n_u])
-;;
-(define_insn "mve_vcmpeqq_n_<supf><mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPEQQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.i%#<V_sz_elem> eq, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpeqq_u, vcmpeqq_s])
-;;
-(define_insn "mve_vcmpeqq_<supf><mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPEQQ))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.i%#<V_sz_elem> eq, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgeq_n_s])
-;;
-(define_insn "mve_vcmpgeq_n_s<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPGEQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> ge, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgeq_s])
-;;
-(define_insn "mve_vcmpgeq_s<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPGEQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> ge, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgtq_n_s])
-;;
-(define_insn "mve_vcmpgtq_n_s<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPGTQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> gt, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgtq_s])
-;;
-(define_insn "mve_vcmpgtq_s<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPGTQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> gt, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmphiq_n_u])
-;;
-(define_insn "mve_vcmphiq_n_u<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPHIQ_N_U))
+ VCADD))
]
"TARGET_HAVE_MVE"
- "vcmp.u%#<V_sz_elem> hi, %q1, %2"
+ "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #<rot>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vcmphiq_u])
-;;
-(define_insn "mve_vcmphiq_u<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPHIQ_U))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.u%#<V_sz_elem> hi, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpleq_n_s])
-;;
-(define_insn "mve_vcmpleq_n_s<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPLEQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> le, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpleq_s])
-;;
-(define_insn "mve_vcmpleq_s<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPLEQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> le, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpltq_n_s])
-;;
-(define_insn "mve_vcmpltq_n_s<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPLTQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> lt, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpltq_s])
-;;
-(define_insn "mve_vcmpltq_s<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VCMPLTQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vcmp.s%#<V_sz_elem> lt, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
+;; Auto vectorizer pattern for int vcadd
+(define_expand "cadd<rot><mode>3"
+ [(set (match_operand:MVE_2 0 "register_operand")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "register_operand")
+ (match_operand:MVE_2 2 "register_operand")]
+ VCADD))]
+ "TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN"
+)
;;
-;; [vcmpneq_n_u, vcmpneq_n_s])
+;; [veorq_u, veorq_s])
;;
-(define_insn "mve_vcmpneq_n_<supf><mode>"
+(define_insn "mve_veorq_u<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPNEQ_N))
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
- "vcmp.i%#<V_sz_elem> ne, %q1, %2"
+ "veor\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
-
-;;
-;; [veorq_u, veorq_s])
-;;
-(define_insn "mve_veorq_<supf><mode>"
+(define_expand "mve_veorq_s<mode>"
[
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VEORQ))
+ (set (match_operand:MVE_2 0 "s_register_operand")
+ (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
+ (match_operand:MVE_2 2 "s_register_operand")))
]
"TARGET_HAVE_MVE"
- "veor %q0, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
+)
;;
;; [vhaddq_n_u, vhaddq_n_s])
;;
;; [vhaddq_s, vhaddq_u])
;;
-(define_insn "mve_vhaddq_<supf><mode>"
+(define_insn "@mve_vhaddq_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
;;
;; [vmaxq_u, vmaxq_s])
;;
-(define_insn "mve_vmaxq_<supf><mode>"
+(define_insn "mve_vmaxq_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VMAXQ))
+ (smax:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "s_register_operand" "w")))
+ ]
+ "TARGET_HAVE_MVE"
+ "vmax.%#<V_s_elem>\t%q0, %q1, %q2"
+ [(set_attr "type" "mve_move")
+])
+
+(define_insn "mve_vmaxq_u<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (umax:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
- "vmax.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
+ "vmax.%#<V_u_elem>\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
;; [vminq_s, vminq_u])
;;
-(define_insn "mve_vminq_<supf><mode>"
+(define_insn "mve_vminq_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VMINQ))
+ (smin:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
- "vmin.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
+ "vmin.%#<V_s_elem>\t%q0, %q1, %q2"
+ [(set_attr "type" "mve_move")
+])
+
+(define_insn "mve_vminq_u<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (umin:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "s_register_operand" "w")))
+ ]
+ "TARGET_HAVE_MVE"
+ "vmin.%#<V_u_elem>\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
[(set_attr "type" "mve_move")
])
+(define_insn "mve_vmulq<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (mult:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "s_register_operand" "w")))
+ ]
+ "TARGET_HAVE_MVE"
+ "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2"
+ [(set_attr "type" "mve_move")
+])
+
;;
;; [vornq_u, vornq_s])
;;
-(define_insn "mve_vornq_<supf><mode>"
+(define_insn "mve_vornq_s<mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VORNQ))
+ (ior:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand" "w"))
+ (match_operand:MVE_2 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
- "vorn %q0, %q1, %q2"
+ "vorn\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
+(define_expand "mve_vornq_u<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand")
+ (ior:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand"))
+ (match_operand:MVE_2 1 "s_register_operand")))
+ ]
+ "TARGET_HAVE_MVE"
+)
+
;;
;; [vorrq_s, vorrq_u])
;;
-(define_insn "mve_vorrq_<supf><mode>"
+;; signed and unsigned versions are the same: define the unsigned
+;; insn, and use an expander for the signed one as we still reference
+;; both names from arm_mve.h.
+;; We use the same code as in neon.md (TODO: avoid this duplication).
+(define_insn "mve_vorrq_s<mode>"
[
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VORRQ))
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w,w")
+ (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0")
+ (match_operand:MVE_2 2 "neon_logic_op2" "w,Dl")))
]
"TARGET_HAVE_MVE"
- "vorr %q0, %q1, %q2"
+ "@
+ vorr\t%q0, %q1, %q2
+ * return neon_output_logic_immediate (\"vorr\", &operands[2], <MODE>mode, 0, VALID_NEON_QREG_MODE (<MODE>mode));"
[(set_attr "type" "mve_move")
])
+(define_expand "mve_vorrq_u<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand")
+ (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
+ (match_operand:MVE_2 2 "neon_logic_op2")))
+ ]
+ "TARGET_HAVE_MVE"
+)
;;
;; [vqaddq_n_s, vqaddq_n_u])
;;
;; [vrhaddq_s, vrhaddq_u])
;;
-(define_insn "mve_vrhaddq_<supf><mode>"
+(define_insn "@mve_vrhaddq_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
;; [vsubq_s, vsubq_u])
;;
(define_insn "mve_vsubq_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VSUBQ))
- ]
- "TARGET_HAVE_MVE"
- "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vabdq_f])
-;;
-(define_insn "mve_vabdq_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VABDQ_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vabd.f%#<V_sz_elem> %q0, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vaddlvaq_s vaddlvaq_u])
-;;
-(define_insn "mve_vaddlvaq_<supf>v4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
- (match_operand:V4SI 2 "s_register_operand" "w")]
- VADDLVAQ))
- ]
- "TARGET_HAVE_MVE"
- "vaddlva.<supf>32 %Q0, %R0, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vaddq_n_f])
-;;
-(define_insn "mve_vaddq_n_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VADDQ_N_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vadd.f%#<V_sz_elem> %q0, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vandq_f])
-;;
-(define_insn "mve_vandq_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VANDQ_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vand %q0, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vbicq_f])
-;;
-(define_insn "mve_vbicq_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VBICQ_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vbic %q0, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vbicq_n_s, vbicq_n_u])
-;;
-(define_insn "mve_vbicq_n_<supf><mode>"
- [
- (set (match_operand:MVE_5 0 "s_register_operand" "=w")
- (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
- (match_operand:SI 2 "immediate_operand" "i")]
- VBICQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vbic.i%#<V_sz_elem> %q0, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcaddq_rot270_f])
-;;
-(define_insn "mve_vcaddq_rot270_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VCADDQ_ROT270_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #270"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcaddq_rot90_f])
-;;
-(define_insn "mve_vcaddq_rot90_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VCADDQ_ROT90_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #90"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpeqq_f])
-;;
-(define_insn "mve_vcmpeqq_f<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VCMPEQQ_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmp.f%#<V_sz_elem> eq, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpeqq_n_f])
-;;
-(define_insn "mve_vcmpeqq_n_f<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPEQQ_N_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmp.f%#<V_sz_elem> eq, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgeq_f])
-;;
-(define_insn "mve_vcmpgeq_f<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VCMPGEQ_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmp.f%#<V_sz_elem> ge, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgeq_n_f])
-;;
-(define_insn "mve_vcmpgeq_n_f<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPGEQ_N_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmp.f%#<V_sz_elem> ge, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmpgtq_f])
-;;
-(define_insn "mve_vcmpgtq_f<mode>"
- [
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VCMPGTQ_F))
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "s_register_operand" "w")]
+ VSUBQ))
]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmp.f%#<V_sz_elem> gt, %q1, %q2"
+ "TARGET_HAVE_MVE"
+ "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
-;;
-;; [vcmpgtq_n_f])
-;;
-(define_insn "mve_vcmpgtq_n_f<mode>"
+(define_insn "mve_vsubq<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPGTQ_N_F))
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (minus:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+ (match_operand:MVE_2 2 "s_register_operand" "w")))
]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmp.f%#<V_sz_elem> gt, %q1, %2"
+ "TARGET_HAVE_MVE"
+ "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
-;; [vcmpleq_f])
+;; [vabdq_f])
;;
-(define_insn "mve_vcmpleq_f<mode>"
+(define_insn "mve_vabdq_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VCMPLEQ_F))
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:MVE_0 2 "s_register_operand" "w")]
+ VABDQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmp.f%#<V_sz_elem> le, %q1, %q2"
+ "vabd.f%#<V_sz_elem> %q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
-;; [vcmpleq_n_f])
+;; [vaddlvaq_s vaddlvaq_u])
;;
-(define_insn "mve_vcmpleq_n_f<mode>"
+(define_insn "mve_vaddlvaq_<supf>v4si"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPLEQ_N_F))
+ (set (match_operand:DI 0 "s_register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
+ (match_operand:V4SI 2 "s_register_operand" "w")]
+ VADDLVAQ))
]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmp.f%#<V_sz_elem> le, %q1, %2"
+ "TARGET_HAVE_MVE"
+ "vaddlva.<supf>32 %Q0, %R0, %q2"
[(set_attr "type" "mve_move")
])
;;
-;; [vcmpltq_f])
+;; [vaddq_n_f])
;;
-(define_insn "mve_vcmpltq_f<mode>"
+(define_insn "mve_vaddq_n_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VCMPLTQ_F))
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:<V_elem> 2 "s_register_operand" "r")]
+ VADDQ_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmp.f%#<V_sz_elem> lt, %q1, %q2"
+ "vadd.f%#<V_sz_elem> %q0, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
-;; [vcmpltq_n_f])
+;; [vandq_f])
;;
-(define_insn "mve_vcmpltq_n_f<mode>"
+(define_insn "mve_vandq_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPLTQ_N_F))
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (and:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmp.f%#<V_sz_elem> lt, %q1, %2"
+ "vand %q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
-;; [vcmpneq_f])
+;; [vbicq_f])
;;
-(define_insn "mve_vcmpneq_f<mode>"
+(define_insn "mve_vbicq_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VCMPNEQ_F))
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (and:MVE_0 (not:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))
+ (match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmp.f%#<V_sz_elem> ne, %q1, %q2"
+ "vbic %q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
-;; [vcmpneq_n_f])
+;; [vbicq_n_s, vbicq_n_u])
;;
-(define_insn "mve_vcmpneq_n_f<mode>"
+(define_insn "mve_vbicq_n_<supf><mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VCMPNEQ_N_F))
+ (set (match_operand:MVE_5 0 "s_register_operand" "=w")
+ (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
+ (match_operand:SI 2 "immediate_operand" "i")]
+ VBICQ_N))
]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmp.f%#<V_sz_elem> ne, %q1, %2"
+ "TARGET_HAVE_MVE"
+ "vbic.i%#<V_sz_elem> %q0, %2"
[(set_attr "type" "mve_move")
])
;;
-;; [vcmulq_f])
+;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270])
;;
-(define_insn "mve_vcmulq_f<mode>"
+(define_insn "mve_vcaddq<mve_rot><mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:MVE_0 2 "s_register_operand" "w")]
- VCMULQ_F))
+ VCADD))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #0"
+ "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #<rot>"
[(set_attr "type" "mve_move")
])
;;
-;; [vcmulq_rot180_f])
+;; [vcmpeqq_f, vcmpgeq_f, vcmpgtq_f, vcmpleq_f, vcmpltq_f, vcmpneq_f])
;;
-(define_insn "mve_vcmulq_rot180_f<mode>"
+(define_insn "@mve_vcmp<mve_cmp_op>q_f<mode>"
[
- (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VCMULQ_ROT180_F))
+ (set (match_operand:HI 0 "vpr_register_operand" "=Up")
+ (MVE_FP_COMPARISONS:HI (match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #180"
+ "vcmp.f%#<V_sz_elem> <mve_cmp_op>, %q1, %q2"
[(set_attr "type" "mve_move")
])
;;
-;; [vcmulq_rot270_f])
+;; [vcmpeqq_n_f, vcmpgeq_n_f, vcmpgtq_n_f, vcmpleq_n_f, vcmpltq_n_f, vcmpneq_n_f])
;;
-(define_insn "mve_vcmulq_rot270_f<mode>"
+(define_insn "@mve_vcmp<mve_cmp_op>q_n_f<mode>"
[
- (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VCMULQ_ROT270_F))
+ (set (match_operand:HI 0 "vpr_register_operand" "=Up")
+ (MVE_FP_COMPARISONS:HI (match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:<V_elem> 2 "s_register_operand" "r")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #270"
+ "vcmp.f%#<V_sz_elem> <mve_cmp_op>, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
-;; [vcmulq_rot90_f])
+;; [vcmulq, vcmulq_rot90, vcmulq_rot180, vcmulq_rot270])
;;
-(define_insn "mve_vcmulq_rot90_f<mode>"
+(define_insn "mve_vcmulq<mve_rot><mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:MVE_0 2 "s_register_operand" "w")]
- VCMULQ_ROT90_F))
+ VCMUL))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #90"
+ "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #<rot>"
[(set_attr "type" "mve_move")
])
(define_insn "mve_veorq_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VEORQ_F))
+ (xor:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"veor %q0, %q1, %q2"
(define_insn "mve_vmaxnmq_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VMAXNMQ_F))
+ (smax:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vmaxnm.f%#<V_sz_elem> %q0, %q1, %q2"
(define_insn "mve_vminnmq_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VMINNMQ_F))
+ (smin:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vminnm.f%#<V_sz_elem> %q0, %q1, %q2"
[(set_attr "type" "mve_move")
])
+;; vmovnb pattern used by the vec_pack_trunc expander to avoid the
+;; need for an uninitialized input operand.
+(define_insn "@mve_vec_pack_trunc_lo_<mode>"
+ [
+ (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
+ (unspec:<V_narrow_pack> [(match_operand:MVE_5 1 "s_register_operand" "w")]
+ VMOVNBQ_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vmovnb.i%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
;;
;; [vmovntq_s, vmovntq_u])
;;
-(define_insn "mve_vmovntq_<supf><mode>"
+(define_insn "@mve_vmovntq_<supf><mode>"
[
(set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
(unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
(define_insn "mve_vmulq_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VMULQ_F))
+ (mult:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vmul.f%#<V_sz_elem> %q0, %q1, %q2"
(define_insn "mve_vornq_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VORNQ_F))
+ (ior:MVE_0 (not:MVE_0 (match_operand:MVE_0 2 "s_register_operand" "w"))
+ (match_operand:MVE_0 1 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vorn %q0, %q1, %q2"
(define_insn "mve_vorrq_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VORRQ_F))
+ (ior:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vorr %q0, %q1, %q2"
(define_insn "mve_vsubq_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VSUBQ_F))
+ (minus:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vsub.f%#<V_sz_elem>\t%q0, %q1, %q2"
;;
;; [vpselq_u, vpselq_s])
;;
-(define_insn "mve_vpselq_<supf><mode>"
+(define_insn "@mve_vpselq_<supf><mode>"
[
(set (match_operand:MVE_1 0 "s_register_operand" "=w")
(unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w")
(set_attr "length""8")])
;;
-;; [vqdmlahq_n_s, vqdmlahq_n_u])
+;; [vqdmlahq_n_s])
;;
(define_insn "mve_vqdmlahq_n_<supf><mode>"
[
[(set_attr "type" "mve_move")
])
+;;
+;; [vqdmlashq_n_s])
+;;
+(define_insn "mve_vqdmlashq_n_<supf><mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")]
+ VQDMLASHQ_N))
+ ]
+ "TARGET_HAVE_MVE"
+ "vqdmlash.s%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+])
+
;;
;; [vqnegq_m_s])
;;
])
;;
-;; [vqrdmlahq_n_s, vqrdmlahq_n_u])
+;; [vqrdmlahq_n_s])
;;
(define_insn "mve_vqrdmlahq_n_<supf><mode>"
[
])
;;
-;; [vqrdmlashq_n_s, vqrdmlashq_n_u])
+;; [vqrdmlashq_n_s])
;;
(define_insn "mve_vqrdmlashq_n_<supf><mode>"
[
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
-;; [vcmlaq_f])
-;;
-(define_insn "mve_vcmlaq_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")]
- VCMLAQ_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #0"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmlaq_rot180_f])
-;;
-(define_insn "mve_vcmlaq_rot180_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")]
- VCMLAQ_ROT180_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #180"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmlaq_rot270_f])
-;;
-(define_insn "mve_vcmlaq_rot270_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")]
- VCMLAQ_ROT270_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #270"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vcmlaq_rot90_f])
+;; [vcmlaq, vcmlaq_rot90, vcmlaq_rot180, vcmlaq_rot270])
;;
-(define_insn "mve_vcmlaq_rot90_f<mode>"
+(define_insn "mve_vcmlaq<mve_rot><mode>"
[
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")]
- VCMLAQ_ROT90_F))
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w,w")
+ (plus:MVE_0 (match_operand:MVE_0 1 "reg_or_zero_operand" "Dz,0")
+ (unspec:MVE_0
+ [(match_operand:MVE_0 2 "s_register_operand" "w,w")
+ (match_operand:MVE_0 3 "s_register_operand" "w,w")]
+ VCMLA)))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #90"
+ "@
+ vcmul.f%#<V_sz_elem> %q0, %q2, %q3, #<rot>
+ vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #<rot>"
[(set_attr "type" "mve_move")
])
;;
;; [vpselq_f])
;;
-(define_insn "mve_vpselq_f<mode>"
+(define_insn "@mve_vpselq_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
[(set_attr "type" "mve_move")
(set_attr "length""8")])
+;;
+;; [vqdmlashq_m_n_s])
+;;
+(define_insn "mve_vqdmlashq_m_n_s<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+ (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
+ (match_operand:MVE_2 2 "s_register_operand" "w")
+ (match_operand:<V_elem> 3 "s_register_operand" "r")
+ (match_operand:HI 4 "vpr_register_operand" "Up")]
+ VQDMLASHQ_M_N_S))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpst\;vqdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3"
+ [(set_attr "type" "mve_move")
+ (set_attr "length""8")])
+
;;
;; [vqrdmlahq_m_n_s])
;;
(set_attr "length""8")])
;;
-;; [vmlaldavaxq_p_u, vmlaldavaxq_p_s])
+;; [vmlaldavaxq_p_s])
;;
(define_insn "mve_vmlaldavaxq_p_<supf><mode>"
[
;;
(define_insn "mve_vldrwq_fv4sf"
[(set (match_operand:V4SF 0 "s_register_operand" "=w")
- (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Ux")]
+ (unspec:V4SF [(match_operand:V4SI 1 "mve_memory_operand" "Ux")]
VLDRWQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
;;
(define_insn "mve_vldrwq_<supf>v4si"
[(set (match_operand:V4SI 0 "s_register_operand" "=w")
- (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Ux")]
+ (unspec:V4SI [(match_operand:V4SI 1 "mve_memory_operand" "Ux")]
VLDRWQ))
]
"TARGET_HAVE_MVE"
;;
(define_insn "mve_vldrwq_z_fv4sf"
[(set (match_operand:V4SF 0 "s_register_operand" "=w")
- (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Ux")
+ (unspec:V4SF [(match_operand:V4SI 1 "mve_memory_operand" "Ux")
(match_operand:HI 2 "vpr_register_operand" "Up")]
VLDRWQ_F))
]
;;
(define_insn "mve_vldrwq_z_<supf>v4si"
[(set (match_operand:V4SI 0 "s_register_operand" "=w")
- (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Ux")
+ (unspec:V4SI [(match_operand:V4SI 1 "mve_memory_operand" "Ux")
(match_operand:HI 2 "vpr_register_operand" "Up")]
VLDRWQ))
]
;; [vstrwq_f]
;;
(define_insn "mve_vstrwq_fv4sf"
- [(set (match_operand:V4SI 0 "memory_operand" "=Ux")
+ [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
(unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")]
VSTRWQ_F))
]
;; [vstrwq_p_f]
;;
(define_insn "mve_vstrwq_p_fv4sf"
- [(set (match_operand:V4SI 0 "memory_operand" "=Ux")
+ [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
(unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
(match_operand:HI 2 "vpr_register_operand" "Up")]
VSTRWQ_F))
;; [vstrwq_p_s vstrwq_p_u]
;;
(define_insn "mve_vstrwq_p_<supf>v4si"
- [(set (match_operand:V4SI 0 "memory_operand" "=Ux")
+ [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
(match_operand:HI 2 "vpr_register_operand" "Up")]
VSTRWQ))
;; [vstrwq_s vstrwq_u]
;;
(define_insn "mve_vstrwq_<supf>v4si"
- [(set (match_operand:V4SI 0 "memory_operand" "=Ux")
+ [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")]
VSTRWQ))
]
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-(define_expand "mve_vstrwq_scatter_base_wb_<supf>v4si"
- [(match_operand:V4SI 0 "s_register_operand" "=w")
- (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
- (match_operand:V4SI 2 "s_register_operand" "w")
- (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)]
- "TARGET_HAVE_MVE"
-{
- rtx ignore_wb = gen_reg_rtx (V4SImode);
- emit_insn (
- gen_mve_vstrwq_scatter_base_wb_<supf>v4si_insn (ignore_wb, operands[0],
- operands[1], operands[2]));
- DONE;
-})
-
-(define_expand "mve_vstrwq_scatter_base_wb_add_<supf>v4si"
- [(match_operand:V4SI 0 "s_register_operand" "=w")
- (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
- (match_operand:V4SI 2 "s_register_operand" "0")
- (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)]
- "TARGET_HAVE_MVE"
-{
- rtx ignore_vec = gen_reg_rtx (V4SImode);
- emit_insn (
- gen_mve_vstrwq_scatter_base_wb_<supf>v4si_insn (operands[0], operands[2],
- operands[1], ignore_vec));
- DONE;
-})
-
;;
-;; [vstrwq_scatter_base_wb_s vstrdq_scatter_base_wb_u]
+;; [vstrwq_scatter_base_wb_s vstrwq_scatter_base_wb_u]
;;
-(define_insn "mve_vstrwq_scatter_base_wb_<supf>v4si_insn"
+(define_insn "mve_vstrwq_scatter_base_wb_<supf>v4si"
[(set (mem:BLK (scratch))
(unspec:BLK
[(match_operand:V4SI 1 "s_register_operand" "0")
}
[(set_attr "length" "4")])
-(define_expand "mve_vstrwq_scatter_base_wb_p_<supf>v4si"
- [(match_operand:V4SI 0 "s_register_operand" "=w")
- (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
- (match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand")
- (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)]
- "TARGET_HAVE_MVE"
-{
- rtx ignore_wb = gen_reg_rtx (V4SImode);
- emit_insn (
- gen_mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn (ignore_wb, operands[0],
- operands[1], operands[2],
- operands[3]));
- DONE;
-})
-
-(define_expand "mve_vstrwq_scatter_base_wb_p_add_<supf>v4si"
- [(match_operand:V4SI 0 "s_register_operand" "=w")
- (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
- (match_operand:V4SI 2 "s_register_operand" "0")
- (match_operand:HI 3 "vpr_register_operand")
- (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)]
- "TARGET_HAVE_MVE"
-{
- rtx ignore_vec = gen_reg_rtx (V4SImode);
- emit_insn (
- gen_mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn (operands[0], operands[2],
- operands[1], ignore_vec,
- operands[3]));
- DONE;
-})
-
;;
;; [vstrwq_scatter_base_wb_p_s vstrwq_scatter_base_wb_p_u]
;;
-(define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn"
+(define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si"
[(set (mem:BLK (scratch))
(unspec:BLK
[(match_operand:V4SI 1 "s_register_operand" "0")
}
[(set_attr "length" "8")])
-(define_expand "mve_vstrwq_scatter_base_wb_fv4sf"
- [(match_operand:V4SI 0 "s_register_operand" "=w")
- (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
- (match_operand:V4SF 2 "s_register_operand" "w")
- (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-{
- rtx ignore_wb = gen_reg_rtx (V4SImode);
- emit_insn (
- gen_mve_vstrwq_scatter_base_wb_fv4sf_insn (ignore_wb,operands[0],
- operands[1], operands[2]));
- DONE;
-})
-
-(define_expand "mve_vstrwq_scatter_base_wb_add_fv4sf"
- [(match_operand:V4SI 0 "s_register_operand" "=w")
- (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
- (match_operand:V4SI 2 "s_register_operand" "0")
- (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-{
- rtx ignore_vec = gen_reg_rtx (V4SFmode);
- emit_insn (
- gen_mve_vstrwq_scatter_base_wb_fv4sf_insn (operands[0], operands[2],
- operands[1], ignore_vec));
- DONE;
-})
-
;;
;; [vstrwq_scatter_base_wb_f]
;;
-(define_insn "mve_vstrwq_scatter_base_wb_fv4sf_insn"
+(define_insn "mve_vstrwq_scatter_base_wb_fv4sf"
[(set (mem:BLK (scratch))
(unspec:BLK
[(match_operand:V4SI 1 "s_register_operand" "0")
}
[(set_attr "length" "4")])
-(define_expand "mve_vstrwq_scatter_base_wb_p_fv4sf"
- [(match_operand:V4SI 0 "s_register_operand" "=w")
- (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
- (match_operand:V4SF 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand")
- (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-{
- rtx ignore_wb = gen_reg_rtx (V4SImode);
- emit_insn (
- gen_mve_vstrwq_scatter_base_wb_p_fv4sf_insn (ignore_wb, operands[0],
- operands[1], operands[2],
- operands[3]));
- DONE;
-})
-
-(define_expand "mve_vstrwq_scatter_base_wb_p_add_fv4sf"
- [(match_operand:V4SI 0 "s_register_operand" "=w")
- (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
- (match_operand:V4SI 2 "s_register_operand" "0")
- (match_operand:HI 3 "vpr_register_operand")
- (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-{
- rtx ignore_vec = gen_reg_rtx (V4SFmode);
- emit_insn (
- gen_mve_vstrwq_scatter_base_wb_p_fv4sf_insn (operands[0], operands[2],
- operands[1], ignore_vec,
- operands[3]));
- DONE;
-})
-
;;
;; [vstrwq_scatter_base_wb_p_f]
;;
-(define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf_insn"
+(define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf"
[(set (mem:BLK (scratch))
(unspec:BLK
[(match_operand:V4SI 1 "s_register_operand" "0")
}
[(set_attr "length" "8")])
-(define_expand "mve_vstrdq_scatter_base_wb_<supf>v2di"
- [(match_operand:V2DI 0 "s_register_operand" "=w")
- (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
- (match_operand:V2DI 2 "s_register_operand" "w")
- (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)]
- "TARGET_HAVE_MVE"
-{
- rtx ignore_wb = gen_reg_rtx (V2DImode);
- emit_insn (
- gen_mve_vstrdq_scatter_base_wb_<supf>v2di_insn (ignore_wb, operands[0],
- operands[1], operands[2]));
- DONE;
-})
-
-(define_expand "mve_vstrdq_scatter_base_wb_add_<supf>v2di"
- [(match_operand:V2DI 0 "s_register_operand" "=w")
- (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
- (match_operand:V2DI 2 "s_register_operand" "0")
- (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)]
- "TARGET_HAVE_MVE"
-{
- rtx ignore_vec = gen_reg_rtx (V2DImode);
- emit_insn (
- gen_mve_vstrdq_scatter_base_wb_<supf>v2di_insn (operands[0], operands[2],
- operands[1], ignore_vec));
- DONE;
-})
-
;;
;; [vstrdq_scatter_base_wb_s vstrdq_scatter_base_wb_u]
;;
-(define_insn "mve_vstrdq_scatter_base_wb_<supf>v2di_insn"
+(define_insn "mve_vstrdq_scatter_base_wb_<supf>v2di"
[(set (mem:BLK (scratch))
(unspec:BLK
[(match_operand:V2DI 1 "s_register_operand" "0")
}
[(set_attr "length" "4")])
-(define_expand "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
- [(match_operand:V2DI 0 "s_register_operand" "=w")
- (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
- (match_operand:V2DI 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand")
- (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)]
- "TARGET_HAVE_MVE"
-{
- rtx ignore_wb = gen_reg_rtx (V2DImode);
- emit_insn (
- gen_mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn (ignore_wb, operands[0],
- operands[1], operands[2],
- operands[3]));
- DONE;
-})
-
-(define_expand "mve_vstrdq_scatter_base_wb_p_add_<supf>v2di"
- [(match_operand:V2DI 0 "s_register_operand" "=w")
- (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
- (match_operand:V2DI 2 "s_register_operand" "0")
- (match_operand:HI 3 "vpr_register_operand")
- (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)]
- "TARGET_HAVE_MVE"
-{
- rtx ignore_vec = gen_reg_rtx (V2DImode);
- emit_insn (
- gen_mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn (operands[0], operands[2],
- operands[1], ignore_vec,
- operands[3]));
- DONE;
-})
-
;;
;; [vstrdq_scatter_base_wb_p_s vstrdq_scatter_base_wb_p_u]
;;
-(define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn"
+(define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
[(set (mem:BLK (scratch))
(unspec:BLK
[(match_operand:V2DI 1 "s_register_operand" "0")
ops[0] = operands[1];
ops[1] = operands[2];
ops[2] = operands[3];
- output_asm_insn ("vpst\;\tvstrdt.u64\t%q2, [%q0, %1]!",ops);
+ output_asm_insn ("vpst;vstrdt.u64\t%q2, [%q0, %1]!",ops);
return "";
}
[(set_attr "length" "8")])
[(set_attr "type" "mve_move")
(set_attr "length" "8")])
-(define_insn "*mve_vec_duplicate<mode>"
- [(set (match_operand:MVE_VLD_ST 0 "s_register_operand" "=w")
- (vec_duplicate:MVE_VLD_ST (match_operand:<V_elem> 1 "general_operand" "r")))]
- "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
- "vdup.<V_sz_elem>\t%q0, %1"
- [(set_attr "type" "mve_move")])
-
;; CDE instructions on MVE registers.
(define_insn "arm_vcx1qv16qi"
[(set_attr "type" "coproc")
(set_attr "length" "8")]
)
+
+(define_insn "*movmisalign<mode>_mve_store"
+ [(set (match_operand:MVE_VLD_ST 0 "neon_permissive_struct_operand" "=Ux")
+ (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "s_register_operand" " w")]
+ UNSPEC_MISALIGNED_ACCESS))]
+ "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
+ || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode)))
+ && !BYTES_BIG_ENDIAN && unaligned_access"
+ "vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0"
+ [(set_attr "type" "mve_store")]
+)
+
+
+(define_insn "*movmisalign<mode>_mve_load"
+ [(set (match_operand:MVE_VLD_ST 0 "s_register_operand" "=w")
+ (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "neon_permissive_struct_operand" " Ux")]
+ UNSPEC_MISALIGNED_ACCESS))]
+ "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
+ || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode)))
+ && !BYTES_BIG_ENDIAN && unaligned_access"
+ "vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1"
+ [(set_attr "type" "mve_load")]
+)
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