/* Definitions of target machine for GNU compiler, NetBSD/arm ELF version.
- Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc.
+ Copyright (C) 2002-2020 Free Software Foundation, Inc.
Contributed by Wasabi Systems, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 2, or (at your
+ by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING. If not, write to
- the Free Software Foundation, 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
/* Run-time Target Specification. */
-#undef TARGET_VERSION
-#define TARGET_VERSION fputs (" (NetBSD/arm ELF)", stderr);
/* arm.h defaults to ARM6 CPU. */
/* Default it to use ATPCS with soft-VFP. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
- (ARM_FLAG_APCS_FRAME \
+ (MASK_APCS_FRAME \
| TARGET_ENDIAN_DEFAULT)
#undef ARM_DEFAULT_ABI
#define ARM_DEFAULT_ABI ARM_ABI_ATPCS
+#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
#undef SUBTARGET_EXTRA_ASM_SPEC
#define SUBTARGET_EXTRA_ASM_SPEC \
- "-matpcs %{fpic|fpie:-k} %{fPIC|fPIE:-k}"
+ "%{" FPIE_OR_FPIC_SPEC ":-k}"
-/* Default to full VFP if -mhard-float is specified. */
+/* Default to full VFP if -mfloat-abi=hard is specified. */
#undef SUBTARGET_ASM_FLOAT_SPEC
#define SUBTARGET_ASM_FLOAT_SPEC \
- "%{mhard-float:{!mfpu=*:-mfpu=vfp}} \
- %{mfloat-abi=hard:{!mfpu=*:-mfpu=vfp}}"
+ "%{mfloat-abi=hard:{!mfpu=*:-mfpu=vfp}}"
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \
/* We don't have any limit on the length as out debugger is GDB. */
#undef DBX_CONTIN_LENGTH
-/* NetBSD does its profiling differently to the Acorn compiler. We
+/* NetBSD does its profiling differently to the Acorn compiler. We
don't need a word following the mcount call; and to skip it
- requires either an assembly stub or use of fomit-frame-pointer when
+ requires either an assembly stub or use of fomit-frame-pointer when
compiling the profiling functions. Since we break Acorn CC
compatibility below a little more won't hurt. */
-
-#undef ARM_FUNCTION_PROFILER
+
+#undef ARM_FUNCTION_PROFILER
#define ARM_FUNCTION_PROFILER(STREAM,LABELNO) \
{ \
asm_fprintf (STREAM, "\tmov\t%Rip, %Rlr\n"); \
asm_fprintf (STREAM, "\tbl\t__mcount%s\n", \
- NEED_PLT_RELOC ? "(PLT)" : ""); \
+ (TARGET_ARM && NEED_PLT_RELOC) \
+ ? "(PLT)" : ""); \
}
/* VERY BIG NOTE: Change of structure alignment for NetBSD/arm.
boundary. However this causes problems with bugged NetBSD kernel
code (possibly userland code as well - I have not checked every
binary). The nature of this bugged code is to rely on sizeof()
- returning the correct size of various structures rounded to the
+ returning the correct size of various structures rounded to the
nearest byte (SCSI and ether code are two examples, the vm system
is another). This code breaks when the structure alignment is 32
- as sizeof() will report a word=rounded size. By changing the
+ as sizeof() will report a word=rounded size. By changing the
structure alignment to 8. GCC will conform to what is expected by
NetBSD.
-
+
This has several side effects that should be considered.
1. Structures will only be aligned to the size of the largest member.
i.e. structures containing only bytes will be byte aligned.
- structures containing shorts will be half word aligned.
- structures containing ints will be word aligned.
-
+ structures containing shorts will be half word aligned.
+ structures containing ints will be word aligned.
+
This means structures should be padded to a word boundary if
alignment of 32 is required for byte structures etc.
-
+
2. A potential performance penalty may exist if strings are no longer
word aligned. GCC will not be able to use word load/stores to copy
short strings.
#undef DEFAULT_STRUCTURE_SIZE_BOUNDARY
#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 8
-/* Emit code to set up a trampoline and synchronize the caches. */
-#undef INITIALIZE_TRAMPOLINE
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-do \
- { \
- emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
- (CXT)); \
- emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
- (FNADDR)); \
- emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
- 0, VOIDmode, 2, TRAMP, Pmode, \
- plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
- } \
-while (0)
+#define SYSARCH_ARM_SYNC_ICACHE 0
/* Clear the instruction cache from `BEG' to `END'. This makes a
call to the ARM_SYNC_ICACHE architecture specific syscall. */
} s; \
s.addr = (unsigned int)(BEG); \
s.len = (END) - (BEG); \
- (void) sysarch (0, &s); \
+ (void) sysarch (SYSARCH_ARM_SYNC_ICACHE, &s); \
} \
while (0)
-
-#undef FPUTYPE_DEFAULT
-#define FPUTYPE_DEFAULT FPUTYPE_VFP
-
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