;; ARM Thumb-2 Machine Description
-;; Copyright (C) 2007-2020 Free Software Foundation, Inc.
+;; Copyright (C) 2007-2024 Free Software Foundation, Inc.
;; Written by CodeSourcery, LLC.
;;
;; This file is part of GCC.
[(match_operand 4 "cc_register" "") (const_int 0)])
(match_operand:SF 1 "s_register_operand" "0,r")
(match_operand:SF 2 "s_register_operand" "r,0")))]
- "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
+ "TARGET_THUMB2 && TARGET_SOFT_FLOAT && !TARGET_HAVE_MVE"
"@
it\\t%D3\;mov%D3\\t%0, %2
it\\t%d3\;mov%d3\\t%0, %1"
[(set_attr "type" "call")]
)
+(define_insn "*nonsecure_call_reg_thumb2_fpcxt"
+ [(call (unspec:SI [(mem:SI (match_operand:SI 0 "s_register_operand" "l*r"))]
+ UNSPEC_NONSECURE_MEM)
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (clobber (reg:SI LR_REGNUM))]
+ "TARGET_THUMB2 && use_cmse && TARGET_HAVE_FPCXT_CMSE"
+ "blxns\\t%0"
+ [(set_attr "length" "4")
+ (set_attr "type" "call")]
+)
+
(define_insn "*nonsecure_call_reg_thumb2"
[(call (unspec:SI [(mem:SI (reg:SI R4_REGNUM))]
UNSPEC_NONSECURE_MEM)
(match_operand 0 "" ""))
(use (match_operand 1 "" ""))
(clobber (reg:SI LR_REGNUM))]
- "TARGET_THUMB2 && use_cmse"
+ "TARGET_THUMB2 && use_cmse && !TARGET_HAVE_FPCXT_CMSE"
"bl\\t__gnu_cmse_nonsecure_call"
[(set_attr "length" "4")
(set_attr "type" "call")]
[(set_attr "type" "call")]
)
-(define_insn "*nonsecure_call_value_reg_thumb2"
+(define_insn "*nonsecure_call_value_reg_thumb2_fpcxt"
[(set (match_operand 0 "" "")
(call
- (unspec:SI [(mem:SI (reg:SI R4_REGNUM))]
+ (unspec:SI [(mem:SI (match_operand:SI 1 "register_operand" "l*r"))]
UNSPEC_NONSECURE_MEM)
+ (match_operand 2 "" "")))
+ (use (match_operand 3 "" ""))
+ (clobber (reg:SI LR_REGNUM))]
+ "TARGET_THUMB2 && use_cmse && TARGET_HAVE_FPCXT_CMSE"
+ "blxns\\t%1"
+ [(set_attr "length" "4")
+ (set_attr "type" "call")]
+)
+
+(define_insn "*nonsecure_call_value_reg_thumb2"
+ [(set (match_operand 0 "" "")
+ (call
+ (unspec:SI [(mem:SI (reg:SI R4_REGNUM))] UNSPEC_NONSECURE_MEM)
(match_operand 1 "" "")))
(use (match_operand 2 "" ""))
(clobber (reg:SI LR_REGNUM))]
- "TARGET_THUMB2 && use_cmse"
- "bl\t__gnu_cmse_nonsecure_call"
+ "TARGET_THUMB2 && use_cmse && !TARGET_HAVE_FPCXT_CMSE"
+ "bl\\t__gnu_cmse_nonsecure_call"
[(set_attr "length" "4")
(set_attr "type" "call")]
)
return \"%i5\\t%0, %1, %2, lsr #31\";
output_asm_insn (\"cmp\\t%2, %3\", operands);
+
+ if (GET_CODE (operands[5]) == PLUS && TARGET_COND_ARITH)
+ return \"cinc\\t%0, %1, %d4\";
+
if (GET_CODE (operands[5]) == AND)
{
output_asm_insn (\"ite\\t%D4\", operands);
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI")])))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_THUMB2"
+ "TARGET_THUMB2 && !TARGET_COND_ARITH"
"#"
"&& reload_completed"
[(const_int 0)]
(set_attr "type" "multiple")]
)
+(define_insn "*thumb2_csinv"
+ [(set (match_operand:SI 0 "arm_general_register_operand" "=r, r")
+ (if_then_else:SI
+ (match_operand 1 "arm_comparison_operation" "")
+ (not:SI (match_operand:SI 2 "arm_general_register_operand" "r, r"))
+ (match_operand:SI 3 "reg_or_zero_operand" "r, Pz")))]
+ "TARGET_COND_ARITH"
+ "@
+ csinv\\t%0, %3, %2, %D1
+ csinv\\t%0, zr, %2, %D1"
+ [(set_attr "type" "csel")
+ (set_attr "predicable" "no")]
+)
+
+(define_insn "*thumb2_csinc"
+ [(set (match_operand:SI 0 "arm_general_register_operand" "=r, r")
+ (if_then_else:SI
+ (match_operand 1 "arm_comparison_operation" "")
+ (plus:SI (match_operand:SI 2 "arm_general_register_operand" "r, r")
+ (const_int 1))
+ (match_operand:SI 3 "reg_or_zero_operand" "r, Pz")))]
+ "TARGET_COND_ARITH"
+ "@
+ csinc\\t%0, %3, %2, %D1
+ csinc\\t%0, zr, %2, %D1"
+ [(set_attr "type" "csel")
+ (set_attr "predicable" "no")]
+)
+
+(define_insn "*thumb2_csneg"
+ [(set (match_operand:SI 0 "arm_general_register_operand" "=r, r")
+ (if_then_else:SI
+ (match_operand 1 "arm_comparison_operation" "")
+ (neg:SI (match_operand:SI 2 "arm_general_register_operand" "r, r"))
+ (match_operand:SI 3 "reg_or_zero_operand" "r, Pz")))]
+ "TARGET_COND_ARITH"
+ "@
+ csneg\\t%0, %3, %2, %D1
+ csneg\\t%0, zr, %2, %D1"
+ [(set_attr "type" "csel")
+ (set_attr "predicable" "no")]
+)
+
(define_insn "*thumb2_movcond"
[(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts")
(if_then_else:SI
(match_operand:SI 1 "arm_rhs_operand" "0,TsI,?TsI")
(match_operand:SI 2 "arm_rhs_operand" "TsI,0,TsI")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_THUMB2"
+ "TARGET_THUMB2 && !TARGET_COND_ARITH"
"*
if (GET_CODE (operands[5]) == LT
&& (operands[4] == const0_rtx))
(set_attr "shift" "1")
(set_attr "length" "2")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "alu_shift_imm")
+ (if_then_else (match_operand 3 "alu_shift_operator_lsl_1_to_4")
+ (const_string "alu_shift_imm_lsl_1to4")
+ (const_string "alu_shift_imm_other"))
(const_string "alu_shift_reg")))]
)
"orn%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
- (set_attr "type" "alu_shift_imm")]
+ (set_attr "autodetect_type" "alu_shift_operator4")]
)
(define_peephole2
using a certain 'count' register and (2) the loop count can be
adjusted by modifying this register prior to the loop.
??? The possible introduction of a new block to initialize the
- new IV can potentially affect branch optimizations. */
- if (optimize > 0 && flag_modulo_sched)
+ new IV can potentially affect branch optimizations.
+
+ Also used to implement the low over head loops feature, which is part of
+ the Armv8.1-M Mainline Low Overhead Branch (LOB) extension. */
+ if (optimize > 0 && (flag_modulo_sched || TARGET_HAVE_LOB))
{
rtx s0;
rtx bcomp;
FAIL;
s0 = operands [0];
+
+ /* Low over head loop instructions require the first operand to be LR. */
+ if (TARGET_HAVE_LOB && arm_target_insn_ok_for_lob (operands [1]))
+ s0 = gen_rtx_REG (SImode, LR_REGNUM);
+
if (TARGET_THUMB2)
insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
else
gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
loc_ref, pc_rtx)));
DONE;
- }else
- FAIL;
+ }
+ else
+ FAIL;
}")
+(define_insn "*clear_apsr"
+ [(unspec_volatile:SI [(const_int 0)] VUNSPEC_CLRM_APSR)
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_THUMB2 && TARGET_HAVE_FPCXT_CMSE && use_cmse"
+ "clrm%?\\t{APSR}"
+ [(set_attr "predicable" "yes")]
+)
+
+;; The operands are validated through the clear_multiple_operation
+;; match_parallel predicate rather than through constraints so enable it only
+;; after reload.
+(define_insn "*clear_multiple"
+ [(match_parallel 0 "clear_multiple_operation"
+ [(set (match_operand:SI 1 "register_operand" "")
+ (const_int 0))])]
+ "TARGET_THUMB2 && TARGET_HAVE_FPCXT_CMSE && use_cmse && reload_completed"
+ {
+ char pattern[100];
+ int i, num_saves = XVECLEN (operands[0], 0);
+
+ strcpy (pattern, \"clrm%?\\t{\");
+ for (i = 0; i < num_saves; i++)
+ {
+ if (GET_CODE (XVECEXP (operands[0], 0, i)) == UNSPEC_VOLATILE)
+ {
+ strcat (pattern, \"APSR\");
+ ++i;
+ }
+ else
+ strcat (pattern,
+ reg_names[REGNO (XEXP (XVECEXP (operands[0], 0, i), 0))]);
+ if (i < num_saves - 1)
+ strcat (pattern, \", %|\");
+ }
+ strcat (pattern, \"}\");
+ output_asm_insn (pattern, operands);
+ return \"\";
+ }
+ [(set_attr "predicable" "yes")]
+)
+
+(define_insn "thumb2_asrl"
+ [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
+ (ashiftrt:DI (match_dup 0)
+ (match_operand:SI 1 "arm_reg_or_long_shift_imm" "rPg")))]
+ "TARGET_HAVE_MVE"
+ "asrl%?\\t%Q0, %R0, %1"
+ [(set_attr "predicable" "yes")])
+
+(define_insn "thumb2_lsll"
+ [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
+ (ashift:DI (match_dup 0)
+ (match_operand:SI 1 "arm_reg_or_long_shift_imm" "rPg")))]
+ "TARGET_HAVE_MVE"
+ "lsll%?\\t%Q0, %R0, %1"
+ [(set_attr "predicable" "yes")])
+
+(define_insn "thumb2_lsrl"
+ [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
+ (lshiftrt:DI (match_dup 0)
+ (match_operand:SI 1 "long_shift_imm" "Pg")))]
+ "TARGET_HAVE_MVE"
+ "lsrl%?\\t%Q0, %R0, %1"
+ [(set_attr "predicable" "yes")])
+
+;; Originally expanded by 'doloop_end'.
+(define_insn "*doloop_end_internal"
+ [(set (pc)
+ (if_then_else
+ (ne (reg:SI LR_REGNUM) (const_int 1))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))
+ (set (reg:SI LR_REGNUM)
+ (plus:SI (reg:SI LR_REGNUM) (const_int -1)))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_32BIT && TARGET_HAVE_LOB"
+ {
+ if (get_attr_length (insn) == 4)
+ return "le\t%|lr, %l0";
+ else
+ return "subs\t%|lr, #1;bne\t%l0";
+ }
+ [(set (attr "length")
+ (if_then_else
+ (ltu (minus (pc) (match_dup 0)) (const_int 1024))
+ (const_int 4)
+ (const_int 6)))
+ (set_attr "type" "branch")])
+
+(define_expand "doloop_begin"
+ [(match_operand 0 "" "")
+ (match_operand 1 "" "")]
+ "TARGET_32BIT && TARGET_HAVE_LOB"
+ {
+ if (REGNO (operands[0]) == LR_REGNUM)
+ {
+ emit_insn (gen_dls_insn (operands[0]));
+ DONE;
+ }
+ else
+ FAIL;
+ })
+
+(define_insn "dls_insn"
+ [(set (reg:SI LR_REGNUM)
+ (unspec:SI [(match_operand:SI 0 "s_register_operand" "r")] UNSPEC_DLS))]
+ "TARGET_32BIT && TARGET_HAVE_LOB"
+ "dls\t%|lr, %0")
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