;; ARM VFP instruction patterns
-;; Copyright (C) 2003-2016 Free Software Foundation, Inc.
+;; Copyright (C) 2003-2020 Free Software Foundation, Inc.
;; Written by CodeSourcery.
;;
;; This file is part of GCC.
(const_string "mov_reg"))
(const_string "mvn_imm")
(const_string "mov_imm")
- (const_string "store1")
- (const_string "load1")
+ (const_string "store_4")
+ (const_string "load_4")
(const_string "f_mcr")
(const_string "f_mrc")
(const_string "fmov")])
(set_attr "predicable_short_it"
"yes, no, yes, no, no, no, no, no, no")
(set_attr "type"
- "mov_reg, mov_imm, mov_imm, mov_imm, store1, load1,\
+ "mov_reg, mov_imm, mov_imm, mov_imm, store_4, load_4,\
f_mcr, f_mrc, fmov")
(set_attr "arch" "*, *, *, v6t2, *, *, *, *, *")
(set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *")
(const_string "mov_reg"))
(const_string "mvn_imm")
(const_string "mov_imm")
- (const_string "store1")
- (const_string "load1")
+ (const_string "store_4")
+ (const_string "load_4")
(const_string "f_mcr")
(const_string "f_mrc")
(const_string "fmov")])
(set_attr "predicable_short_it"
"yes, no, yes, no, no, no, no, no, no")
(set_attr "type"
- "mov_reg, mov_imm, mov_imm, mov_imm, store1, load1,\
+ "mov_reg, mov_imm, mov_imm, mov_imm, store_4, load_4,\
f_mcr, f_mrc, fmov")
(set_attr "arch" "*, *, *, v6t2, *, *, *, *, *")
(set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *")
}
"
[(set_attr "predicable" "yes")
- (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,
+ (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load_4,store_4,
f_mcr,f_mrc,fmov,f_loads,f_stores")
(set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
;; is chosen with length 2 when the instruction is predicated for
;; arm_restrict_it.
(define_insn "*thumb2_movsi_vfp"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r, l,*hk,m, *m,*t, r,*t,*t, *Uv")
- (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,lk*r,m,*t, r,*t,*t, *Uv")
+ (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,lk*r, r,*t,*t,*UvTu,*t"))]
"TARGET_THUMB2 && TARGET_HARD_FLOAT
&& ( s_register_operand (operands[0], SImode)
|| s_register_operand (operands[1], SImode))"
case 4:
return \"movw%?\\t%0, %1\";
case 5:
- case 6:
+ /* Cannot load it directly, split to load it via MOV / MOVT. */
+ if (!MEM_P (operands[1]) && arm_disable_literal_pool)
+ return \"#\";
return \"ldr%?\\t%0, %1\";
- case 7:
- case 8:
+ case 6:
return \"str%?\\t%1, %0\";
- case 9:
+ case 7:
return \"vmov%?\\t%0, %1\\t%@ int\";
- case 10:
+ case 8:
return \"vmov%?\\t%0, %1\\t%@ int\";
- case 11:
+ case 9:
return \"vmov%?.f32\\t%0, %1\\t%@ int\";
- case 12: case 13:
+ case 10: case 11:
return output_move_vfp (operands);
default:
gcc_unreachable ();
}
"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no")
- (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load1,load1,store1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores")
- (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4")
- (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*")
- (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
+ (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no")
+ (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load_4,store_4,f_mcr,f_mrc,fmov,f_loads,f_stores")
+ (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4")
+ (set_attr "pool_range" "*,*,*,*,*,1018,*,*,*,*,1018,*")
+ (set_attr "neg_pool_range" "*,*,*,*,*, 0,*,*,*,*,1008,*")]
)
;; DImode moves
(define_insn "*movdi_vfp"
- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w, Uv")
- (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && arm_tune != TARGET_CPU_cortexa8
+ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv")
+ (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,UvTu,w"))]
+ "TARGET_32BIT && TARGET_HARD_FLOAT
&& ( register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))
&& !(TARGET_NEON && CONST_INT_P (operands[1])
return \"#\";
case 4:
case 5:
+ /* Cannot load it directly, split to load it via MOV / MOVT. */
+ if (!MEM_P (operands[1]) && arm_disable_literal_pool)
+ return \"#\";
+ /* Fall through. */
case 6:
return output_move_double (operands, true, NULL);
case 7:
gcc_unreachable ();
}
"
- [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
- (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
+ [(set_attr "type" "multiple,multiple,multiple,multiple,load_8,load_8,store_8,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
+ (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
(eq_attr "alternative" "2") (const_int 12)
(eq_attr "alternative" "3") (const_int 16)
+ (eq_attr "alternative" "4,5,6")
+ (symbol_ref "arm_count_output_move_double_insns (operands) * 4")
(eq_attr "alternative" "9")
(if_then_else
(match_test "TARGET_VFP_SINGLE")
(const_int 8)
(const_int 4))]
(const_int 4)))
+ (set_attr "predicable" "yes")
(set_attr "arm_pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*")
(set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
(set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
+ (set (attr "ce_count") (symbol_ref "get_attr_length (insn) / 4"))
(set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")]
)
-(define_insn "*movdi_vfp_cortexa8"
- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,!r,w,w, Uv")
- (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && arm_tune == TARGET_CPU_cortexa8
- && ( register_operand (operands[0], DImode)
- || register_operand (operands[1], DImode))
- && !(TARGET_NEON && CONST_INT_P (operands[1])
- && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
- "*
- switch (which_alternative)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- return \"#\";
- case 4:
- case 5:
- case 6:
- return output_move_double (operands, true, NULL);
- case 7:
- return \"vmov%?\\t%P0, %Q1, %R1\\t%@ int\";
- case 8:
- return \"vmov%?\\t%Q0, %R0, %P1\\t%@ int\";
- case 9:
- return \"vmov%?.f64\\t%P0, %P1\\t%@ int\";
- case 10: case 11:
- return output_move_vfp (operands);
- default:
- gcc_unreachable ();
- }
- "
- [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
- (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
- (eq_attr "alternative" "2") (const_int 12)
- (eq_attr "alternative" "3") (const_int 16)
- (eq_attr "alternative" "4,5,6")
- (symbol_ref
- "arm_count_output_move_double_insns (operands) \
- * 4")]
- (const_int 4)))
- (set_attr "predicable" "yes")
- (set_attr "arm_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
- (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*")
- (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
- (set (attr "ce_count")
- (symbol_ref "get_attr_length (insn) / 4"))
- (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")]
- )
-
;; HFmode moves
(define_insn "*movhf_vfp_fp16"
gcc_unreachable ();
}
}
- [(set_attr "predicable" "yes, yes, no, yes, no, no, no, no, no, no")
+ [(set_attr "conds" "*, *, unconditional, *, unconditional, unconditional,\
+ unconditional, unconditional, unconditional,\
+ unconditional")
+ (set_attr "predicable" "yes, yes, no, yes, no, no, no, no, no, no")
(set_attr "predicable_short_it" "no, no, no, yes,\
no, no, no, no,\
no, no")
(set_attr_alternative "type"
- [(const_string "load1") (const_string "store1")
+ [(const_string "load_4") (const_string "store_4")
(const_string "fmov") (const_string "mov_reg")
(const_string "f_mcr") (const_string "f_mrc")
(const_string "fconsts") (const_string "neon_load1_1reg")
"
[(set_attr "conds" "unconditional")
(set_attr "type" "neon_load1_1reg,neon_store1_1reg,\
- load1,store1,fmov,mov_reg,f_mcr,f_mrc,multiple")
+ load_4,store_4,fmov,mov_reg,f_mcr,f_mrc,multiple")
(set_attr "length" "4,4,4,4,4,4,4,4,8")]
)
}
"
[(set_attr "conds" "unconditional")
- (set_attr "type" "load1,store1,fmov,mov_reg,f_mcr,f_mrc,multiple")
+ (set_attr "type" "load_4,store_4,fmov,mov_reg,f_mcr,f_mrc,multiple")
(set_attr "length" "4,4,4,4,4,4,8")]
)
"
[(set_attr "predicable" "yes")
(set_attr "type"
- "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg")
+ "f_mcr,f_mrc,fconsts,f_loads,f_stores,load_4,store_4,fmov,mov_reg")
(set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
)
(define_insn "*thumb2_movsf_vfp"
[(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t ,Uv,r ,m,t,r")
- (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
+ (match_operand:SF 1 "hard_sf_operand" " ?r,t,Dv,UvHa,t, mHa,r,t,r"))]
"TARGET_THUMB2 && TARGET_HARD_FLOAT
&& ( s_register_operand (operands[0], SFmode)
|| s_register_operand (operands[1], SFmode))"
}
"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type"
- "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg")
+ "f_mcr,f_mrc,fconsts,f_loads,f_stores,load_4,store_4,fmov,mov_reg")
(set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
)
}
"
[(set_attr "type" "f_mcrr,f_mrrc,fconstd,neon_move,f_loadd,f_stored,\
- load2,store2,ffarithd,multiple")
+ load_8,store_8,ffarithd,multiple")
(set (attr "length") (cond [(eq_attr "alternative" "6,7,9") (const_int 8)
(eq_attr "alternative" "8")
(if_then_else
(define_insn "*thumb2_movdf_vfp"
[(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,w ,Uv,r ,m,w,r")
- (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,G,UvF,w, mF,r, w,r"))]
+ (match_operand:DF 1 "hard_df_operand" " ?r,w,Dy,G,UvHa,w, mHa,r, w,r"))]
"TARGET_THUMB2 && TARGET_HARD_FLOAT
&& ( register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode))"
}
"
[(set_attr "type" "f_mcrr,f_mrrc,fconstd,neon_move,f_loadd,\
- f_stored,load2,store2,ffarithd,multiple")
+ f_stored,load_8,store_8,ffarithd,multiple")
(set (attr "length") (cond [(eq_attr "alternative" "6,7,9") (const_int 8)
(eq_attr "alternative" "8")
(if_then_else
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vabs%?.f32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffariths")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vabs%?.f64\\t%P0, %P1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffarithd")]
)
vneg%?.f32\\t%0, %1
eor%?\\t%0, %1, #-2147483648"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffariths")]
)
if (REGNO (operands[0]) == REGNO (operands[1]))
{
operands[0] = gen_highpart (SImode, operands[0]);
- operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
+ operands[1] = gen_rtx_XOR (SImode, operands[0],
+ gen_int_mode (0x80000000, SImode));
}
else
{
rtx in_hi, in_lo, out_hi, out_lo;
in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
- GEN_INT (0x80000000));
+ gen_int_mode (0x80000000, SImode));
in_lo = gen_lowpart (SImode, operands[1]);
out_hi = gen_highpart (SImode, operands[0]);
out_lo = gen_lowpart (SImode, operands[0]);
}
"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "length" "4,4,8")
(set_attr "type" "ffarithd")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vadd%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fadds")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vadd%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "faddd")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vsub%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fadds")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vsub%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "faddd")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vdiv%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "arch" "*,armv6_or_vfpv3")
(set_attr "type" "fdivs")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vdiv%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "arch" "*,armv6_or_vfpv3")
(set_attr "type" "fdivd")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuls")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vmul%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuld")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && !flag_rounding_math"
"vnmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuls")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vnmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuls")]
)
&& !flag_rounding_math"
"vnmul%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuld")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vnmul%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuld")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vmla%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vmla%?.f64\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vnmls%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vnmls%?.f64\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vmls%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vmls%?.f64\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vnmla%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vnmla%?.f64\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
(fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
(match_operand:SDF 2 "register_operand" "<F_constraint>")
(match_operand:SDF 3 "register_operand" "0")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>"
"vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
"<F_constraint>"))
(match_operand:SDF 2 "register_operand" "<F_constraint>")
(match_operand:SDF 3 "register_operand" "0")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>"
"vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
(fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
(match_operand:SDF 2 "register_operand" "<F_constraint>")
(neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>"
"vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
"<F_constraint>"))
(match_operand:SDF 2 "register_operand" "<F_constraint>")
(neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>"
"vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.f64.f32\\t%P0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.f32.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)"
"vcvtb%?.f32.f16\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
"TARGET_32BIT && TARGET_FP16_TO_DOUBLE"
"vcvtb%?.f16.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
"TARGET_32BIT && TARGET_FP16_TO_DOUBLE"
"vcvtb%?.f64.f16\\t%P0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)"
"vcvtb%?.f16.f32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.s32.f32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.s32.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.u32.f32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.u32.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.f32.s32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.f64.s32\\t%P0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.f32.u32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.f64.u32\\t%P0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vsqrt%?.f32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "arch" "*,armv6_or_vfpv3")
(set_attr "type" "fsqrts")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vsqrt%?.f64\\t%P0, %P1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "arch" "*,armv6_or_vfpv3")
(set_attr "type" "fsqrtd")]
)
vcmp%?.f32\\t%0, %1
vcmp%?.f32\\t%0, #0"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fcmps")]
)
vcmpe%?.f32\\t%0, %1
vcmpe%?.f32\\t%0, #0"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fcmps")]
)
vcmp%?.f64\\t%P0, %P1
vcmp%?.f64\\t%P0, #0"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fcmpd")]
)
vcmpe%?.f64\\t%P0, %P1
vcmpe%?.f64\\t%P0, #0"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fcmpd")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
"vcvt%?.f32.<FCVTI32typename>\\t%0, %1, %v2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
[(set_attr "predicable" "yes")
(set_attr "ce_count" "2")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")
(set_attr "length" "8")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
"vcvt%?.s32.f32\\t%0, %1, %v2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
(float_truncate:HF (float:SF (match_dup 0))))]
"TARGET_VFP_FP16INST"
{
- neon_const_bounds (operands[2], 1, 33);
+ arm_const_bounds (operands[2], 1, 33);
return "vcvt.f16.<sup>32\t%0, %0, %2\;vmov.f32\t%3, %0";
}
[(set_attr "conds" "unconditional")
{
rtx op1 = gen_reg_rtx (SImode);
- neon_const_bounds (operands[2], 1, 33);
+ arm_const_bounds (operands[2], 1, 33);
emit_move_insn (op1, operands[1]);
emit_insn (gen_neon_vcvth<sup>_nhf_unspec (op1, op1, operands[2],
VCVT_SI_US_N))]
"TARGET_VFP_FP16INST"
{
- neon_const_bounds (operands[2], 1, 33);
+ arm_const_bounds (operands[2], 1, 33);
return "vmov.f32\t%0, %1\;vcvt.<sup>%#32.f16\t%0, %0, %2";
}
[(set_attr "conds" "unconditional")
{
rtx op1 = gen_reg_rtx (SImode);
- neon_const_bounds (operands[2], 1, 33);
+ arm_const_bounds (operands[2], 1, 33);
emit_insn (gen_neon_vcvth<sup>_nsi_unspec (op1, operands[1], operands[2]));
emit_move_insn (operands[0], op1);
DONE;
"TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
"vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
[(set_attr "predicable" "<vrint_predicable>")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_rint<vfp_type>")
(set_attr "conds" "<vrint_conds>")]
)
(FIXUORS:SI (unspec:SDF
[(match_operand:SDF 1
"register_operand" "<F_constraint>")] VCVT)))]
- "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
+ "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
"vcvt<vrint_variant>.<su>32.<V_if_elem>\\t%0, %<V_reg>1"
- [(set_attr "predicable" "no")
- (set_attr "conds" "unconditional")
+ [(set_attr "conds" "unconditional")
(set_attr "type" "f_cvtf2i")]
)
;; fmdhr et al (VFPv1)
;; Support for xD (single precision only) variants.
;; fmrrs, fmsrr
+
+;; Load a DF immediate via GPR (where combinations of MOV and MOVT can be used)
+;; and then move it into a VFP register.
+(define_insn_and_split "no_literal_pool_df_immediate"
+ [(set (match_operand:DF 0 "s_register_operand" "=w")
+ (match_operand:DF 1 "const_double_operand" "F"))
+ (clobber (match_operand:DF 2 "s_register_operand" "=r"))]
+ "arm_disable_literal_pool
+ && TARGET_HARD_FLOAT
+ && !arm_const_double_rtx (operands[1])
+ && !(TARGET_VFP_DOUBLE && vfp3_const_double_rtx (operands[1]))"
+ "#"
+ ""
+ [(const_int 0)]
+{
+ long buf[2];
+ int order = BYTES_BIG_ENDIAN ? 1 : 0;
+ real_to_target (buf, CONST_DOUBLE_REAL_VALUE (operands[1]), DFmode);
+ unsigned HOST_WIDE_INT ival = zext_hwi (buf[order], 32);
+ ival |= (zext_hwi (buf[1 - order], 32) << 32);
+ rtx cst = gen_int_mode (ival, DImode);
+ emit_move_insn (simplify_gen_subreg (DImode, operands[2], DFmode, 0), cst);
+ emit_move_insn (operands[0], operands[2]);
+ DONE;
+}
+)
+
+;; Load a SF immediate via GPR (where combinations of MOV and MOVT can be used)
+;; and then move it into a VFP register.
+(define_insn_and_split "no_literal_pool_sf_immediate"
+ [(set (match_operand:SF 0 "s_register_operand" "=t")
+ (match_operand:SF 1 "const_double_operand" "E"))
+ (clobber (match_operand:SF 2 "s_register_operand" "=r"))]
+ "arm_disable_literal_pool
+ && TARGET_HARD_FLOAT
+ && !vfp3_const_double_rtx (operands[1])"
+ "#"
+ ""
+ [(const_int 0)]
+{
+ long buf;
+ real_to_target (&buf, CONST_DOUBLE_REAL_VALUE (operands[1]), SFmode);
+ rtx cst = gen_int_mode (buf, SImode);
+ emit_move_insn (simplify_gen_subreg (SImode, operands[2], SFmode, 0), cst);
+ emit_move_insn (operands[0], operands[2]);
+ DONE;
+}
+)