Update copyright years.

[thirdparty/gcc.git] / gcc / config / bfin / bfin.opt

diff --git a/gcc/config/bfin/bfin.opt b/gcc/config/bfin/bfin.opt
index b09d4ddf177781de4e1d980b59e2933946b65a2d..042170ed15aba2fa6c5755845fbe744946b4c186 100644 (file)
--- a/gcc/config/bfin/bfin.opt
+++ b/gcc/config/bfin/bfin.opt
@@ -1,12 +1,12 @@
 ; Options for the Blackfin port of the compiler
 ;
-; Copyright (C) 2005 Free Software Foundation, Inc.
+; Copyright (C) 2005-2024 Free Software Foundation, Inc.
 ;
 ; This file is part of GCC.
 ;
 ; GCC is free software; you can redistribute it and/or modify it under
 ; the terms of the GNU General Public License as published by the Free
-; Software Foundation; either version 2, or (at your option) any later
+; Software Foundation; either version 3, or (at your option) any later
 ; version.
 ;
 ; GCC is distributed in the hope that it will be useful, but WITHOUT
@@ -15,22 +15,104 @@
 ; License for more details.
 ;
 ; You should have received a copy of the GNU General Public License
-; along with GCC; see the file COPYING.  If not, write to the Free
-; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-; 02111-1307, USA.
+; along with GCC; see the file COPYING3.  If not see
+; <http://www.gnu.org/licenses/>.
+
+HeaderInclude
+config/bfin/bfin-opts.h
+
+; Value of -mcpu=.
+Variable
+bfin_cpu_t bfin_cpu_type = BFIN_CPU_UNKNOWN
+
+; -msi-revision support. There are three special values:
+; -1      -msi-revision=none.
+; 0xffff  -msi-revision=any.
+Variable
+int bfin_si_revision
+
+; The workarounds enabled.
+Variable
+unsigned int bfin_workarounds = 0
+
+msim
+Target RejectNegative
+Use simulator runtime.
+
+mcpu=
+Target RejectNegative Joined
+Specify the name of the target CPU.
 
 momit-leaf-frame-pointer
-Target Report Mask(OMIT_LEAF_FRAME_POINTER)
-Omit frame pointer for leaf functions
+Target Mask(OMIT_LEAF_FRAME_POINTER)
+Omit frame pointer for leaf functions.
 
 mlow64k
-Target Report Mask(LOW_64K)
+Target Mask(LOW_64K)
 Program is entirely located in low 64k of memory.
 
-mcsync
-Target Report Mask(CSYNC)
-Avoid speculative loads by inserting CSYNC or equivalent
+mcsync-anomaly
+Target Var(bfin_csync_anomaly) Init(-1)
+Work around a hardware anomaly by adding a number of NOPs before a
+CSYNC or SSYNC instruction.
+
+mspecld-anomaly
+Target Var(bfin_specld_anomaly) Init(-1)
+Avoid speculative loads to work around a hardware anomaly.
 
 mid-shared-library
-Target Report Mask(ID_SHARED_LIBRARY)
-Enabled ID based shared library
+Target Mask(ID_SHARED_LIBRARY)
+Enabled ID based shared library.
+
+mleaf-id-shared-library
+Target Mask(LEAF_ID_SHARED_LIBRARY)
+Generate code that won't be linked against any other ID shared libraries,
+but may be used as a shared library.
+
+mshared-library-id=
+Target RejectNegative Joined UInteger Var(bfin_library_id)
+ID of shared library to build.
+
+msep-data
+Target Mask(SEP_DATA)
+Enable separate data segment.
+
+mlong-calls
+Target Mask(LONG_CALLS)
+Avoid generating pc-relative calls; use indirection.
+
+mfast-fp
+Target Mask(FAST_FP)
+Link with the fast floating-point library.
+
+mfdpic
+Target Mask(FDPIC)
+Enable Function Descriptor PIC mode.
+
+minline-plt
+Target Mask(INLINE_PLT)
+Enable inlining of PLT in function calls.
+
+mstack-check-l1
+Target Mask(STACK_CHECK_L1)
+Do stack checking using bounds in L1 scratch memory.
+
+mmulticore
+Target Mask(MULTICORE)
+Enable multicore support.
+
+mcorea
+Target Mask(COREA)
+Build for Core A.
+
+mcoreb
+Target Mask(COREB)
+Build for Core B.
+
+msdram
+Target Mask(SDRAM)
+Build for SDRAM.
+
+micplb
+Target Mask(ICPLB)
+Assume ICPLBs are enabled at runtime.