;; Predicate definitions for code generation on the EPIPHANY cpu.
-;; Copyright (C) 1994-2013 Free Software Foundation, Inc.
+;; Copyright (C) 1994-2020 Free Software Foundation, Inc.
;; Contributed by Embecosm on behalf of Adapteva, Inc.
;;
;; This file is part of GCC.
{
if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
return add_reg_operand (op, mode);
- return satisfies_constraint_L (op);
+ return satisfies_constraint_L (op) || satisfies_constraint_CnL (op);
})
;; Ordinary 3rd operand for arithmetic operations
return 0;
switch (GET_MODE (cc))
{
- case CC_Zmode:
- case CC_N_NEmode:
- case CC_FP_EQmode:
+ case E_CC_Zmode:
+ case E_CC_N_NEmode:
+ case E_CC_FP_EQmode:
return REGNO (cc) == CC_REGNUM && (code == EQ || code == NE);
- case CC_C_LTUmode:
+ case E_CC_C_LTUmode:
return REGNO (cc) == CC_REGNUM && (code == LTU || code == GEU);
- case CC_C_GTUmode:
+ case E_CC_C_GTUmode:
return REGNO (cc) == CC_REGNUM && (code == GTU || code == LEU);
- case CC_FPmode:
+ case E_CC_FPmode:
return (REGNO (cc) == CCFP_REGNUM
&& (code == EQ || code == NE || code == LT || code == LE));
- case CC_FP_GTEmode:
+ case E_CC_FP_GTEmode:
return (REGNO (cc) == CC_REGNUM
&& (code == EQ || code == NE || code == GT || code == GE
|| code == UNLE || code == UNLT));
- case CC_FP_ORDmode:
+ case E_CC_FP_ORDmode:
return REGNO (cc) == CC_REGNUM && (code == ORDERED || code == UNORDERED);
- case CC_FP_UNEQmode:
+ case E_CC_FP_UNEQmode:
return REGNO (cc) == CC_REGNUM && (code == UNEQ || code == LTGT);
- case CCmode:
+ case E_CCmode:
return REGNO (cc) == CC_REGNUM;
/* From combiner. */
- case QImode: case SImode: case SFmode: case HImode:
+ case E_QImode: case E_SImode: case E_SFmode: case E_HImode:
/* From cse.c:dead_libcall_p. */
- case DFmode:
+ case E_DFmode:
return 0;
default:
gcc_unreachable ();
bool inserted = MACHINE_FUNCTION (cfun)->control_use_inserted;
int i;
- if (count == 2)
+ if (count == 2
+ /* Vector ashift has an extra use for the constant factor required to
+ implement the shift as multiply. */
+ || (count == 3 && GET_CODE (XVECEXP (op, 0, 0)) == SET
+ && GET_CODE (XEXP (XVECEXP (op, 0, 0), 1)) == ASHIFT))
return !inserted;
/* combine / recog will pass any old garbage here before checking the
i = 1;
if (count > 4)
- for (i = 4; i < count; i++)
+ for (i = 2; i < count; i++)
{
rtx x = XVECEXP (op, 0, i);
(and (match_code "mem")
(match_test "post_modify_address (XEXP (op, 0), Pmode)")))
+; used in the memory clobber of stack_adjust_str, allows addresses with
+; large offsets.
+(define_predicate "memclob_operand"
+ (match_code "mem"))
+
(define_predicate "nonsymbolic_immediate_operand"
(ior (match_test "immediate_operand (op, mode)")
(match_code "const_vector"))) /* Is this specific enough? */