Update copyright years.

[thirdparty/gcc.git] / gcc / config / i386 / cpuid.h

diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index a16c2d7a5b863fbc2d54882523c1c44c50cf86d1..34a7956d36aa4d880975317b041629a8398df0ef 100644 (file)
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007-2017 Free Software Foundation, Inc.
+ * Copyright (C) 2007-2020 Free Software Foundation, Inc.
  *
  * This file is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -21,6 +21,9 @@
  * <http://www.gnu.org/licenses/>.
  */
 
+/* %eax */
+#define bit_AVX512BF16 (1 << 5)
+
 /* %ecx */
 #define bit_SSE3       (1 << 0)
 #define bit_PCLMUL     (1 << 1)
@@ -67,6 +70,7 @@
 
 /* %ebx  */
 #define bit_CLZERO     (1 << 0)
+#define bit_WBNOINVD   (1 << 9)
 
 /* Extended Features (%eax == 7) */
 /* %ebx */
@@ -97,14 +101,27 @@
 #define bit_AVX512VBMI (1 << 1)
 #define bit_PKU        (1 << 3)
 #define bit_OSPKE      (1 << 4)
+#define bit_WAITPKG    (1 << 5)
+#define bit_AVX512VBMI2        (1 << 6)
+#define bit_SHSTK      (1 << 7)
 #define bit_GFNI       (1 << 8)
+#define bit_VAES       (1 << 9)
+#define bit_AVX512VNNI (1 << 11)
+#define bit_VPCLMULQDQ (1 << 10)
+#define bit_AVX512BITALG       (1 << 12)
 #define bit_AVX512VPOPCNTDQ    (1 << 14)
 #define bit_RDPID      (1 << 22)
+#define bit_MOVDIRI    (1 << 27)
+#define bit_MOVDIR64B  (1 << 28)
+#define bit_ENQCMD     (1 << 29)
+#define bit_CLDEMOTE   (1 << 25)
 
 /* %edx */
 #define bit_AVX5124VNNIW (1 << 2)
 #define bit_AVX5124FMAPS (1 << 3)
-
+#define bit_AVX512VP2INTERSECT (1 << 8)
+#define bit_IBT        (1 << 20)
+#define bit_PCONFIG    (1 << 18)
 /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
 #define bit_BNDREGS     (1 << 3)
 #define bit_BNDCSR      (1 << 4)
@@ -114,6 +131,10 @@
 #define bit_XSAVEC     (1 << 1)
 #define bit_XSAVES     (1 << 3)
 
+/* PT sub leaf (%eax == 14, %ecx == 0) */
+/* %ebx */
+#define bit_PTWRITE    (1 << 4)
+
 /* Signatures for different CPU implementations as returned in uses
    of cpuid with level 0.  */
 #define signature_AMD_ebx      0x68747541
@@ -168,10 +189,27 @@
 #define signature_VORTEX_ecx   0x436f5320
 #define signature_VORTEX_edx   0x36387865
 
+#ifndef __x86_64__
+/* At least one cpu (Winchip 2) does not set %ebx and %ecx
+   for cpuid leaf 1. Forcibly zero the two registers before
+   calling cpuid as a precaution.  */
+#define __cpuid(level, a, b, c, d)                     \
+  do {                                                 \
+    if (__builtin_constant_p (level) && (level) != 1)  \
+      __asm__ ("cpuid\n\t"                             \
+             : "=a" (a), "=b" (b), "=c" (c), "=d" (d)  \
+             : "0" (level));                           \
+    else                                               \
+      __asm__ ("cpuid\n\t"                             \
+             : "=a" (a), "=b" (b), "=c" (c), "=d" (d)  \
+             : "0" (level), "1" (0), "2" (0));         \
+  } while (0)
+#else
 #define __cpuid(level, a, b, c, d)                     \
   __asm__ ("cpuid\n\t"                                 \
           : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
           : "0" (level))
+#endif
 
 #define __cpuid_count(level, count, a, b, c, d)                \
   __asm__ ("cpuid\n\t"                                 \