/* Subroutines for the gcc driver.
- Copyright (C) 2006-2013 Free Software Foundation, Inc.
+ Copyright (C) 2006-2020 Free Software Foundation, Inc.
This file is part of GCC.
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
+#define IN_TARGET_CODE 1
+
#include "config.h"
#include "system.h"
#include "coretypes.h"
const char *host_detect_local_cpu (int argc, const char **argv);
-#ifdef __GNUC__
+#if defined(__GNUC__) && (__GNUC__ >= 5 || !defined(__PIC__))
#include "cpuid.h"
struct cache_desc
case 0x0c:
level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
break;
+ case 0x0d:
+ level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
+ break;
+ case 0x0e:
+ level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
+ break;
+ case 0x21:
+ level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
+ break;
+ case 0x24:
+ level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
+ break;
case 0x2c:
level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
break;
case 0x45:
level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
break;
+ case 0x48:
+ level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
+ break;
case 0x49:
if (xeon_mp)
break;
case 0x7f:
level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
break;
+ case 0x80:
+ level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
+ break;
case 0x82:
level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
break;
unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
- unsigned int has_hle = 0, has_rtm = 0;
+ unsigned int has_hle = 0, has_rtm = 0, has_sgx = 0;
+ unsigned int has_pconfig = 0, has_wbnoinvd = 0;
unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
+ unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
+ unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
+ unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
+ unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
+ unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
+ unsigned int has_mwaitx = 0, has_clzero = 0, has_pku = 0, has_rdpid = 0;
+ unsigned int has_avx5124fmaps = 0, has_avx5124vnniw = 0;
+ unsigned int has_gfni = 0, has_avx512vbmi2 = 0;
+ unsigned int has_avx512bitalg = 0;
+ unsigned int has_shstk = 0;
+ unsigned int has_avx512vnni = 0, has_vaes = 0;
+ unsigned int has_vpclmulqdq = 0;
+ unsigned int has_avx512vp2intersect = 0;
+ unsigned int has_movdiri = 0, has_movdir64b = 0;
+ unsigned int has_enqcmd = 0;
+ unsigned int has_waitpkg = 0;
+ unsigned int has_cldemote = 0;
+ unsigned int has_avx512bf16 = 0;
+
+ unsigned int has_ptwrite = 0;
bool arch;
model = (eax >> 4) & 0x0f;
family = (eax >> 8) & 0x0f;
- if (vendor == signature_INTEL_ebx)
+ if (vendor == signature_INTEL_ebx
+ || vendor == signature_AMD_ebx)
{
unsigned int extended_model, extended_family;
__cpuid_count (7, 0, eax, ebx, ecx, edx);
has_bmi = ebx & bit_BMI;
+ has_sgx = ebx & bit_SGX;
has_hle = ebx & bit_HLE;
has_rtm = ebx & bit_RTM;
has_avx2 = ebx & bit_AVX2;
has_fsgsbase = ebx & bit_FSGSBASE;
has_rdseed = ebx & bit_RDSEED;
has_adx = ebx & bit_ADX;
+ has_avx512f = ebx & bit_AVX512F;
+ has_avx512er = ebx & bit_AVX512ER;
+ has_avx512pf = ebx & bit_AVX512PF;
+ has_avx512cd = ebx & bit_AVX512CD;
+ has_sha = ebx & bit_SHA;
+ has_clflushopt = ebx & bit_CLFLUSHOPT;
+ has_clwb = ebx & bit_CLWB;
+ has_avx512dq = ebx & bit_AVX512DQ;
+ has_avx512bw = ebx & bit_AVX512BW;
+ has_avx512vl = ebx & bit_AVX512VL;
+ has_avx512ifma = ebx & bit_AVX512IFMA;
+
+ has_prefetchwt1 = ecx & bit_PREFETCHWT1;
+ has_avx512vbmi = ecx & bit_AVX512VBMI;
+ has_pku = ecx & bit_OSPKE;
+ has_avx512vbmi2 = ecx & bit_AVX512VBMI2;
+ has_avx512vnni = ecx & bit_AVX512VNNI;
+ has_rdpid = ecx & bit_RDPID;
+ has_gfni = ecx & bit_GFNI;
+ has_vaes = ecx & bit_VAES;
+ has_vpclmulqdq = ecx & bit_VPCLMULQDQ;
+ has_avx512bitalg = ecx & bit_AVX512BITALG;
+ has_movdiri = ecx & bit_MOVDIRI;
+ has_movdir64b = ecx & bit_MOVDIR64B;
+ has_enqcmd = ecx & bit_ENQCMD;
+ has_cldemote = ecx & bit_CLDEMOTE;
+
+ has_avx5124vnniw = edx & bit_AVX5124VNNIW;
+ has_avx5124fmaps = edx & bit_AVX5124FMAPS;
+ has_avx512vp2intersect = edx & bit_AVX512VP2INTERSECT;
+
+ has_shstk = ecx & bit_SHSTK;
+ has_pconfig = edx & bit_PCONFIG;
+ has_waitpkg = ecx & bit_WAITPKG;
+
+ __cpuid_count (7, 1, eax, ebx, ecx, edx);
+ has_avx512bf16 = eax & bit_AVX512BF16;
}
if (max_level >= 13)
__cpuid_count (13, 1, eax, ebx, ecx, edx);
has_xsaveopt = eax & bit_XSAVEOPT;
+ has_xsavec = eax & bit_XSAVEC;
+ has_xsaves = eax & bit_XSAVES;
}
- /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */
-#define XCR_XFEATURE_ENABLED_MASK 0x0
-#define XSTATE_FP 0x1
-#define XSTATE_SSE 0x2
-#define XSTATE_YMM 0x4
- if (has_osxsave)
- asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
- : "=a" (eax), "=d" (edx)
- : "c" (XCR_XFEATURE_ENABLED_MASK));
-
- /* Check if SSE and YMM states are supported. */
- if (!has_osxsave
- || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM))
+ if (max_level >= 0x14)
{
- has_avx = 0;
- has_avx2 = 0;
- has_fma = 0;
- has_fma4 = 0;
- has_xop = 0;
- has_xsave = 0;
- has_xsaveopt = 0;
+ __cpuid_count (0x14, 0, eax, ebx, ecx, edx);
+
+ has_ptwrite = ebx & bit_PTWRITE;
}
/* Check cpuid level of extended features. */
__cpuid (0x80000000, ext_level, ebx, ecx, edx);
- if (ext_level > 0x80000000)
+ if (ext_level >= 0x80000001)
{
__cpuid (0x80000001, eax, ebx, ecx, edx);
has_longmode = edx & bit_LM;
has_3dnowp = edx & bit_3DNOWP;
has_3dnow = edx & bit_3DNOW;
+ has_mwaitx = ecx & bit_MWAITX;
+ }
+
+ if (ext_level >= 0x80000008)
+ {
+ __cpuid (0x80000008, eax, ebx, ecx, edx);
+ has_clzero = ebx & bit_CLZERO;
+ has_wbnoinvd = ebx & bit_WBNOINVD;
+ }
+
+ /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */
+#define XCR_XFEATURE_ENABLED_MASK 0x0
+#define XSTATE_FP 0x1
+#define XSTATE_SSE 0x2
+#define XSTATE_YMM 0x4
+#define XSTATE_OPMASK 0x20
+#define XSTATE_ZMM 0x40
+#define XSTATE_HI_ZMM 0x80
+
+#define XCR_AVX_ENABLED_MASK \
+ (XSTATE_SSE | XSTATE_YMM)
+#define XCR_AVX512F_ENABLED_MASK \
+ (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM)
+
+ if (has_osxsave)
+ asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
+ : "=a" (eax), "=d" (edx)
+ : "c" (XCR_XFEATURE_ENABLED_MASK));
+ else
+ eax = 0;
+
+ /* Check if AVX registers are supported. */
+ if ((eax & XCR_AVX_ENABLED_MASK) != XCR_AVX_ENABLED_MASK)
+ {
+ has_avx = 0;
+ has_avx2 = 0;
+ has_fma = 0;
+ has_fma4 = 0;
+ has_f16c = 0;
+ has_xop = 0;
+ has_xsave = 0;
+ has_xsaveopt = 0;
+ has_xsaves = 0;
+ has_xsavec = 0;
+ }
+
+ /* Check if AVX512F registers are supported. */
+ if ((eax & XCR_AVX512F_ENABLED_MASK) != XCR_AVX512F_ENABLED_MASK)
+ {
+ has_avx512f = 0;
+ has_avx512er = 0;
+ has_avx512pf = 0;
+ has_avx512cd = 0;
+ has_avx512dq = 0;
+ has_avx512bw = 0;
+ has_avx512vl = 0;
}
if (!arch)
{
if (vendor == signature_AMD_ebx
- || vendor == signature_CENTAUR_ebx)
+ || vendor == signature_CENTAUR_ebx
+ || vendor == signature_CYRIX_ebx
+ || vendor == signature_NSC_ebx)
cache = detect_caches_amd (ext_level);
else if (vendor == signature_INTEL_ebx)
{
unsigned int name;
/* Detect geode processor by its processor signature. */
- if (ext_level > 0x80000001)
+ if (ext_level >= 0x80000002)
__cpuid (0x80000002, name, ebx, ecx, edx);
else
name = 0;
if (name == signature_NSC_ebx)
processor = PROCESSOR_GEODE;
- else if (has_movbe)
+ else if (has_movbe && family == 22)
processor = PROCESSOR_BTVER2;
+ else if (has_clwb)
+ processor = PROCESSOR_ZNVER2;
+ else if (has_clzero)
+ processor = PROCESSOR_ZNVER1;
+ else if (has_avx2)
+ processor = PROCESSOR_BDVER4;
else if (has_xsaveopt)
processor = PROCESSOR_BDVER3;
else if (has_bmi)
}
else if (vendor == signature_CENTAUR_ebx)
{
- if (arch)
+ processor = PROCESSOR_GENERIC;
+
+ switch (family)
{
- if (family == 6)
- {
- if (model > 9)
- /* Use the default detection procedure. */
- processor = PROCESSOR_GENERIC32;
- else if (model == 9)
- cpu = "c3-2";
- else if (model >= 6)
- cpu = "c3";
- else
- /* We have no idea. */
- processor = PROCESSOR_GENERIC32;
- }
- else if (has_3dnow)
- cpu = "winchip2";
- else if (has_mmx)
- cpu = "winchip2-c6";
- else
- /* We have no idea. */
- processor = PROCESSOR_GENERIC32;
+ default:
+ /* We have no idea. */
+ break;
+
+ case 5:
+ if (has_3dnow || has_mmx)
+ processor = PROCESSOR_I486;
+ break;
+
+ case 6:
+ if (has_longmode)
+ processor = PROCESSOR_K8;
+ else if (model >= 9)
+ processor = PROCESSOR_PENTIUMPRO;
+ else if (model >= 6)
+ processor = PROCESSOR_I486;
}
}
else
break;
default:
/* We have no idea. */
- processor = PROCESSOR_GENERIC32;
+ processor = PROCESSOR_GENERIC;
}
}
/* Default. */
break;
case PROCESSOR_I486:
- cpu = "i486";
+ if (arch && vendor == signature_CENTAUR_ebx)
+ {
+ if (model >= 6)
+ cpu = "c3";
+ else if (has_3dnow)
+ cpu = "winchip2";
+ else
+ /* Assume WinChip C6. */
+ cpu = "winchip-c6";
+ }
+ else
+ cpu = "i486";
break;
case PROCESSOR_PENTIUM:
if (arch && has_mmx)
{
case 0x1c:
case 0x26:
- /* Atom. */
- cpu = "atom";
+ /* Bonnell. */
+ cpu = "bonnell";
+ break;
+ case 0x37:
+ case 0x4a:
+ case 0x4d:
+ case 0x5a:
+ case 0x5d:
+ /* Silvermont. */
+ cpu = "silvermont";
+ break;
+ case 0x5c:
+ case 0x5f:
+ /* Goldmont. */
+ cpu = "goldmont";
+ break;
+ case 0x7a:
+ /* Goldmont Plus. */
+ cpu = "goldmont-plus";
+ break;
+ case 0x0f:
+ /* Merom. */
+ case 0x17:
+ case 0x1d:
+ /* Penryn. */
+ cpu = "core2";
break;
case 0x1a:
case 0x1e:
case 0x1f:
case 0x2e:
/* Nehalem. */
- cpu = "corei7";
+ cpu = "nehalem";
break;
case 0x25:
case 0x2c:
case 0x2f:
/* Westmere. */
- cpu = "corei7";
+ cpu = "westmere";
break;
case 0x2a:
case 0x2d:
/* Sandy Bridge. */
- cpu = "corei7-avx";
+ cpu = "sandybridge";
break;
- case 0x17:
- case 0x1d:
- /* Penryn. */
- cpu = "core2";
+ case 0x3a:
+ case 0x3e:
+ /* Ivy Bridge. */
+ cpu = "ivybridge";
break;
- case 0x0f:
- /* Merom. */
- cpu = "core2";
+ case 0x3c:
+ case 0x3f:
+ case 0x45:
+ case 0x46:
+ /* Haswell. */
+ cpu = "haswell";
+ break;
+ case 0x3d:
+ case 0x47:
+ case 0x4f:
+ case 0x56:
+ /* Broadwell. */
+ cpu = "broadwell";
+ break;
+ case 0x4e:
+ case 0x5e:
+ /* Skylake. */
+ case 0x8e:
+ case 0x9e:
+ /* Kaby Lake. */
+ cpu = "skylake";
+ break;
+ case 0x55:
+ if (has_avx512vnni)
+ /* Cascade Lake. */
+ cpu = "cascadelake";
+ else
+ /* Skylake with AVX-512. */
+ cpu = "skylake-avx512";
+ break;
+ case 0x57:
+ /* Knights Landing. */
+ cpu = "knl";
+ break;
+ case 0x66:
+ /* Cannon Lake. */
+ cpu = "cannonlake";
+ break;
+ case 0x85:
+ /* Knights Mill. */
+ cpu = "knm";
break;
default:
if (arch)
{
/* This is unknown family 0x6 CPU. */
if (has_avx)
+ {
+ /* Assume Tiger Lake */
+ if (has_avx512vp2intersect)
+ cpu = "tigerlake";
+ /* Assume Cooper Lake */
+ else if (has_avx512bf16)
+ cpu = "cooperlake";
+ /* Assume Ice Lake Server. */
+ else if (has_wbnoinvd)
+ cpu = "icelake-server";
+ /* Assume Ice Lake. */
+ else if (has_avx512bitalg)
+ cpu = "icelake-client";
+ /* Assume Cannon Lake. */
+ else if (has_avx512vbmi)
+ cpu = "cannonlake";
+ /* Assume Knights Mill. */
+ else if (has_avx5124vnniw)
+ cpu = "knm";
+ /* Assume Knights Landing. */
+ else if (has_avx512er)
+ cpu = "knl";
+ /* Assume Skylake with AVX-512. */
+ else if (has_avx512f)
+ cpu = "skylake-avx512";
+ /* Assume Skylake. */
+ else if (has_clflushopt)
+ cpu = "skylake";
+ /* Assume Broadwell. */
+ else if (has_adx)
+ cpu = "broadwell";
+ else if (has_avx2)
+ /* Assume Haswell. */
+ cpu = "haswell";
+ else
/* Assume Sandy Bridge. */
- cpu = "corei7-avx";
+ cpu = "sandybridge";
+ }
else if (has_sse4_2)
- /* Assume Core i7. */
- cpu = "corei7";
+ {
+ if (has_gfni)
+ /* Assume Tremont. */
+ cpu = "tremont";
+ else if (has_sgx)
+ /* Assume Goldmont Plus. */
+ cpu = "goldmont-plus";
+ else if (has_xsave)
+ /* Assume Goldmont. */
+ cpu = "goldmont";
+ else if (has_movbe)
+ /* Assume Silvermont. */
+ cpu = "silvermont";
+ else
+ /* Assume Nehalem. */
+ cpu = "nehalem";
+ }
else if (has_ssse3)
{
if (has_movbe)
- /* Assume Atom. */
- cpu = "atom";
+ /* Assume Bonnell. */
+ cpu = "bonnell";
else
/* Assume Core 2. */
cpu = "core2";
}
+ else if (has_longmode)
+ /* Perhaps some emulator? Assume x86-64, otherwise gcc
+ -march=native would be unusable for 64-bit compilations,
+ as all the CPUs below are 32-bit only. */
+ cpu = "x86-64";
else if (has_sse3)
- /* It is Core Duo. */
- cpu = "pentium-m";
+ {
+ if (vendor == signature_CENTAUR_ebx)
+ /* C7 / Eden "Esther" */
+ cpu = "c7";
+ else
+ /* It is Core Duo. */
+ cpu = "pentium-m";
+ }
else if (has_sse2)
/* It is Pentium M. */
cpu = "pentium-m";
else if (has_sse)
- /* It is Pentium III. */
- cpu = "pentium3";
+ {
+ if (vendor == signature_CENTAUR_ebx)
+ {
+ if (model >= 9)
+ /* Eden "Nehemiah" */
+ cpu = "nehemiah";
+ else
+ cpu = "c3-2";
+ }
+ else
+ /* It is Pentium III. */
+ cpu = "pentium3";
+ }
else if (has_mmx)
/* It is Pentium II. */
cpu = "pentium2";
cpu = "athlon";
break;
case PROCESSOR_K8:
- if (arch && has_sse3)
- cpu = "k8-sse3";
+ if (arch)
+ {
+ if (vendor == signature_CENTAUR_ebx)
+ {
+ if (has_sse4_1)
+ /* Nano 3000 | Nano dual / quad core | Eden X4 */
+ cpu = "nano-3000";
+ else if (has_ssse3)
+ /* Nano 1000 | Nano 2000 */
+ cpu = "nano";
+ else if (has_sse3)
+ /* Eden X2 */
+ cpu = "eden-x2";
+ else
+ /* Default to k8 */
+ cpu = "k8";
+ }
+ else if (has_sse3)
+ cpu = "k8-sse3";
+ else
+ cpu = "k8";
+ }
else
+ /* For -mtune, we default to -mtune=k8 */
cpu = "k8";
break;
case PROCESSOR_AMDFAM10:
case PROCESSOR_BDVER3:
cpu = "bdver3";
break;
+ case PROCESSOR_BDVER4:
+ cpu = "bdver4";
+ break;
+ case PROCESSOR_ZNVER1:
+ cpu = "znver1";
+ break;
+ case PROCESSOR_ZNVER2:
+ cpu = "znver2";
+ break;
case PROCESSOR_BTVER1:
cpu = "btver1";
break;
else
cpu = "prescott";
}
+ else if (has_longmode)
+ /* Perhaps some emulator? Assume x86-64, otherwise gcc
+ -march=native would be unusable for 64-bit compilations,
+ as all the CPUs below are 32-bit only. */
+ cpu = "x86-64";
else if (has_sse2)
cpu = "pentium4";
else if (has_cmov)
if (arch)
{
+ const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
+ const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
+ const char *sse = has_sse ? " -msse" : " -mno-sse";
+ const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
+ const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
+ const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
+ const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
- const char *ase = has_aes ? " -maes" : " -mno-aes";
+ const char *aes = has_aes ? " -maes" : " -mno-aes";
+ const char *sha = has_sha ? " -msha" : " -mno-sha";
const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
const char *abm = has_abm ? " -mabm" : " -mno-abm";
const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
const char *xop = has_xop ? " -mxop" : " -mno-xop";
const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
+ const char *pconfig = has_pconfig ? " -mpconfig" : " -mno-pconfig";
+ const char *wbnoinvd = has_wbnoinvd ? " -mwbnoinvd" : " -mno-wbnoinvd";
+ const char *sgx = has_sgx ? " -msgx" : " -mno-sgx";
const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
const char *avx = has_avx ? " -mavx" : " -mno-avx";
const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
-
- options = concat (options, cx16, sahf, movbe, ase, pclmul,
- popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
+ const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
+ const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
+ const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
+ const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
+ const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
+ const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
+ const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
+ const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
+ const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
+ const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
+ const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
+ const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
+ const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
+ const char *avx5124vnniw = has_avx5124vnniw ? " -mavx5124vnniw" : " -mno-avx5124vnniw";
+ const char *avx512vbmi2 = has_avx512vbmi2 ? " -mavx512vbmi2" : " -mno-avx512vbmi2";
+ const char *avx512vnni = has_avx512vnni ? " -mavx512vnni" : " -mno-avx512vnni";
+ const char *avx5124fmaps = has_avx5124fmaps ? " -mavx5124fmaps" : " -mno-avx5124fmaps";
+ const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
+ const char *mwaitx = has_mwaitx ? " -mmwaitx" : " -mno-mwaitx";
+ const char *clzero = has_clzero ? " -mclzero" : " -mno-clzero";
+ const char *pku = has_pku ? " -mpku" : " -mno-pku";
+ const char *rdpid = has_rdpid ? " -mrdpid" : " -mno-rdpid";
+ const char *gfni = has_gfni ? " -mgfni" : " -mno-gfni";
+ const char *shstk = has_shstk ? " -mshstk" : " -mno-shstk";
+ const char *vaes = has_vaes ? " -mvaes" : " -mno-vaes";
+ const char *vpclmulqdq = has_vpclmulqdq ? " -mvpclmulqdq" : " -mno-vpclmulqdq";
+ const char *avx512vp2intersect = has_avx512vp2intersect ? " -mavx512vp2intersect" : " -mno-avx512vp2intersect";
+ const char *avx512bitalg = has_avx512bitalg ? " -mavx512bitalg" : " -mno-avx512bitalg";
+ const char *movdiri = has_movdiri ? " -mmovdiri" : " -mno-movdiri";
+ const char *movdir64b = has_movdir64b ? " -mmovdir64b" : " -mno-movdir64b";
+ const char *enqcmd = has_enqcmd ? " -menqcmd" : " -mno-enqcmd";
+ const char *waitpkg = has_waitpkg ? " -mwaitpkg" : " -mno-waitpkg";
+ const char *cldemote = has_cldemote ? " -mcldemote" : " -mno-cldemote";
+ const char *ptwrite = has_ptwrite ? " -mptwrite" : " -mno-ptwrite";
+ const char *avx512bf16 = has_avx512bf16 ? " -mavx512bf16" : " -mno-avx512bf16";
+
+ options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
+ sse4a, cx16, sahf, movbe, aes, sha, pclmul,
+ popcnt, abm, lwp, fma, fma4, xop, bmi, sgx, bmi2,
+ pconfig, wbnoinvd,
tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
- fxsr, xsave, xsaveopt, NULL);
+ fxsr, xsave, xsaveopt, avx512f, avx512er,
+ avx512cd, avx512pf, prefetchwt1, clflushopt,
+ xsavec, xsaves, avx512dq, avx512bw, avx512vl,
+ avx512ifma, avx512vbmi, avx5124fmaps, avx5124vnniw,
+ clwb, mwaitx, clzero, pku, rdpid, gfni, shstk,
+ avx512vbmi2, avx512vnni, vaes, vpclmulqdq,
+ avx512bitalg, movdiri, movdir64b, waitpkg, cldemote,
+ ptwrite, avx512bf16, enqcmd, avx512vp2intersect,
+ NULL);
}
done:
}
#else
-/* If we aren't compiling with GCC then the driver will just ignore
- -march and -mtune "native" target and will leave to the newly
- built compiler to generate code for its default target. */
+/* If we are compiling with GCC where %EBX register is fixed, then the
+ driver will just ignore -march and -mtune "native" target and will leave
+ to the newly built compiler to generate code for its default target. */
-const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED,
- const char **argv ATTRIBUTE_UNUSED)
+const char *host_detect_local_cpu (int, const char **)
{
return NULL;
}
projects / thirdparty / gcc.git / blobdiff