;; For USER_MSR support
UNSPECV_URDMSR
UNSPECV_UWRMSR
+
+ ;; For AMX-TILE
+ UNSPECV_LDTILECFG
+ UNSPECV_STTILECFG
])
;; Constants to represent rounding modes in the ROUND instruction
;; Processor type.
(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
atom,slm,glm,haswell,generic,lujiazui,yongfeng,amdfam10,bdver1,
- bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4"
+ bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4,
+ znver5"
(const (symbol_ref "ix86_schedule")))
;; A basic instruction type. Refinements due to arguments to be
;; Main data type used by the insn
(define_attr "mode"
- "unknown,none,QI,HI,SI,DI,TI,OI,XI,HF,BF,SF,DF,XF,TF,V32HF,V16HF,V8HF,
- V16SF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,V8DF,V4HF,V4BF,V2HF,V2BF"
+ "unknown,none,QI,HI,SI,DI,TI,OI,XI,HF,BF,SF,DF,XF,TF,
+ V32HF,V16HF,V8HF,V4HF,V2HF,V32BF,V16BF,V8BF,V4BF,V2BF,
+ V16SF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,V8DF"
(const_string "unknown"))
;; The CPU unit operations uses.
;; SSE and x87 SFmode and DFmode floating point modes
(define_mode_iterator MODEF [SF DF])
+(define_mode_iterator MODEF248 [BF HF SF (DF "TARGET_SSE2")])
+
;; SSE floating point modes
(define_mode_iterator MODEFH [(HF "TARGET_AVX512FP16") SF DF])
(V64QI "b") (V32HI "w") (V16SI "d") (V8DI "q")])
;; SSE vector suffix for floating point modes
-(define_mode_attr ssevecmodesuffix [(SF "ps") (DF "pd")])
+;; BF HF use same suffix as SF for logic operations.
+(define_mode_attr ssevecmodesuffix [(BF "ps") (HF "ps") (SF "ps") (DF "pd")])
;; SSE vector mode corresponding to a scalar mode
(define_mode_attr ssevecmode
;; AVX512F vector mode corresponding to a scalar mode
(define_mode_attr avx512fvecmode
- [(QI "V64QI") (HI "V32HI") (SI "V16SI") (DI "V8DI") (SF "V16SF") (DF "V8DF")])
+ [(QI "V64QI") (HI "V32HI") (SI "V16SI") (DI "V8DI")
+ (HF "V32HF") (BF "V32BF") (SF "V16SF") (DF "V8DF")])
;; Instruction suffix for REX 64bit operators.
(define_mode_attr rex64suffix [(SI "{l}") (DI "{q}")])
(include "bdver3.md")
(include "btver2.md")
(include "znver.md")
-(include "znver4.md")
+(include "zn4zn5.md")
(include "geode.md")
(include "atom.md")
(include "slm.md")
(set (match_dup 4) (ior:DWIH (match_dup 4) (match_dup 5)))])]
{
split_double_mode (<DWI>mode, &operands[0], 2, &operands[0], &operands[2]);
- /* Placing the SUBREG pieces in pseudos helps reload. */
- for (int i = 0; i < 4; i++)
- if (SUBREG_P (operands[i]))
- operands[i] = force_reg (<MODE>mode, operands[i]);
operands[4] = gen_reg_rtx (<MODE>mode);
(define_insn "@pushfl<mode>2"
[(set (match_operand:W 0 "push_operand" "=<")
- (unspec:W [(match_operand:CC 1 "flags_reg_operand")]
+ (unspec:W [(match_operand 1 "flags_reg_operand")]
UNSPEC_PUSHFL))]
- ""
+ "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_CC"
"pushf{<imodesuffix>}"
[(set_attr "type" "push")
(set_attr "mode" "<MODE>")])
&& !x86_64_immediate_operand (operands[1], DImode)
&& !x86_64_zext_immediate_operand (operands[1], DImode)
&& !((UINTVAL (operands[1]) >> ctz_hwi (UINTVAL (operands[1])))
- & ~(HOST_WIDE_INT) 0xffffffff)
+ & ~HOST_WIDE_INT_C (0xffffffff))
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(set (match_dup 0) (match_dup 1))
(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
[(set (match_operand:SWI48 0 "general_reg_operand")
(match_dup 4))]
{
- HOST_WIDE_INT tmp = INTVAL (operands[1]) & ~(HOST_WIDE_INT)0xff00;
+ HOST_WIDE_INT tmp = INTVAL (operands[1]) & ~HOST_WIDE_INT_C (0xff00);
tmp |= (INTVAL (operands[3]) & 0xff) << 8;
operands[4] = gen_int_mode (tmp, <SWI48:MODE>mode);
})
})
(define_insn_and_split "*add<dwi>3_doubleword"
- [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,&r,&r")
+ [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,&r,&r,&r")
(plus:<DWI>
- (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,r")
- (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o,r<di>,r")))
+ (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,rjO,r")
+ (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o,r,<di>,r")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (PLUS, <DWI>mode, operands, TARGET_APX_NDD)"
"#"
DONE;
}
}
-[(set_attr "isa" "*,*,apx_ndd,apx_ndd")])
+[(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd")])
(define_insn_and_split "*add<dwi>3_doubleword_zext"
[(set (match_operand:<DWI> 0 "nonimmediate_operand" "=r,o,&r,&r")
"split_double_mode (<DWI>mode, &operands[0], 1, &operands[0], &operands[5]);")
(define_insn "*add<mode>_1"
- [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r,r,r,r,r,r")
+ [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r,r,r,r,r")
(plus:SWI48
- (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,r,r,rm,r,m,r")
- (match_operand:SWI48 2 "x86_64_general_operand" "re,BM,0,le,r,e,je,BM")))
+ (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,r,r,rje,jM,r")
+ (match_operand:SWI48 2 "x86_64_general_operand" "re,BM,0,le,r,e,BM")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (PLUS, <MODE>mode, operands, TARGET_APX_NDD)"
{
: "add{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
- [(set_attr "isa" "*,*,*,*,apx_ndd,apx_ndd,apx_ndd,apx_ndd")
+ [(set_attr "isa" "*,*,*,*,apx_ndd,apx_ndd,apx_ndd")
(set (attr "type")
(cond [(eq_attr "alternative" "3")
(const_string "lea")
;; patterns constructed from addsi_1 to match.
(define_insn "addsi_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r")
(zero_extend:DI
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r,r,r,rm")
- (match_operand:SI 2 "x86_64_general_operand" "rBMe,0,le,rBMe,re"))))
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r,r,r,rm,rjM")
+ (match_operand:SI 2 "x86_64_general_operand" "rBMe,0,le,rBMe,r,e"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& ix86_binary_operator_ok (PLUS, SImode, operands, TARGET_APX_NDD)"
: "add{l}\t{%2, %k0|%k0, %2}";
}
}
- [(set_attr "isa" "*,*,*,apx_ndd,apx_ndd")
+ [(set_attr "isa" "*,*,*,apx_ndd,apx_ndd,apx_ndd")
(set (attr "type")
(cond [(eq_attr "alternative" "2")
(const_string "lea")
(eq:CCO
(plus:<QPWI>
(sign_extend:<QPWI>
- (match_operand:<DWI> 1 "nonimmediate_operand" "%0,rm"))
+ (match_operand:<DWI> 1 "nonimmediate_operand" "%0,rjM"))
(match_operand:<QPWI> 3 "const_scalar_int_operand" "n,n"))
(sign_extend:<QPWI>
(plus:<DWI>
[(set_attr "isa" "*,*,apx_ndd,apx_ndd")])
(define_insn "*sub<mode>_1"
- [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>,r,r")
+ [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>,r,r,r")
(minus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "0,0,rm,r")
- (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>,r<i>,<m>")))
+ (match_operand:SWI 1 "nonimmediate_operand" "0,0,rm,rjM,r")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>,r,<i>,<m>")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (MINUS, <MODE>mode, operands, TARGET_APX_NDD)"
"@
sub{<imodesuffix>}\t{%2, %0|%0, %2}
sub{<imodesuffix>}\t{%2, %0|%0, %2}
sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd")
(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(plus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "%0,0,rm,r")
- (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>,r<i>,<m>"))
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,0,rm,rjM,r")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>,r,<i>,<m>"))
(match_dup 1)))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>,r,r")
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>,r,r,r")
(plus:SWI (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, <MODE>mode, operands, TARGET_APX_NDD)"
"@
add{<imodesuffix>}\t{%2, %0|%0, %2}
add{<imodesuffix>}\t{%2, %0|%0, %2}
add{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ add{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
add{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd")
(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(plus:<DWI>
- (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,r")
- (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o,r<di>,o"))
+ (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,rjO,r")
+ (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o,r,<di>,o"))
(match_dup 1)))
- (set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,&r,&r")
+ (set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,&r,&r,&r")
(plus:<DWI> (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, <DWI>mode, operands, TARGET_APX_NDD)"
"#"
else
operands[6] = gen_rtx_ZERO_EXTEND (<DWI>mode, operands[5]);
}
-[(set_attr "isa" "*,*,apx_ndd,apx_ndd")])
+[(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd")])
;; x == 0 with zero flag test can be done also as x < 1U with carry flag
;; test, where the latter is preferrable if we have some carry consuming
})
(define_insn_and_split "*and<dwi>3_doubleword"
- [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,&r,&r")
+ [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,&r,&r,&r")
(and:<DWI>
- (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,r")
- (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o,r<di>,o")))
+ (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,rjO,r")
+ (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o,r,<di>,o")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (AND, <DWI>mode, operands, TARGET_APX_NDD)"
"#"
DONE;
}
-[(set_attr "isa" "*,*,apx_ndd,apx_ndd")])
+[(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd")])
(define_insn "*anddi_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm,r,r,r,r,?k")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm,r,r,r,r,r,?k")
(and:DI
- (match_operand:DI 1 "nonimmediate_operand" "%0,r,0,0,rm,r,qm,k")
- (match_operand:DI 2 "x86_64_szext_general_operand" "Z,Z,re,m,re,m,L,k")))
+ (match_operand:DI 1 "nonimmediate_operand" "%0,r,0,0,rm,rjM,r,qm,k")
+ (match_operand:DI 2 "x86_64_szext_general_operand" "Z,Z,re,m,r,e,m,L,k")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& ix86_binary_operator_ok (AND, DImode, operands, TARGET_APX_NDD)"
and{q}\t{%2, %0|%0, %2}
and{q}\t{%2, %1, %0|%0, %1, %2}
and{q}\t{%2, %1, %0|%0, %1, %2}
+ and{q}\t{%2, %1, %0|%0, %1, %2}
#
#"
- [(set_attr "isa" "x64,apx_ndd,x64,x64,apx_ndd,apx_ndd,x64,avx512bw")
- (set_attr "type" "alu,alu,alu,alu,alu,alu,imovx,msklog")
- (set_attr "length_immediate" "*,*,*,*,*,*,0,*")
+ [(set_attr "isa" "x64,apx_ndd,x64,x64,apx_ndd,apx_ndd,apx_ndd,x64,avx512bw")
+ (set_attr "type" "alu,alu,alu,alu,alu,alu,alu,imovx,msklog")
+ (set_attr "length_immediate" "*,*,*,*,*,*,*,0,*")
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "type" "imovx")
(match_operand 1 "ext_QIreg_operand")))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "SI,SI,DI,DI,DI,DI,SI,DI")])
+ (set_attr "mode" "SI,SI,DI,DI,DI,DI,DI,SI,DI")])
(define_insn_and_split "*anddi_1_btr"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
;; See comment for addsi_1_zext why we do use nonimmediate_operand
(define_insn "*andsi_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
(zero_extend:DI
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,rm,r")
- (match_operand:SI 2 "x86_64_general_operand" "rBMe,re,BM"))))
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,rm,rjM,r")
+ (match_operand:SI 2 "x86_64_general_operand" "rBMe,r,e,BM"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& ix86_binary_operator_ok (AND, SImode, operands, TARGET_APX_NDD)"
"@
and{l}\t{%2, %k0|%k0, %2}
and{l}\t{%2, %1, %k0|%k0, %1, %2}
+ and{l}\t{%2, %1, %k0|%k0, %1, %2}
and{l}\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "type" "alu")
- (set_attr "isa" "*,apx_ndd,apx_ndd")
+ (set_attr "isa" "*,apx_ndd,apx_ndd,apx_ndd")
(set_attr "mode" "SI")])
(define_insn "*and<mode>_1"
- [(set (match_operand:SWI24 0 "nonimmediate_operand" "=rm,r,r,r,Ya,?k")
- (and:SWI24 (match_operand:SWI24 1 "nonimmediate_operand" "%0,0,rm,r,qm,k")
- (match_operand:SWI24 2 "<general_operand>" "r<i>,<m>,r<i>,<m>,L,k")))
+ [(set (match_operand:SWI24 0 "nonimmediate_operand" "=rm,r,r,r,r,Ya,?k")
+ (and:SWI24 (match_operand:SWI24 1 "nonimmediate_operand" "%0,0,rm,rjM,r,qm,k")
+ (match_operand:SWI24 2 "<general_operand>" "r<i>,<m>,r,<i>,<m>,L,k")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (AND, <MODE>mode, operands, TARGET_APX_NDD)"
"@
and{<imodesuffix>}\t{%2, %0|%0, %2}
and{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
and{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ and{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
#
#"
[(set (attr "isa")
- (cond [(eq_attr "alternative" "2,3")
+ (cond [(eq_attr "alternative" "2,3,4")
(const_string "apx_ndd")
- (eq_attr "alternative" "5")
+ (eq_attr "alternative" "6")
(if_then_else (eq_attr "mode" "SI")
(const_string "avx512bw")
(const_string "avx512f"))
]
(const_string "*")))
- (set_attr "type" "alu,alu,alu,alu,imovx,msklog")
- (set_attr "length_immediate" "*,*,*,*,0,*")
+ (set_attr "type" "alu,alu,alu,alu,alu,imovx,msklog")
+ (set_attr "length_immediate" "*,*,*,*,*,0,*")
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "type" "imovx")
(match_operand 1 "ext_QIreg_operand")))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "<MODE>,<MODE>,<MODE>,<MODE>,SI,<MODE>")])
+ (set_attr "mode" "<MODE>,<MODE>,<MODE>,<MODE>,<MODE>,SI,<MODE>")])
(define_insn "*andqi_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r,r,?k")
})
(define_insn_and_split "*<code><dwi>3_doubleword"
- [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,&r,&r")
+ [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,&r,&r,&r")
(any_or:<DWI>
- (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,r")
- (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o,r<di>,o")))
+ (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,rjO,r")
+ (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o,r,<di>,o")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <DWI>mode, operands, TARGET_APX_NDD)"
"#"
DONE;
}
-[(set_attr "isa" "*,*,apx_ndd,apx_ndd")])
+[(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd")])
(define_insn "*<code><mode>_1"
- [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,r,r,r,?k")
+ [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,r,r,r,r,?k")
(any_or:SWI248
- (match_operand:SWI248 1 "nonimmediate_operand" "%0,0,rm,r,k")
- (match_operand:SWI248 2 "<general_operand>" "r<i>,<m>,r<i>,<m>,k")))
+ (match_operand:SWI248 1 "nonimmediate_operand" "%0,0,rm,rjM,r,k")
+ (match_operand:SWI248 2 "<general_operand>" "r<i>,<m>,r,<i>,<m>,k")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands, TARGET_APX_NDD)"
"@
<logic>{<imodesuffix>}\t{%2, %0|%0, %2}
<logic>{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
<logic>{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ <logic>{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
#"
- [(set_attr "isa" "*,*,apx_ndd,apx_ndd,<kmov_isa>")
- (set_attr "type" "alu, alu, alu, alu, msklog")
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_ndd,<kmov_isa>")
+ (set_attr "type" "alu, alu, alu, alu, alu, msklog")
(set_attr "mode" "<MODE>")])
(define_insn_and_split "*notxor<mode>_1"
;; See comment for addsi_1_zext why we do use nonimmediate_operand
(define_insn "*<code>si_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
(zero_extend:DI
- (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0,rm,r")
- (match_operand:SI 2 "x86_64_general_operand" "rBMe,re,BM"))))
+ (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0,rm,rjM,r")
+ (match_operand:SI 2 "x86_64_general_operand" "rBMe,r,e,BM"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& ix86_binary_operator_ok (<CODE>, SImode, operands, TARGET_APX_NDD)"
"@
<logic>{l}\t{%2, %k0|%k0, %2}
<logic>{l}\t{%2, %1, %k0|%k0, %1, %2}
+ <logic>{l}\t{%2, %1, %k0|%k0, %1, %2}
<logic>{l}\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "type" "alu")
- (set_attr "isa" "*,apx_ndd,apx_ndd")
+ (set_attr "isa" "*,apx_ndd,apx_ndd,apx_ndd")
(set_attr "mode" "SI")])
(define_insn "*<code>si_1_zext_imm"
(and:QI (match_dup 2) (const_int 63)))) 0)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
- "shld{q}\t{%s2%1, %0|%0, %1, %2}"
+ "shld{q}\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ishift")
(set_attr "prefix_0f" "1")
(set_attr "mode" "DI")
(and:QI (match_dup 3) (const_int 63)))) 0)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_APX_NDD"
- "shld{q}\t{%s3%2, %1, %0|%0, %1, %2, %3}"
+ "shld{q}\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
(and:QI (match_dup 2) (const_int 31)))) 0)))
(clobber (reg:CC FLAGS_REG))]
""
- "shld{l}\t{%s2%1, %0|%0, %1, %2}"
+ "shld{l}\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ishift")
(set_attr "prefix_0f" "1")
(set_attr "mode" "SI")
(and:QI (match_dup 3) (const_int 31)))) 0)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_APX_NDD"
- "shld{l}\t{%s3%2, %1, %0|%0, %1, %2, %3}"
+ "shld{l}\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
(and:QI (match_dup 2) (const_int 63)))) 0)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
- "shrd{q}\t{%s2%1, %0|%0, %1, %2}"
+ "shrd{q}\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ishift")
(set_attr "prefix_0f" "1")
(set_attr "mode" "DI")
(and:QI (match_dup 3) (const_int 63)))) 0)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_APX_NDD"
- "shrd{q}\t{%s3%2, %1, %0|%0, %1, %2, %3}"
+ "shrd{q}\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
(and:QI (match_dup 2) (const_int 31)))) 0)))
(clobber (reg:CC FLAGS_REG))]
""
- "shrd{l}\t{%s2%1, %0|%0, %1, %2}"
+ "shrd{l}\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ishift")
(set_attr "prefix_0f" "1")
(set_attr "mode" "SI")
(and:QI (match_dup 3) (const_int 31)))) 0)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_APX_NDD"
- "shrd{l}\t{%s3%2, %1, %0|%0, %1, %2, %3}"
+ "shrd{l}\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
[(set_attr "prefix" "vex")
(set_attr "type" "other")])
+(define_insn "ldtilecfg"
+ [(unspec_volatile [(match_operand:XI 0 "memory_operand" "m")]
+ UNSPECV_LDTILECFG)]
+ "TARGET_AMX_TILE"
+ "ldtilecfg\t%0"
+ [(set_attr "type" "other")
+ (set_attr "prefix" "maybe_evex")
+ (set_attr "memory" "load")
+ (set_attr "mode" "XI")])
+
+(define_insn "sttilecfg"
+ [(set (match_operand:XI 0 "memory_operand" "=m")
+ (unspec_volatile:XI [(const_int 0)] UNSPECV_STTILECFG))]
+ "TARGET_AMX_TILE"
+ "sttilecfg\t%0"
+ [(set_attr "type" "other")
+ (set_attr "prefix" "maybe_evex")
+ (set_attr "memory" "store")
+ (set_attr "mode" "XI")])
+
(include "mmx.md")
(include "sse.md")
(include "sync.md")
projects / thirdparty / gcc.git / blobdiff