(clobber (match_scratch:<ssevecmode> 4))])]
"!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
{
- enum machine_mode mode = <MODE>mode;
- enum machine_mode vecmode = <ssevecmode>mode;
+ machine_mode mode = <MODE>mode;
+ machine_mode vecmode = <ssevecmode>mode;
REAL_VALUE_TYPE TWO31r;
rtx two31;
&& reload_completed && SSE_REG_P (operands[0])"
[(const_int 0)]
{
- const enum machine_mode vmode = <MODEF:ssevecmode>mode;
- const enum machine_mode mode = <MODEF:MODE>mode;
+ const machine_mode vmode = <MODEF:ssevecmode>mode;
+ const machine_mode mode = <MODEF:MODE>mode;
rtx t, op0 = simplify_gen_subreg (vmode, operands[0], mode, 0);
emit_move_insn (op0, CONST0_RTX (vmode));
"reload_completed && ix86_avoid_lea_for_addr (insn, operands)"
[(const_int 0)]
{
- enum machine_mode mode = <MODE>mode;
+ machine_mode mode = <MODE>mode;
rtx pat;
/* ix86_avoid_lea_for_addr re-recognizes insn and may
"reload_completed && ix86_lea_for_add_ok (insn, operands)"
[(const_int 0)]
{
- enum machine_mode mode = <MODE>mode;
+ machine_mode mode = <MODE>mode;
rtx pat;
if (<MODE_SIZE> < GET_MODE_SIZE (SImode))
"&& reload_completed"
[(const_int 0)]
{
- enum machine_mode mode = SImode;
+ machine_mode mode = SImode;
rtx pat;
operands[0] = gen_lowpart (mode, operands[0]);
"&& reload_completed"
[(const_int 0)]
{
- enum machine_mode mode = SImode;
+ machine_mode mode = SImode;
rtx pat;
operands[0] = gen_lowpart (mode, operands[0]);
"&& reload_completed"
[(const_int 0)]
{
- enum machine_mode mode = SImode;
+ machine_mode mode = SImode;
rtx pat;
operands[0] = gen_lowpart (mode, operands[0]);
"&& reload_completed"
[(const_int 0)]
{
- enum machine_mode mode = GET_MODE (operands[0]);
+ machine_mode mode = GET_MODE (operands[0]);
rtx pat;
if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (SImode))
HOST_WIDE_INT len = INTVAL (operands[3]);
HOST_WIDE_INT pos = INTVAL (operands[4]);
HOST_WIDE_INT mask;
- enum machine_mode mode, submode;
+ machine_mode mode, submode;
mode = GET_MODE (val);
if (MEM_P (val))
(match_operand:SWIM 2 "<general_szext_operand>")))]
""
{
- enum machine_mode mode = <MODE>mode;
+ machine_mode mode = <MODE>mode;
rtx (*insn) (rtx, rtx);
if (CONST_INT_P (operands[2]) && REG_P (operands[0]))
[(const_int 0)]
{
HOST_WIDE_INT ival = INTVAL (operands[2]);
- enum machine_mode mode;
+ machine_mode mode;
rtx (*insn) (rtx, rtx);
if (ival == (HOST_WIDE_INT) 0xffffffff)
"reload_completed && SSE_REG_P (operands[0])"
[(set (match_dup 0) (match_dup 3))]
{
- enum machine_mode mode = GET_MODE (operands[0]);
- enum machine_mode vmode = GET_MODE (operands[2]);
+ machine_mode mode = GET_MODE (operands[0]);
+ machine_mode vmode = GET_MODE (operands[2]);
rtx tmp;
operands[0] = simplify_gen_subreg (vmode, operands[0], mode, 0);
&& true_regnum (operands[0]) != true_regnum (operands[1])"
[(const_int 0)]
{
- enum machine_mode mode = GET_MODE (operands[0]);
+ machine_mode mode = GET_MODE (operands[0]);
rtx pat;
if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (SImode))
(clobber (reg:CC FLAGS_REG))])]
""
{
- enum machine_mode flags_mode;
+ machine_mode flags_mode;
if (<MODE>mode == SImode && !TARGET_CMOVE)
{
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
(clobber (reg:CC FLAGS_REG))])]
{
- enum machine_mode flags_mode
+ machine_mode flags_mode
= (TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI) ? CCCmode : CCZmode;
operands[3] = gen_lowpart (QImode, operands[2]);
[(set (match_dup 5) (match_dup 4))
(set (match_dup 0) (match_dup 1))]
{
- enum machine_mode op1mode = GET_MODE (operands[1]);
- enum machine_mode mode = op1mode == DImode ? DImode : SImode;
+ machine_mode op1mode = GET_MODE (operands[1]);
+ machine_mode mode = op1mode == DImode ? DImode : SImode;
int scale = 1 << INTVAL (operands[2]);
rtx index = gen_lowpart (word_mode, operands[1]);
rtx base = gen_lowpart (word_mode, operands[5]);