; Options for the IA-32 and AMD64 ports of the compiler.
-; Copyright (C) 2005-2013 Free Software Foundation, Inc.
+; Copyright (C) 2005-2020 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
Variable
HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT
+Variable
+HOST_WIDE_INT ix86_isa_flags2 = 0
+
; A mask of ix86_isa_flags that includes bit X if X was set or cleared
; on the command line.
Variable
HOST_WIDE_INT ix86_isa_flags_explicit
+Variable
+HOST_WIDE_INT ix86_isa_flags2_explicit
+
+; Additional target flags
+Variable
+int ix86_target_flags
+
TargetVariable
int recip_mask = RECIP_MASK_DEFAULT
TargetSave
unsigned char schedule
+;; True if processor has SSE prefetch instruction.
+TargetSave
+unsigned char prefetch_sse
+
;; branch cost
TargetSave
unsigned char branch_cost
;; which flags were passed by the user
TargetSave
-HOST_WIDE_INT x_ix86_isa_flags_explicit
-
-;; which flags were passed by the user
-Variable
-int ix86_target_flags_explicit
+HOST_WIDE_INT x_ix86_isa_flags2_explicit
;; which flags were passed by the user
TargetSave
-HOST_WIDE_INT x_ix86_target_flags_explicit
+HOST_WIDE_INT x_ix86_isa_flags_explicit
;; whether -mtune was not specified
TargetSave
TargetSave
int x_ix86_branch_cost
-;; -mdump-tune-features=
+;; -mdump-tune-features=
TargetSave
int x_ix86_dump_tunes
TargetSave
int x_ix86_force_align_arg_pointer
-;; -mforce-drap=
+;; -mforce-drap=
TargetSave
int x_ix86_force_drap
TargetSave
enum pmode x_ix86_pmode
-;; -mpreferred-stack-boundary=
+;; -mpreferred-stack-boundary=
TargetSave
int x_ix86_preferred_stack_boundary_arg
TargetSave
enum ix86_veclibabi x_ix86_veclibabi_type
+;; -mprefer-vector-width=
+TargetSave
+enum prefer_vector_width x_prefer_vector_width_type
+
;; x86 options
m128bit-long-double
Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
-sizeof(long double) is 16
+sizeof(long double) is 16.
m80387
Target Report Mask(80387) Save
-Use hardware fp
+Use hardware fp.
m96bit-long-double
Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
-sizeof(long double) is 12
+sizeof(long double) is 12.
mlong-double-80
-Target Report RejectNegative InverseMask(LONG_DOUBLE_64) Save
-Use 80-bit long double
+Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save
+Use 80-bit long double.
mlong-double-64
-Target Report RejectNegative Mask(LONG_DOUBLE_64) Save
-Use 64-bit long double
+Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save
+Use 64-bit long double.
+
+mlong-double-128
+Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save
+Use 128-bit long double.
maccumulate-outgoing-args
Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
-Reserve space for outgoing arguments in the function prologue
+Reserve space for outgoing arguments in the function prologue.
malign-double
Target Report Mask(ALIGN_DOUBLE) Save
-Align some doubles on dword boundary
+Align some doubles on dword boundary.
malign-functions=
Target RejectNegative Joined UInteger
-Function starts are aligned to this power of 2
+Function starts are aligned to this power of 2.
malign-jumps=
Target RejectNegative Joined UInteger
-Jump targets are aligned to this power of 2
+Jump targets are aligned to this power of 2.
malign-loops=
Target RejectNegative Joined UInteger
-Loop code aligned to this power of 2
+Loop code aligned to this power of 2.
malign-stringops
Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
-Align destination of the string operations
+Align destination of the string operations.
+
+malign-data=
+Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat)
+Use the given data alignment.
+
+Enum
+Name(ix86_align_data) Type(enum ix86_align_data)
+Known data alignment choices (for use with the -malign-data= option):
+
+EnumValue
+Enum(ix86_align_data) String(compat) Value(ix86_align_data_type_compat)
+
+EnumValue
+Enum(ix86_align_data) String(abi) Value(ix86_align_data_type_abi)
+
+EnumValue
+Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline)
march=
-Target RejectNegative Joined Var(ix86_arch_string)
-Generate code for given CPU
+Target RejectNegative Negative(march=) Joined Var(ix86_arch_string)
+Generate code for given CPU.
masm=
Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT)
-Use given assembler dialect
+Use given assembler dialect.
Enum
Name(asm_dialect) Type(enum asm_dialect)
-Known assembler dialects (for use with the -masm-dialect= option):
+Known assembler dialects (for use with the -masm= option):
EnumValue
Enum(asm_dialect) String(intel) Value(ASM_INTEL)
Enum(asm_dialect) String(att) Value(ASM_ATT)
mbranch-cost=
-Target RejectNegative Joined UInteger Var(ix86_branch_cost)
-Branches are this expensive (1-5, arbitrary units)
+Target RejectNegative Joined UInteger Var(ix86_branch_cost) IntegerRange(0, 5)
+Branches are this expensive (arbitrary units).
mlarge-data-threshold=
Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD)
-Data greater than given threshold will go into .ldata section in x86-64 medium model
+-mlarge-data-threshold=<number> Data greater than given threshold will go into .ldata section in x86-64 medium model.
mcmodel=
Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32)
-Use given x86-64 code model
+Use given x86-64 code model.
Enum
Name(cmodel) Type(enum cmodel)
maddress-mode=
Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI)
-Use given address mode
+Use given address mode.
Enum
Name(pmode) Type(enum pmode)
mfancy-math-387
Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
-Generate sin, cos, sqrt for FPU
+Generate sin, cos, sqrt for FPU.
mforce-drap
Target Report Var(ix86_force_drap)
-Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack
+Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack.
mfp-ret-in-387
Target Report Mask(FLOAT_RETURNS) Save
-Return values of functions in FPU registers
+Return values of functions in FPU registers.
mfpmath=
Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save
-Generate floating point mathematics using given instruction set
+Generate floating point mathematics using given instruction set.
Enum
Name(fpmath_unit) Type(enum fpmath_unit)
mhard-float
Target RejectNegative Mask(80387) Save
-Use hardware fp
+Use hardware fp.
mieee-fp
Target Report Mask(IEEE_FP) Save
-Use IEEE math for fp comparisons
+Use IEEE math for fp comparisons.
minline-all-stringops
Target Report Mask(INLINE_ALL_STRINGOPS) Save
-Inline all known string operations
+Inline all known string operations.
minline-stringops-dynamically
Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
-Inline memset/memcpy string operations, but perform inline version only for small blocks
+Inline memset/memcpy string operations, but perform inline version only for small blocks.
mintel-syntax
Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
-;; Deprecated
mms-bitfields
Target Report Mask(MS_BITFIELD_LAYOUT) Save
-Use native (MS) bitfield layout
+Use native (MS) bitfield layout.
mno-align-stringops
Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
momit-leaf-frame-pointer
Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
-Omit the frame pointer in leaf functions
+Omit the frame pointer in leaf functions.
mpc32
Target RejectNegative Report
-Set 80387 floating-point precision to 32-bit
+Set 80387 floating-point precision to 32-bit.
mpc64
Target RejectNegative Report
-Set 80387 floating-point precision to 64-bit
+Set 80387 floating-point precision to 64-bit.
mpc80
Target RejectNegative Report
-Set 80387 floating-point precision to 80-bit
+Set 80387 floating-point precision to 80-bit.
mpreferred-stack-boundary=
Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
-Attempt to keep stack aligned to this power of 2
+Attempt to keep stack aligned to this power of 2.
mincoming-stack-boundary=
Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg)
-Assume incoming stack aligned to this power of 2
+Assume incoming stack aligned to this power of 2.
mpush-args
Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
-Use push instructions to save outgoing arguments
+Use push instructions to save outgoing arguments.
mred-zone
Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
-Use red-zone in the x86-64 code
+Use red-zone in the x86-64 code.
mregparm=
Target RejectNegative Joined UInteger Var(ix86_regparm)
-Number of registers used to pass integer arguments
+Number of registers used to pass integer arguments.
mrtd
Target Report Mask(RTD) Save
-Alternate calling convention
+Alternate calling convention.
msoft-float
Target InverseMask(80387) Save
-Do not use hardware fp
+Do not use hardware fp.
msseregparm
Target RejectNegative Mask(SSEREGPARM) Save
-Use SSE register passing conventions for SF and DF mode
+Use SSE register passing conventions for SF and DF mode.
mstackrealign
-Target Report Var(ix86_force_align_arg_pointer) Init(-1)
-Realign stack in prologue
+Target Report Var(ix86_force_align_arg_pointer)
+Realign stack in prologue.
mstack-arg-probe
Target Report Mask(STACK_PROBE) Save
-Enable stack probing
+Enable stack probing.
mmemcpy-strategy=
Target RejectNegative Joined Var(ix86_tune_memcpy_strategy)
-Specify memcpy expansion strategy when expected size is known
+Specify memcpy expansion strategy when expected size is known.
mmemset-strategy=
Target RejectNegative Joined Var(ix86_tune_memset_strategy)
-Specify memset expansion strategy when expected size is known
+Specify memset expansion strategy when expected size is known.
mstringop-strategy=
Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop)
-Chose strategy to generate stringop using
+Chose strategy to generate stringop using.
Enum
Name(stringop_alg) Type(enum stringop_alg)
mtls-dialect=
Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU)
-Use given thread-local storage dialect
+Use given thread-local storage dialect.
Enum
Name(tls_dialect) Type(enum tls_dialect)
mtls-direct-seg-refs
Target Report Mask(TLS_DIRECT_SEG_REFS)
-Use direct references against %gs when accessing tls data
+Use direct references against %gs when accessing tls data.
mtune=
-Target RejectNegative Joined Var(ix86_tune_string)
-Schedule code for given CPU
+Target RejectNegative Negative(mtune=) Joined Var(ix86_tune_string)
+Schedule code for given CPU.
mtune-ctrl=
Target RejectNegative Joined Var(ix86_tune_ctrl_string)
-Fine grain control of tune features
+Fine grain control of tune features.
mno-default
-Target RejectNegative Var(ix86_tune_no_default) Init(0)
-Clear all tune features
+Target RejectNegative Var(ix86_tune_no_default)
+Clear all tune features.
mdump-tune-features
-Target RejectNegative Var(ix86_dump_tunes) Init(0)
+Target RejectNegative Var(ix86_dump_tunes)
+
+miamcu
+Target Report Mask(IAMCU)
+Generate code that conforms to Intel MCU psABI.
mabi=
Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI)
-Generate code that conforms to the given ABI
+Generate code that conforms to the given ABI.
Enum
Name(calling_abi) Type(enum calling_abi)
EnumValue
Enum(calling_abi) String(ms) Value(MS_ABI)
+mcall-ms2sysv-xlogues
+Target Report Mask(CALL_MS2SYSV_XLOGUES) Save
+Use libgcc stubs to save and restore registers clobbered by 64-bit Microsoft to System V ABI calls.
+
mveclibabi=
Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none)
-Vector library ABI to use
+Vector library ABI to use.
Enum
Name(ix86_veclibabi) Type(enum ix86_veclibabi)
mvect8-ret-in-mem
Target Report Mask(VECT8_RETURNS) Save
-Return 8-byte vectors in memory
+Return 8-byte vectors in memory.
mrecip
Target Report Mask(RECIP) Save
Generate vzeroupper instruction before a transfer of control flow out of
the function.
+mstv
+Target Report Mask(STV) Save
+Disable Scalar to Vector optimization pass transforming 64-bit integer
+computations into a vector ones.
+
mdispatch-scheduler
Target RejectNegative Var(flag_dispatch_scheduler)
-Do dispatch scheduling if processor is bdver1 or bdver2 or bdver3 or bdver4 and Haifa scheduling
-is selected.
+Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4
+or znver1 and Haifa scheduling is selected.
mprefer-avx128
-Target Report Mask(PREFER_AVX128) SAVE
+Target Alias(mprefer-vector-width=, 128, 256)
Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
+mprefer-vector-width=
+Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE)
+Use given register vector width instructions instead of maximum register width in the auto-vectorizer.
+
+Enum
+Name(prefer_vector_width) Type(enum prefer_vector_width)
+Known preferred register vector length (to use with the -mprefer-vector-width= option):
+
+EnumValue
+Enum(prefer_vector_width) String(none) Value(PVW_NONE)
+
+EnumValue
+Enum(prefer_vector_width) String(128) Value(PVW_AVX128)
+
+EnumValue
+Enum(prefer_vector_width) String(256) Value(PVW_AVX256)
+
+EnumValue
+Enum(prefer_vector_width) String(512) Value(PVW_AVX512)
+
;; ISA support
m32
Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
-Generate 32bit i386 code
+Generate 32bit i386 code.
m64
Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save
-Generate 64bit x86-64 code
+Generate 64bit x86-64 code.
mx32
-Target RejectNegative Negative(m32) Report Mask(ABI_X32) Var(ix86_isa_flags) Save
-Generate 32bit x86-64 code
+Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save
+Generate 32bit x86-64 code.
+
+m16
+Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
+Generate 16bit i386 code.
mmmx
Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
-Support MMX built-in functions
+Support MMX built-in functions.
m3dnow
Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
-Support 3DNow! built-in functions
+Support 3DNow! built-in functions.
m3dnowa
-Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
-Support Athlon 3Dnow! built-in functions
+Target Report Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
+Support Athlon 3Dnow! built-in functions.
msse
Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
-Support MMX and SSE built-in functions and code generation
+Support MMX and SSE built-in functions and code generation.
msse2
Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
-Support MMX, SSE and SSE2 built-in functions and code generation
+Support MMX, SSE and SSE2 built-in functions and code generation.
msse3
Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
+Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation.
mssse3
Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
+Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation.
msse4.1
Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
+Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation.
msse4.2
Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
msse4
Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
mno-sse4
Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save
-Do not support SSE4.1 and SSE4.2 built-in functions and code generation
+Do not support SSE4.1 and SSE4.2 built-in functions and code generation.
msse5
Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
mavx
Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation.
mavx2
Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation.
mavx512f
Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation.
mavx512pf
Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation.
mavx512er
Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation.
mavx512cd
Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation.
+
+mavx512dq
+Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation.
+
+mavx512bw
+Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation.
+
+mavx512vl
+Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation.
+
+mavx512ifma
+Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation.
+
+mavx512vbmi
+Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation.
+
+mavx5124fmaps
+Target Report Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation.
+
+mavx5124vnniw
+Target Report Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation.
+
+mavx512vpopcntdq
+Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation.
+
+mavx512vbmi2
+Target Report Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation.
+
+mavx512vnni
+Target Report Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save
+Support AVX512VNNI built-in functions and code generation.
+
+mavx512bitalg
+Target Report Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BITALG built-in functions and code generation.
+
+mavx512vp2intersect
+Target Report Mask(ISA2_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save
+Support AVX512VP2INTERSECT built-in functions and code generation.
mfma
Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation.
msse4a
Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
-Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
+Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation.
mfma4
Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
-Support FMA4 built-in functions and code generation
+Support FMA4 built-in functions and code generation.
mxop
Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
-Support XOP built-in functions and code generation
+Support XOP built-in functions and code generation.
mlwp
Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
-Support LWP built-in functions and code generation
+Support LWP built-in functions and code generation.
mabm
Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
Support code generation of popcnt instruction.
+mpconfig
+Target Report Mask(ISA2_PCONFIG) Var(ix86_isa_flags2) Save
+Support PCONFIG built-in functions and code generation.
+
+mwbnoinvd
+Target Report Mask(ISA2_WBNOINVD) Var(ix86_isa_flags2) Save
+Support WBNOINVD built-in functions and code generation.
+
+mptwrite
+Target Report Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save
+Support PTWRITE built-in functions and code generation.
+
+msgx
+Target Report Mask(ISA2_SGX) Var(ix86_isa_flags2) Save
+Support SGX built-in functions and code generation.
+
+mrdpid
+Target Report Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save
+Support RDPID built-in functions and code generation.
+
+mgfni
+Target Report Mask(ISA_GFNI) Var(ix86_isa_flags) Save
+Support GFNI built-in functions and code generation.
+
+mvaes
+Target Report Mask(ISA2_VAES) Var(ix86_isa_flags2) Save
+Support VAES built-in functions and code generation.
+
+mvpclmulqdq
+Target Report Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save
+Support VPCLMULQDQ built-in functions and code generation.
+
mbmi
Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
-Support BMI built-in functions and code generation
+Support BMI built-in functions and code generation.
mbmi2
Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save
-Support BMI2 built-in functions and code generation
+Support BMI2 built-in functions and code generation.
mlzcnt
Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
-Support LZCNT built-in function and code generation
+Support LZCNT built-in function and code generation.
mhle
-Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save
-Support Hardware Lock Elision prefixes
+Target Report Mask(ISA2_HLE) Var(ix86_isa_flags2) Save
+Support Hardware Lock Elision prefixes.
mrdseed
Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save
-Support RDSEED instruction
+Support RDSEED instruction.
mprfchw
Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
-Support PREFETCHW instruction
+Support PREFETCHW instruction.
madx
Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save
-Support flag-preserving add-carry instructions
+Support flag-preserving add-carry instructions.
+
+mclflushopt
+Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save
+Support CLFLUSHOPT instructions.
+
+mclwb
+Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save
+Support CLWB instruction.
+
+mpcommit
+Target WarnRemoved
mfxsr
Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save
-Support FXSAVE and FXRSTOR instructions
+Support FXSAVE and FXRSTOR instructions.
mxsave
Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save
-Support XSAVE and XRSTOR instructions
+Support XSAVE and XRSTOR instructions.
mxsaveopt
Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save
-Support XSAVEOPT instruction
+Support XSAVEOPT instruction.
+
+mxsavec
+Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save
+Support XSAVEC instructions.
+
+mxsaves
+Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save
+Support XSAVES and XRSTORS instructions.
mtbm
Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
-Support TBM built-in functions and code generation
+Support TBM built-in functions and code generation.
mcx16
-Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save
+Target Report Mask(ISA2_CX16) Var(ix86_isa_flags2) Save
Support code generation of cmpxchg16b instruction.
msahf
Support code generation of sahf instruction in 64bit x86-64 code.
mmovbe
-Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save
+Target Report Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save
Support code generation of movbe instruction.
mcrc32
maes
Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
-Support AES built-in functions and code generation
+Support AES built-in functions and code generation.
+
+msha
+Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save
+Support SHA1 and SHA256 built-in functions and code generation.
mpclmul
Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
-Support PCLMUL built-in functions and code generation
+Support PCLMUL built-in functions and code generation.
msse2avx
Target Report Var(ix86_sse2avx)
-Encode SSE instructions with VEX prefix
+Encode SSE instructions with VEX prefix.
mfsgsbase
Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
-Support FSGSBASE built-in functions and code generation
+Support FSGSBASE built-in functions and code generation.
mrdrnd
Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
-Support RDRND built-in functions and code generation
+Support RDRND built-in functions and code generation.
mf16c
Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
-Support F16C built-in functions and code generation
+Support F16C built-in functions and code generation.
+
+mprefetchwt1
+Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save
+Support PREFETCHWT1 built-in functions and code generation.
mfentry
-Target Report Var(flag_fentry) Init(-1)
+Target Report Var(flag_fentry)
Emit profiling counter call at function entry before prologue.
+mrecord-mcount
+Target Report Var(flag_record_mcount)
+Generate __mcount_loc section with all mcount or __fentry__ calls.
+
+mnop-mcount
+Target Report Var(flag_nop_mcount)
+Generate mcount/__fentry__ calls as nops. To activate they need to be
+patched in.
+
+mfentry-name=
+Target RejectNegative Joined Var(fentry_name)
+Set name of __fentry__ symbol called at function entry.
+
+mfentry-section=
+Target RejectNegative Joined Var(fentry_section)
+Set name of section to record mrecord-mcount calls.
+
+mskip-rax-setup
+Target Report Var(flag_skip_rax_setup)
+Skip setting up RAX register when passing variable arguments.
+
m8bit-idiv
Target Report Mask(USE_8BIT_IDIV) Save
-Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check
+Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check.
mavx256-split-unaligned-load
Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
-Split 32-byte AVX unaligned load
+Split 32-byte AVX unaligned load.
mavx256-split-unaligned-store
Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
-Split 32-byte AVX unaligned store
+Split 32-byte AVX unaligned store.
mrtm
Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save
-Support RTM built-in functions and code generation
+Support RTM built-in functions and code generation.
+
+mmpx
+Target WarnRemoved
+Removed in GCC 9. This switch has no effect.
+
+mmwaitx
+Target Report Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save
+Support MWAITX and MONITORX built-in functions and code generation.
+
+mclzero
+Target Report Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save
+Support CLZERO built-in functions and code generation.
+
+mpku
+Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save
+Support PKU built-in functions and code generation.
mstack-protector-guard=
Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS)
-Use given stack-protector guard
+Use given stack-protector guard.
Enum
Name(stack_protector_guard) Type(enum stack_protector_guard)
EnumValue
Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
+
+mstack-protector-guard-reg=
+Target RejectNegative Joined Var(ix86_stack_protector_guard_reg_str)
+Use the given base register for addressing the stack-protector guard.
+
+TargetVariable
+addr_space_t ix86_stack_protector_guard_reg = ADDR_SPACE_GENERIC
+
+mstack-protector-guard-offset=
+Target RejectNegative Joined Integer Var(ix86_stack_protector_guard_offset_str)
+Use the given offset for addressing the stack-protector guard.
+
+TargetVariable
+HOST_WIDE_INT ix86_stack_protector_guard_offset = 0
+
+mstack-protector-guard-symbol=
+Target RejectNegative Joined Integer Var(ix86_stack_protector_guard_symbol_str)
+Use the given symbol for addressing the stack-protector guard.
+
+mmitigate-rop
+Target WarnRemoved
+
+mgeneral-regs-only
+Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save
+Generate code which uses only the general registers.
+
+mshstk
+Target Report Mask(ISA_SHSTK) Var(ix86_isa_flags) Save
+Enable shadow stack built-in functions from Control-flow Enforcement
+Technology (CET).
+
+mcet-switch
+Target Report Undocumented Var(flag_cet_switch) Init(0)
+Turn on CET instrumentation for switch statements that use a jump table and
+an indirect jump.
+
+mmanual-endbr
+Target Report Var(flag_manual_endbr) Init(0)
+Insert ENDBR instruction at function entry only via cf_check attribute
+for CET instrumentation.
+
+mforce-indirect-call
+Target Report Var(flag_force_indirect_call) Init(0)
+Make all function calls indirect.
+
+mindirect-branch=
+Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep)
+Convert indirect call and jump to call and return thunks.
+
+mfunction-return=
+Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep)
+Convert function return to call and return thunk.
+
+Enum
+Name(indirect_branch) Type(enum indirect_branch)
+Known indirect branch choices (for use with the -mindirect-branch=/-mfunction-return= options):
+
+EnumValue
+Enum(indirect_branch) String(keep) Value(indirect_branch_keep)
+
+EnumValue
+Enum(indirect_branch) String(thunk) Value(indirect_branch_thunk)
+
+EnumValue
+Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline)
+
+EnumValue
+Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern)
+
+mindirect-branch-register
+Target Report Var(ix86_indirect_branch_register) Init(0)
+Force indirect call and jump via register.
+
+mmovdiri
+Target Report Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save
+Support MOVDIRI built-in functions and code generation.
+
+mmovdir64b
+Target Report Mask(ISA2_MOVDIR64B) Var(ix86_isa_flags2) Save
+Support MOVDIR64B built-in functions and code generation.
+
+mwaitpkg
+Target Report Mask(ISA2_WAITPKG) Var(ix86_isa_flags2) Save
+Support WAITPKG built-in functions and code generation.
+
+mcldemote
+Target Report Mask(ISA2_CLDEMOTE) Var(ix86_isa_flags2) Save
+Support CLDEMOTE built-in functions and code generation.
+
+minstrument-return=
+Target Report RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none)
+Instrument function exit in instrumented functions with __fentry__.
+
+Enum
+Name(instrument_return) Type(enum instrument_return)
+Known choices for return instrumentation with -minstrument-return=:
+
+EnumValue
+Enum(instrument_return) String(none) Value(instrument_return_none)
+
+EnumValue
+Enum(instrument_return) String(call) Value(instrument_return_call)
+
+EnumValue
+Enum(instrument_return) String(nop5) Value(instrument_return_nop5)
+
+mrecord-return
+Target Report Var(ix86_flag_record_return) Init(0)
+Generate a __return_loc section pointing to all return instrumentation code.
+
+mavx512bf16
+Target Report Mask(ISA2_AVX512BF16) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and
+AVX512BF16 built-in functions and code generation.
+
+menqcmd
+Target Report Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save
+Support ENQCMD built-in functions and code generation.
projects / thirdparty / gcc.git / blobdiff