Update copyright years.

[thirdparty/gcc.git] / gcc / config / i386 / ppro.md

diff --git a/gcc/config/i386/ppro.md b/gcc/config/i386/ppro.md
index 5e163d8296f73a3dd1e3d5d5f2b0f2c7e0f342d8..d5dde1f32871db9bc9b078c63c6c8a516463614f 100644 (file)
--- a/gcc/config/i386/ppro.md
+++ b/gcc/config/i386/ppro.md
@@ -1,5 +1,5 @@
 ;; Scheduling for the Intel P6 family of processors
-;; Copyright (C) 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
+;; Copyright (C) 2004-2020 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
@@ -509,14 +509,14 @@
                         (and (eq_attr "cpu" "pentiumpro")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "mode" "SF")
-                                       (eq_attr "type" "sseadd"))))
+                                       (eq_attr "type" "sseadd,sseadd1"))))
                         "decodern,p1")
 
 (define_insn_reservation "ppro_sse_add_SF_load" 3
                         (and (eq_attr "cpu" "pentiumpro")
                              (and (eq_attr "memory" "load")
                                   (and (eq_attr "mode" "SF")
-                                       (eq_attr "type" "sseadd"))))
+                                       (eq_attr "type" "sseadd,sseadd1"))))
                         "decoder0,p2+p1")
 
 (define_insn_reservation "ppro_sse_cmp_SF" 3
@@ -619,14 +619,14 @@
                         (and (eq_attr "cpu" "pentiumpro")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "mode" "V4SF")
-                                       (eq_attr "type" "sseadd"))))
+                                       (eq_attr "type" "sseadd,sseadd1"))))
                         "decoder0,p1*2")
 
 (define_insn_reservation "ppro_sse_add_V4SF_load" 3
                         (and (eq_attr "cpu" "pentiumpro")
                              (and (eq_attr "memory" "load")
                                   (and (eq_attr "mode" "V4SF")
-                                       (eq_attr "type" "sseadd"))))
+                                       (eq_attr "type" "sseadd,sseadd1"))))
                         "decoder0,(p2+p1)*2")
 
 (define_insn_reservation "ppro_sse_cmp_V4SF" 3
@@ -690,14 +690,14 @@
                         (and (eq_attr "cpu" "pentiumpro")
                              (and (eq_attr "memory" "none")
                                   (and (eq_attr "mode" "V4SF")
-                                       (eq_attr "type" "sselog,sselog1"))))
+                                       (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1"))))
                         "decodern,p1")
 
 (define_insn_reservation "ppro_sse_log_V4SF_load" 2
                         (and (eq_attr "cpu" "pentiumpro")
                              (and (eq_attr "memory" "load")
                                   (and (eq_attr "mode" "V4SF")
-                                       (eq_attr "type" "sselog,sselog1"))))
+                                       (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1"))))
                         "decoder0,(p2+p1)")
 
 (define_insn_reservation "ppro_sse_mov_V4SF" 1
@@ -731,7 +731,7 @@
 (define_insn_reservation "ppro_insn" 1
                         (and (eq_attr "cpu" "pentiumpro")
                              (and (eq_attr "memory" "none,unknown")
-                                  (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp")))
+                                  (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseishft1,sseimul,mmx,mmxadd,mmxcmp")))
                         "decodern,(p0|p1)")
 
 ;; read-modify and register-memory instructions have 2 or three uops,
@@ -739,13 +739,13 @@
 (define_insn_reservation "ppro_insn_load" 3
                         (and (eq_attr "cpu" "pentiumpro")
                              (and (eq_attr "memory" "load")
-                                  (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp")))
+                                  (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseishft1,sseimul,mmx,mmxadd,mmxcmp")))
                         "decoder0,p2+(p0|p1)")
 
 (define_insn_reservation "ppro_insn_store" 1
                         (and (eq_attr "cpu" "pentiumpro")
                              (and (eq_attr "memory" "store")
-                                  (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp")))
+                                  (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseishft1,sseimul,mmx,mmxadd,mmxcmp")))
                         "decoder0,(p0|p1),p4+p3")
 
 ;; read-modify-store instructions produce 4 uops so they have to be
@@ -753,6 +753,6 @@
 (define_insn_reservation "ppro_insn_both" 4
                         (and (eq_attr "cpu" "pentiumpro")
                              (and (eq_attr "memory" "both")
-                                  (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp")))
+                                  (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseishft1,sseimul,mmx,mmxadd,mmxcmp")))
                         "decoder0,p2+(p0|p1),p4+p3")