/* Definitions of target machine for GNU compiler, for Intel 80960
- Copyright (C) 1992, 1993, 1995, 1996, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1992, 1993, 1995, 1996, 1998, 1999, 2000, 2001, 2002
+ Free Software Foundation, Inc.
Contributed by Steven McGeady, Intel Corp.
Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
-This file is part of GNU CC.
+This file is part of GCC.
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
+along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* Note that some other tm.h files may include this one and then override
many of the definitions that relate to assembler syntax. */
-/* Names to predefine in the preprocessor for this target machine. */
-#define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu(i960) -Amachine(i960)"
+/* Target CPU builtins. */
+#define TARGET_CPU_CPP_BUILTINS() \
+ do \
+ { \
+ builtin_define_std ("i960"); \
+ builtin_define_std ("I960"); \
+ builtin_define_std ("i80960"); \
+ builtin_define_std ("I80960"); \
+ builtin_assert ("cpu=i960"); \
+ builtin_assert ("machine=i960"); \
+ } \
+ while (0)
+
+#define MULTILIB_DEFAULTS { "mnumerics" }
-/* Name to predefine in the preprocessor for processor variations. */
-#define CPP_SPEC "%{mic*:-D__i960\
+/* Name to predefine in the preprocessor for processor variations.
+ -mic* options make characters signed by default. */
+#define CPP_SPEC "%{mic*:-D__i960 -fsigned-char\
%{mka:-D__i960KA}%{mkb:-D__i960KB}\
%{mja:-D__i960JA}%{mjd:-D__i960JD}%{mjf:-D__i960JF}\
%{mrp:-D__i960RP}\
%{mmc:-D__i960MC}\
%{mca:-D__i960CA}%{mcc:-D__i960CC}\
%{mcf:-D__i960CF}}\
+ %{msoft-float:-D_SOFT_FLOAT}\
%{mka:-D__i960KA__ -D__i960_KA__}\
%{mkb:-D__i960KB__ -D__i960_KB__}\
%{msa:-D__i960SA__ -D__i960_SA__}\
%{mcc:-D__i960CC__ -D__i960_CC__}\
%{mcf:-D__i960CF__ -D__i960_CF__}\
%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
- %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}"
-
-/* -mic* options make characters signed by default. */
-/* Use #if rather than ?: because MIPS C compiler rejects ?: in
- initializers. */
-#if DEFAULT_SIGNED_CHAR
-#define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
-#else
-#define SIGNED_CHAR_SPEC "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}"
-#endif
+ %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}\
+ %{mlong-double-64:-D__LONG_DOUBLE_64__}"
/* Specs for the compiler, to handle processor variations.
If the user gives an explicit -gstabs or -gcoff option, then do not
- try to add an implicit one, as this will fail. */
+ try to add an implicit one, as this will fail.
+ -mic* options make characters signed by default. */
#define CC1_SPEC \
- "%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-mka}}}}}}}}}}}}\
+ "%{mic*:-fsigned-char}\
+%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-mka}}}}}}}}}}}}\
%{!gs*:%{!gc*:%{mbout:%{g*:-gstabs}}\
%{mcoff:%{g*:-gcoff}}\
%{!mbout:%{!mcoff:%{g*:-gstabs}}}}}"
#define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
%{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"
-/* Show we can debug even without a frame pointer. */
-#define CAN_DEBUG_WITHOUT_FP
+/* Defining the macro shows we can debug even without a frame pointer.
+ Actually, we can debug without FP. But defining the macro results in
+ that -O means FP elimination. Addressing through sp requires
+ negative offset and more one word addressing in the most cases
+ (offsets except for 0-4095 require one more word). Therefore we've
+ not defined the macro. */
+/*#define CAN_DEBUG_WITHOUT_FP*/
/* Do leaf procedure and tail call optimizations for -O2 and higher. */
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
#define TARGET_VERSION fprintf (stderr," (intel 80960)");
/* Generate DBX debugging information. */
-#define DBX_DEBUGGING_INFO
+#define DBX_DEBUGGING_INFO 1
/* Generate SDB style debugging information. */
-#define SDB_DEBUGGING_INFO
+#define SDB_DEBUGGING_INFO 1
#define EXTENDED_SDB_BASIC_TYPES
/* Generate DBX_DEBUGGING_INFO by default. */
fprintf (asm_out_file, "\t.type\t0x%x;", A)
/* Handle pragmas for compatibility with Intel's compilers. */
-#define HANDLE_PRAGMA(FILE, NODE) process_pragma (FILE, NODE)
+
+extern int i960_maxbitalignment;
+extern int i960_last_maxbitalignment;
+
+#define REGISTER_TARGET_PRAGMAS() do { \
+ c_register_pragma (0, "align", i960_pr_align); \
+ c_register_pragma (0, "noalign", i960_pr_noalign); \
+} while (0)
/* Run-time compilation parameters selecting different hardware subsets. */
/* The following three are mainly used to provide a little sanity checking
against the -mARCH flags given. The Jx series, for the purposes of
- gcc, is a Kx with a data cache. */
+ gcc, is a Kx with a data cache. */
/* Nonzero if we should generate code for the KA and similar processors.
No FPU, no microcode instructions. */
#define TARGET_FLAG_OLD_ALIGN 0x8000
#define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN)
+/* Nonzero if long doubles are to be 64 bits. Useful for soft-float targets
+ if 80 bit long double support is missing. */
+#define TARGET_FLAG_LONG_DOUBLE_64 0x10000
+#define TARGET_LONG_DOUBLE_64 (target_flags & TARGET_FLAG_LONG_DOUBLE_64)
+
extern int target_flags;
/* Macro to define tables used to set the flags.
am not sure which are real and which aren't. */
#define TARGET_SWITCHES \
- { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
- {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
- TARGET_FLAG_COMPLEX_ADDR)},\
-/* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
- TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
- {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
- {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
- TARGET_FLAG_COMPLEX_ADDR)},\
-/* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
- TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
- {"ja", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
- {"jd", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
- {"jf", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
- TARGET_FLAG_COMPLEX_ADDR)},\
- {"rp", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
- {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
- TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\
- {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
- TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
-/* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\
- TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\
- {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
+ { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
+ N_("Generate SA code")}, \
+ {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
+ TARGET_FLAG_COMPLEX_ADDR), \
+ N_("Generate SB code")}, \
+/* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
+ TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
+ N_("Generate SC code")}, */ \
+ {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
+ N_("Generate KA code")}, \
+ {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
+ TARGET_FLAG_COMPLEX_ADDR), \
+ N_("Generate KB code")}, \
+/* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
+ TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
+ N_("Generate KC code")}, */ \
+ {"ja", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
+ N_("Generate JA code")}, \
+ {"jd", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
+ N_("Generate JD code")}, \
+ {"jf", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
+ TARGET_FLAG_COMPLEX_ADDR), \
+ N_("Generate JF code")}, \
+ {"rp", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
+ N_("generate RP code")}, \
+ {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
+ TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
+ N_("Generate MC code")}, \
+ {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \
+ TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
+ N_("Generate CA code")}, \
+/* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES| \
+ TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN),\
+ N_("Generate CB code")}, \
+ {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
- TARGET_FLAG_CODE_ALIGN)}, */ \
- {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
- TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
- {"numerics", (TARGET_FLAG_NUMERICS)}, \
- {"soft-float", -(TARGET_FLAG_NUMERICS)}, \
- {"leaf-procedures", TARGET_FLAG_LEAFPROC}, \
- {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)}, \
- {"tail-call",TARGET_FLAG_TAILCALL}, \
- {"no-tail-call",-(TARGET_FLAG_TAILCALL)}, \
- {"complex-addr",TARGET_FLAG_COMPLEX_ADDR}, \
- {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)}, \
- {"code-align",TARGET_FLAG_CODE_ALIGN}, \
- {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)}, \
- {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)}, \
- {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)}, \
- {"ic-compat", TARGET_FLAG_IC_COMPAT2_0}, \
- {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0}, \
- {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0}, \
- {"asm-compat",TARGET_FLAG_ASM_COMPAT}, \
- {"intel-asm",TARGET_FLAG_ASM_COMPAT}, \
- {"strict-align", TARGET_FLAG_STRICT_ALIGN}, \
- {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)}, \
- {"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)}, \
- {"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)}, \
- {"link-relax", 0}, \
- {"no-link-relax", 0}, \
+ TARGET_FLAG_CODE_ALIGN), \
+ N_("Generate CC code")}, */ \
+ {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \
+ TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
+ N_("Generate CF code")}, \
+ {"numerics", (TARGET_FLAG_NUMERICS), \
+ N_("Use hardware floating point instructions")}, \
+ {"soft-float", -(TARGET_FLAG_NUMERICS), \
+ N_("Use software floating point")}, \
+ {"leaf-procedures", TARGET_FLAG_LEAFPROC, \
+ N_("Use alternate leaf function entries")}, \
+ {"no-leaf-procedures", -(TARGET_FLAG_LEAFPROC), \
+ N_("Do not use alternate leaf function entries")}, \
+ {"tail-call", TARGET_FLAG_TAILCALL, \
+ N_("Perform tail call optimization")}, \
+ {"no-tail-call", -(TARGET_FLAG_TAILCALL), \
+ N_("Do not perform tail call optimization")}, \
+ {"complex-addr", TARGET_FLAG_COMPLEX_ADDR, \
+ N_("Use complex addressing modes")}, \
+ {"no-complex-addr", -(TARGET_FLAG_COMPLEX_ADDR), \
+ N_("Do not use complex addressing modes")}, \
+ {"code-align", TARGET_FLAG_CODE_ALIGN, \
+ N_("Align code to 8 byte boundary")}, \
+ {"no-code-align", -(TARGET_FLAG_CODE_ALIGN), \
+ N_("Do not align code to 8 byte boundary")}, \
+/* {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE), \
+ N_("Force use of prototypes")}, \
+ {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE), \
+ N_("Do not force use of prototypes")}, */ \
+ {"ic-compat", TARGET_FLAG_IC_COMPAT2_0, \
+ N_("Enable compatibility with iC960 v2.0")}, \
+ {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0, \
+ N_("Enable compatibility with iC960 v2.0")}, \
+ {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0, \
+ N_("Enable compatibility with iC960 v3.0")}, \
+ {"asm-compat", TARGET_FLAG_ASM_COMPAT, \
+ N_("Enable compatibility with ic960 assembler")}, \
+ {"intel-asm", TARGET_FLAG_ASM_COMPAT, \
+ N_("Enable compatibility with ic960 assembler")}, \
+ {"strict-align", TARGET_FLAG_STRICT_ALIGN, \
+ N_("Do not permit unaligned accesses")}, \
+ {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN), \
+ N_("Permit unaligned accesses")}, \
+ {"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \
+ N_("Layout types like Intel's v1.3 gcc")}, \
+ {"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \
+ N_("Do not layout types like Intel's v1.3 gcc")}, \
+ {"long-double-64", TARGET_FLAG_LONG_DOUBLE_64, \
+ N_("Use 64 bit long doubles")}, \
+ {"link-relax", 0, \
+ N_("Enable linker relaxation")}, \
+ {"no-link-relax", 0, \
+ N_("Do not enable linker relaxation")}, \
SUBTARGET_SWITCHES \
- { "", TARGET_DEFAULT}}
+ { "", TARGET_DEFAULT, \
+ NULL}}
/* This are meant to be redefined in the host dependent files */
#define SUBTARGET_SWITCHES
/* Override conflicting target switch options.
Doesn't actually detect if more than one -mARCH option is given, but
does handle the case of two blatantly conflicting -mARCH options. */
-#define OVERRIDE_OPTIONS \
-{ \
- if (TARGET_K_SERIES && TARGET_C_SERIES) \
- { \
- warning ("conflicting architectures defined - using C series", 0); \
- target_flags &= ~TARGET_FLAG_K_SERIES; \
- } \
- if (TARGET_K_SERIES && TARGET_MC) \
- { \
- warning ("conflicting architectures defined - using K series", 0); \
- target_flags &= ~TARGET_FLAG_MC; \
- } \
- if (TARGET_C_SERIES && TARGET_MC) \
- { \
- warning ("conflicting architectures defined - using C series", 0);\
- target_flags &= ~TARGET_FLAG_MC; \
- } \
- if (TARGET_IC_COMPAT3_0) \
- { \
- flag_short_enums = 1; \
- flag_signed_char = 1; \
- target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
- if (TARGET_IC_COMPAT2_0) \
- { \
- warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \
- target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \
- } \
- } \
- if (TARGET_IC_COMPAT2_0) \
- { \
- flag_signed_char = 1; \
- target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
- } \
- i960_initialize (); \
-}
+#define OVERRIDE_OPTIONS i960_initialize ()
/* Don't enable anything by default. The user is expected to supply a -mARCH
option. If none is given, then -mka is added by CC1_SPEC. */
\f
/* Target machine storage layout. */
-/* Define for cross-compilation from a host with a different float format
- or endianness, as well as to support 80 bit long doubles on the i960. */
-#define REAL_ARITHMETIC
-
/* Define this if most significant bit is lowest numbered
in instructions that operate on numbered bit-fields. */
#define BITS_BIG_ENDIAN 0
numbered. */
#define WORDS_BIG_ENDIAN 0
-/* Number of bits in an addressable storage unit. */
-#define BITS_PER_UNIT 8
-
/* Bitfields cannot cross word boundaries. */
#define BITFIELD_NBYTES_LIMITED 1
-/* Width in bits of a "word", which is the contents of a machine register.
- Note that this is not necessarily the width of data type `int';
- if using 16-bit ints on a 68000, this would still be 32.
- But on a machine with 16-bit registers, this would be 16. */
-#define BITS_PER_WORD 32
-
/* Width of a word, in units (bytes). */
#define UNITS_PER_WORD 4
-/* Width in bits of a pointer. See also the macro `Pmode' defined below. */
-#define POINTER_SIZE 32
+/* Width in bits of a long double. */
+#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 128)
+#define MAX_LONG_DOUBLE_TYPE_SIZE 128
-/* Width in bits of a long double. Identical to double for now. */
-#define LONG_DOUBLE_TYPE_SIZE 64
+/* Define this to set long double type size to use in libgcc2.c, which can
+ not depend on target_flags. */
+#if defined(__LONG_DOUBLE_64__)
+#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
+#else
+#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
+#endif
/* Allocation boundary (in *bits*) for storing pointers in memory. */
#define POINTER_BOUNDARY 32
library functions. */
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
(TREE_CODE (EXP) == STRING_CST \
- && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \
+ && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (int)(ALIGN) \
? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \
- : (ALIGN))
-
-/* Make XFmode floating point quantities be 128 bit aligned. */
-#define DATA_ALIGNMENT(TYPE, ALIGN) \
- (TREE_CODE (TYPE) == ARRAY_TYPE \
- && TYPE_MODE (TREE_TYPE (TYPE)) == XFmode \
- && (ALIGN) < 128 ? 128 : (ALIGN))
+ : (int)(ALIGN))
/* Macros to determine size of aggregates (structures and unions
in C). Normally, these may be defined to simply return the maximum
the i960), the total size of a structure is based on a non-trivial
rounding method. */
-#define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
- ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
- ? 128 /* Put 80 bit floating point elements on 128 bit boundaries. */ \
- : ((!TARGET_OLD_ALIGN && !TYPE_PACKED (TYPE) \
- && TREE_CODE (TYPE) == RECORD_TYPE) \
- ? i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE_SIZE (TYPE)) \
- : MAX ((COMPUTED), (SPECIFIED))))
-
-#define ROUND_TYPE_SIZE(TYPE, COMPUTED, SPECIFIED) \
- ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
- ? build_int_2 (128, 0) : round_up (COMPUTED, SPECIFIED))
+#define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
+ i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE)
\f
/* Standard register usage. */
g0..g3 are used for return values,
g0..g7 may always be used for parameters,
g8..g11 may be used for parameters, but are preserved if they aren't,
- g12 is always preserved, but otherwise unused,
+ g12 is the static chain if needed, otherwise is preserved
g13 is the struct return ptr if used, or temp, but may be trashed,
g14 is the leaf return ptr or the arg block ptr otherwise zero,
must be reset to zero before returning if it was used,
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
On 80960, the cpu registers can hold any mode but the float registers
- can only hold SFmode, DFmode, or XFmode. */
-extern int hard_regno_mode_ok ();
+ can only hold SFmode, DFmode, or TFmode. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok ((REGNO), (MODE))
/* Value is 1 if it is a good idea to tie two pseudo registers
/* ??? It isn't clear to me why this is here. Perhaps because of a bug (since
fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have
caused this to fail. */
-#define FRAME_POINTER_REQUIRED (! leaf_function_p ())
+/* ??? Must check current_function_has_nonlocal_goto, otherwise frame pointer
+ elimination messes up nonlocal goto sequences. I think this works for other
+ targets because they use indirect jumps for the return which disables fp
+ elimination. */
+#define FRAME_POINTER_REQUIRED \
+ (! leaf_function_p () || current_function_has_nonlocal_goto)
+
+/* Definitions for register eliminations.
+
+ This is an array of structures. Each structure initializes one pair
+ of eliminable registers. The "from" register number is given first,
+ followed by "to". Eliminations of the same "from" register are listed
+ in order of preference.. */
-/* C statement to store the difference between the frame pointer
- and the stack pointer values immediately after the function prologue.
+#define ELIMINABLE_REGS {{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
+
+/* Given FROM and TO register numbers, say whether this elimination is allowed.
+ Frame pointer elimination is automatically handled. */
+#define CAN_ELIMINATE(FROM, TO) 1
+
+/* Define the offset between two registers, one to be eliminated, and
+ the other its replacement, at the start of a routine.
Since the stack grows upward on the i960, this must be a negative number.
This includes the 64 byte hardware register save area and the size of
the frame. */
-#define INITIAL_FRAME_POINTER_OFFSET(VAR) \
- do { (VAR) = - (64 + compute_frame_size (get_frame_size ())); } while (0)
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
+ do { (OFFSET) = - (64 + compute_frame_size (get_frame_size ())); } while (0)
/* Base register for access to arguments of the function. */
#define ARG_POINTER_REGNUM 14
/* Register in which static-chain is passed to a function.
- On i960, we use r3. */
-#define STATIC_CHAIN_REGNUM 19
+ On i960, we use g12. We can't use any local register, because we need
+ a register that can be set before a call or before a jump. */
+#define STATIC_CHAIN_REGNUM 12
/* Functions which return large structures get the address
to place the wanted value at in g13. */
#define OUTGOING_REG_PARM_STACK_SPACE
/* Keep the stack pointer constant throughout the function. */
-#define ACCUMULATE_OUTGOING_ARGS
+#define ACCUMULATE_OUTGOING_ARGS 1
/* Value is 1 if returning from a function call automatically
pops the arguments described by the number-of-args field in the call.
/* Define how to find the value returned by a library function
assuming the value has mode MODE. */
-#define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0)
+#define LIBCALL_VALUE(MODE) gen_rtx_REG ((MODE), 0)
/* 1 if N is a possible register number for a function value
as seen by the caller.
#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL)
+
+/* Implement `va_start' for varargs and stdarg. */
+#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
+ i960_va_start (valist, nextarg)
+
+/* Implement `va_arg'. */
+#define EXPAND_BUILTIN_VA_ARG(valist, type) \
+ i960_va_arg (valist, type)
\f
/* Define a data type for recording info about an argument list
during the scan of that argument list. This data type should
On 80960, the offset always starts at 0; the first parm reg is g0. */
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0)
/* Update the data in CUM to advance over an argument
NAMED is nonzero if this argument is a named parameter
(otherwise it is an extra parameter matching an ellipsis). */
-extern struct rtx_def *i960_function_arg ();
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
i960_function_arg(&CUM, MODE, TYPE, NAMED)
otherwise, FUNC is 0. */
#define FUNCTION_VALUE(TYPE, FUNC) \
- gen_rtx (REG, TYPE_MODE (TYPE), 0)
+ gen_rtx_REG (TYPE_MODE (TYPE), 0)
/* Force aggregates and objects larger than 16 bytes to be returned in memory,
since we only have 4 registers available for return values. */
#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
i960_function_name_declare (FILE, NAME, DECL)
-/* This macro generates the assembly code for function entry.
- FILE is a stdio stream to output the code to.
- SIZE is an int: how many units of temporary storage to allocate.
- Refer to the array `regs_ever_live' to determine which registers
- to save; `regs_ever_live[I]' is nonzero if register number I
- is ever used in the function. This macro is responsible for
- knowing which registers should not be saved even if used. */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE))
-
/* Output assembler code to FILE to increment profiler label # LABELNO
for profiling a function entry. */
No definition is equivalent to always zero. */
#define EXIT_IGNORE_STACK 1
-
-/* This macro generates the assembly code for function exit,
- on machines that need it. If FUNCTION_EPILOGUE is not defined
- then individual return instructions are generated for each
- return statement. Args are same as for FUNCTION_PROLOGUE.
-
- The function epilogue should not depend on the current stack pointer!
- It should use the frame pointer only. This is mandatory because
- of alloca; we also take advantage of it to omit stack adjustments
- before returning. */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE)
\f
/* Addressing modes, and classification of registers for them. */
-/* #define HAVE_POST_INCREMENT */
-/* #define HAVE_POST_DECREMENT */
-
-/* #define HAVE_PRE_DECREMENT */
-/* #define HAVE_PRE_INCREMENT */
-
/* Macros to check register numbers against specific register classes. */
/* These assume that REGNO is a hard or pseudo reg number.
In each case, scale can be 1, 2, 4, 8, or 16. */
-/* Returns 1 if the scale factor of an index term is valid. */
+/* Returns 1 if the scale factor of an index term is valid. */
#define SCALE_TERM_P(X) \
(GET_CODE (X) == CONST_INT \
&& (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \
/* On 80960, convert non-canonical addresses to canonical form. */
-extern struct rtx_def *legitimize_address ();
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
{ rtx orig_x = (X); \
(X) = legitimize_address (X, OLDX, MODE); \
/* Define as C expression which evaluates to nonzero if the tablejump
instruction expects the table to contain offsets from the address of the
table.
- Do not define this if the table should contain absolute addresses. */
+ Do not define this if the table should contain absolute addresses. */
/* #define CASE_VECTOR_PC_RELATIVE 1 */
-/* Specify the tree operation to be used to convert reals to integers. */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case. */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
/* Define this as 1 if `char' should by default be signed; else as 0. */
#define DEFAULT_SIGNED_CHAR 0
-/* Allow and ignore #sccs directives. */
-#define SCCS_DIRECTIVE
-
/* Max number of bytes we can move from memory to memory
in one reasonably fast instruction. */
#define MOVE_MAX 16
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* Nonzero if access to memory by bytes is no faster than for words.
- Defining this results in worse code on the i960. */
-
-#define SLOW_BYTE_ACCESS 0
+ Value changed to 1 after reports of poor bit-field code with g++.
+ Indications are that code is usually as good, sometimes better. */
-/* We assume that the store-condition-codes instructions store 0 for false
- and some other value for true. This is the value stored for true. */
-
-#define STORE_FLAG_VALUE 1
+#define SLOW_BYTE_ACCESS 1
/* Define this to be nonzero if shift instructions ignore all but the low-order
- few bits. */
+ few bits. */
#define SHIFT_COUNT_TRUNCATED 0
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
extern struct rtx_def *i960_compare_op0, *i960_compare_op1;
-/* Define the function that build the compare insn for scc and bcc. */
-
-extern struct rtx_def *gen_compare_reg ();
-
-/* Add any extra modes needed to represent the condition code.
-
- Also, signed and unsigned comparisons are distinguished, as
- are operations which are compatible with chkbit insns. */
-#define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode
-
-/* Define the names for the modes specified above. */
-#define EXTRA_CC_NAMES "CC_UNS", "CC_CHK"
-
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
return the mode to be used for the comparison. For floating-point, CCFPmode
should be used. CC_NOOVmode should be used when the first operand is a
#ifndef WIND_RIVER
#define TARGET_MEM_FUNCTIONS 1
#endif
-
-/* Compute the cost of computing a constant rtl expression RTX
- whose rtx-code is CODE. The body of this macro is a portion
- of a switch statement. If the code is computed here,
- return it with a return statement. Otherwise, break from the switch. */
-
-/* Constants that can be (non-ldconst) insn operands are cost 0. Constants
- that can be non-ldconst operands in rare cases are cost 1. Other constants
- have higher costs. */
-
-#define CONST_COSTS(RTX, CODE, OUTER_CODE) \
- case CONST_INT: \
- if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \
- || power2_operand (RTX, VOIDmode)) \
- return 0; \
- else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \
- return 1; \
- case CONST: \
- case LABEL_REF: \
- case SYMBOL_REF: \
- return (TARGET_FLAG_C_SERIES ? 6 : 8); \
- case CONST_DOUBLE: \
- if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \
- || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\
- return 1; \
- return 12;
-
-/* The i960 offers addressing modes which are "as cheap as a register".
- See i960.c (or gcc.texinfo) for details. */
-
-#define ADDRESS_COST(RTX) \
- (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX))
\f
/* Control the assembler format that we output. */
-/* Output at beginning of assembler file. */
-
-#define ASM_FILE_START(file)
-
/* Output to assembler file text saying following lines
may contain character constants, extra white space, comments, etc. */
/* Output before read-only data. */
-#define TEXT_SECTION_ASM_OP ".text"
+#define TEXT_SECTION_ASM_OP "\t.text"
/* Output before writable data. */
-#define DATA_SECTION_ASM_OP ".data"
+#define DATA_SECTION_ASM_OP "\t.data"
/* How to refer to registers in assembler output.
This sequence is indexed by compiler's hard-register-number (see above). */
#define DBX_CONTIN_LENGTH 1500
/* This is how to output a note to DBX telling it the line number
- to which the following sequence of instructions corresponds. */
+ to which the following sequence of instructions corresponds. */
-#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
+#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE, COUNTER) \
{ if (write_symbols == SDB_DEBUG) { \
fprintf ((FILE), "\t.ln %d\n", \
(sdb_begin_function_line \
fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \
} }
-/* This is how to output the definition of a user-level label named NAME,
- such as the label on a static function or variable NAME. */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME) \
- do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
- defined for reference from other files. */
+/* Globalizing directive for a label. */
+#define GLOBAL_ASM_OP "\t.globl "
-#define ASM_GLOBALIZE_LABEL(FILE,NAME) \
-{ fputs ("\t.globl ", FILE); \
- assemble_name (FILE, NAME); \
- fputs ("\n", FILE); }
-
-/* The prefix to add to user-visible assembler symbols. */
+/* The prefix to add to user-visible assembler symbols. */
#define USER_LABEL_PREFIX "_"
-/* This is how to output an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class. */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
/* This is how to store into the string LABEL
the symbol_ref name of an internal numbered label where
PREFIX is the class of label and NUM is the number within the class.
This is suitable for output with `assemble_name'. */
#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
- sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `long double'
- constant. */
-
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) i960_output_long_double(FILE, VALUE)
-
-/* This is how to output an assembler line defining a `double' constant. */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE)
-
-/* This is how to output an assembler line defining a `float' constant. */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE)
-
-/* This is how to output an assembler line defining an `int' constant. */
-
-#define ASM_OUTPUT_INT(FILE,VALUE) \
-( fprintf (FILE, "\t.word "), \
- output_addr_const (FILE, (VALUE)), \
- fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants. */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE) \
-( fprintf (FILE, "\t.short "), \
- output_addr_const (FILE, (VALUE)), \
- fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE) \
-( fprintf (FILE, "\t.byte "), \
- output_addr_const (FILE, (VALUE)), \
- fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte. */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE) \
- fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
+ sprintf (LABEL, "*%s%lu", PREFIX, (unsigned long)(NUM))
#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO])
fprintf (FILE, "\t.align %d\n", (LOG))
#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- fprintf (FILE, "\t.space %d\n", (SIZE))
+ fprintf (FILE, "\t.space %d\n", (int)(SIZE))
/* This says how to output an assembler line
to define a global common symbol. */
assemble_name ((FILE), (NAME)), \
fputs ("\n.comm ", (FILE)), \
assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%d\n", (SIZE)); \
+ fprintf ((FILE), ",%d\n", (int)(SIZE)); \
} \
}
#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
( fputs (".bss\t", (FILE)), \
assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%d,%d\n", (SIZE), \
+ fprintf ((FILE), ",%d,%d\n", (int)(SIZE), \
(floor_log2 ((ALIGN) / BITS_PER_UNIT))))
/* A C statement (sans semicolon) to output to the stdio stream
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
do { \
- fputs (".globl ", (FILE)); \
- assemble_name ((FILE), (NAME)); \
- fputs ("\n", (FILE)); \
ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
} while (0)
#define LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_CODE_ALIGN ? 3 : 0)
-/* Store in OUTPUT a string (made with alloca) containing
- an assembler-name for a local static variable named NAME.
- LABELNO is an integer which is different for each call. */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
- ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
- sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
- in assembler code. */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences. */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-\f
-/* Output assembler code to FILE to initialize this source file's
- basic block profiling info, if that has not already been done. */
-
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
-{ fprintf (FILE, "\tld LPBX0,g12\n"); \
- fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\
- fprintf (FILE, "\tlda LPBX0,g12\n"); \
- fprintf (FILE, "\tcall ___bb_init_func\n"); \
- fprintf (FILE, "LPY%d:\n",LABELNO); }
-
-/* Output assembler code to FILE to increment the entry-count for
- the BLOCKNO'th basic block in this source file. */
-
-#define BLOCK_PROFILER(FILE, BLOCKNO) \
-{ int blockn = (BLOCKNO); \
- fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \
- fprintf (FILE, "\taddo g12,1,g12\n"); \
- fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); }
\f
/* Print operand X (an rtx) in assembler syntax to file FILE.
CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
i960_print_operand_addr (FILE, ADDR)
+
+/* Determine which codes are valid without a following integer. These must
+ not be alphabetic (the characters are chosen so that
+ PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
+ using ASCII). */
+
+#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '+')
\f
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts. */
/* On the i960, the trampoline contains three instructions:
ldconst _function, r4
- ldconst static addr, r3
+ ldconst static addr, g12
jump (r4) */
#define TRAMPOLINE_TEMPLATE(FILE) \
{ \
- ASM_OUTPUT_INT (FILE, GEN_INT (0x8C203000)); \
- ASM_OUTPUT_INT (FILE, GEN_INT (0x00000000)); \
- ASM_OUTPUT_INT (FILE, GEN_INT (0x8C183000)); \
- ASM_OUTPUT_INT (FILE, GEN_INT (0x00000000)); \
- ASM_OUTPUT_INT (FILE, GEN_INT (0x84212000)); \
+ assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x8C203000)); \
+ assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x00000000)); \
+ assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x8CE03000)); \
+ assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x00000000)); \
+ assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x84212000)); \
}
/* Length in units of the trampoline for entering a nested function. */
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
- emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \
- FNADDR); \
- emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), \
- CXT); \
+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), FNADDR); \
+ emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), CXT); \
}
/* Generate RTL to flush the register windows so as to make arbitrary frames
{"power2_operand", {CONST_INT}}, \
{"cmplpower2_operand", {CONST_INT}},
-/* Define functions in i960.c and used in insn-output.c. */
-
-extern char *i960_output_ldconst ();
-extern char *i960_output_call_insn ();
-extern char *i960_output_ret_insn ();
-extern char *i960_output_move_double ();
-extern char *i960_output_move_quad ();
-
/* Defined in reload.c, and used in insn-recog.c. */
extern int rtx_equal_function_value_matters;
-
-/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
- Used for C++ multiple inheritance. */
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
-do { \
- int d = (DELTA); \
- if (d < 0 && d > -32) \
- fprintf (FILE, "\tsubo %d,g0,g0\n", -d); \
- else if (d > 0 && d < 32) \
- fprintf (FILE, "\taddo %d,g0,g0\n", d); \
- else \
- { \
- fprintf (FILE, "\tldconst %d,r5\n", d); \
- fprintf (FILE, "\taddo r5,g0,g0\n"); \
- } \
- fprintf (FILE, "\tbx "); \
- assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
- fprintf (FILE, "\n"); \
-} while (0);
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