;; Machine description of the Renesas M32R cpu for GNU C compiler
-;; Copyright (C) 1996, 1997, 1998, 1999, 2001, 2003, 2004
-; Free Software Foundation, Inc.
+;; Copyright (C) 1996-2020 Free Software Foundation, Inc.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
-;; by the Free Software Foundation; either version 2, or (at your
+;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
\f
[(UNSPEC_LOAD_SDA_BASE 2)
(UNSPEC_SET_CBIT 3)
(UNSPEC_PIC_LOAD_ADDR 4)
- (UNSPEC_GET_PC 5)])
+ (UNSPEC_GET_PC 5)
+ (UNSPEC_GOTOFF 6)
+ ])
;; Insn type. Used to default other attribute values.
(define_attr "type"
;; The target CPU we're compiling for.
(define_attr "cpu" "m32r,m32r2,m32rx"
- (cond [(ne (symbol_ref "TARGET_M32RX") (const_int 0))
+ (cond [(match_test "TARGET_M32RX")
(const_string "m32rx")
- (ne (symbol_ref "TARGET_M32R2") (const_int 0))
+ (match_test "TARGET_M32R2")
(const_string "m32r2")]
(const_string "m32r")))
;; These fetch units are a hack to get GCC to better pack the instructions
;; for the M32Rx processor, which has two execution pipes.
;;
-;; In reality there is only one decoder, which can decode either two 16 bits
-;; instructions, or a single 32 bits instruction.
+;; In reality there is only one decoder, which can decode either two 16-bit
+;; instructions, or a single 32-bit instruction.
;;
;; Note, "fetch" models both the IF and the D pipeline stages.
;;
;; Load/store instructions do 6 stages: IF D E MEM1 MEM2 WB.
;; MEM1 may require more than one cycle depending on locality. We
-;; optimistically assume all memory is nearby, ie. MEM1 takes only
+;; optimistically assume all memory is nearby, i.e. MEM1 takes only
;; one cycle. Hence, ready latency is 3.
;; The M32Rx can do short load/store only on the left pipe.
"long_IF,long_E,memory*2")
\f
+(include "predicates.md")
+(include "constraints.md")
+
;; Expand prologue as RTL
(define_expand "prologue"
[(const_int 1)]
DONE;
}")
+;; Expand epilogue as RTL
+(define_expand "epilogue"
+ [(return)]
+ ""
+ "
+{
+ m32r_expand_epilogue ();
+ emit_jump_insn (gen_return_normal ());
+ DONE;
+}")
\f
;; Move instructions.
;;
/* Everything except mem = const or mem = mem can be done easily.
Objects in the small data area are handled too. */
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (QImode, operands[1]);
}")
/* Everything except mem = const or mem = mem can be done easily. */
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (HImode, operands[1]);
}")
/* Everything except mem = const or mem = mem can be done easily. */
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (SImode, operands[1]);
/* Small Data Area reference? */
"register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
"*
{
- if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == SUBREG)
+ if (REG_P (operands[0]) || GET_CODE (operands[1]) == SUBREG)
{
switch (GET_CODE (operands[1]))
{
- HOST_WIDE_INT value;
-
default:
break;
return \"ld %0,%1\";
case CONST_INT:
- value = INTVAL (operands[1]);
- if (INT16_P (value))
+ if (satisfies_constraint_J (operands[1]))
return \"ldi %0,%#%1\\t; %X1\";
- if (UINT24_P (value))
+ if (satisfies_constraint_M (operands[1]))
return \"ld24 %0,%#%1\\t; %X1\";
- if (UPPER16_P (value))
+ if (satisfies_constraint_L (operands[1]))
return \"seth %0,%#%T1\\t; %X1\";
return \"#\";
}
}
- else if (GET_CODE (operands[0]) == MEM
- && (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG))
+ else if (MEM_P (operands[0])
+ && (REG_P (operands[1]) || GET_CODE (operands[1]) == SUBREG))
{
if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
&& XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
return \"st %1,%0\";
}
- abort ();
+ gcc_unreachable ();
}"
[(set_attr "type" "int2,int2,int4,int4,int4,multi,load2,load2,load4,store2,store2,store4")
(set_attr "length" "2,2,4,4,4,8,2,2,4,2,2,4")])
use 2 byte instructions wherever possible. We can assume the
constant isn't loadable with any of ldi, ld24, or seth. */
- /* See if we can load a 24 bit unsigned value and invert it. */
+ /* See if we can load a 24-bit unsigned value and invert it. */
if (UINT24_P (~ val))
{
emit_insn (gen_movsi (operands[0], GEN_INT (~ val)));
DONE;
}
- /* See if we can load a 24 bit unsigned value and shift it into place.
+ /* See if we can load a 24-bit unsigned value and shift it into place.
0x01fffffe is just beyond ld24's range. */
for (shift = 1, tmp = 0x01fffffe;
shift < 8;
;; the small data area are indexed off that. This is done for each reference
;; but cse will clean things up for us. We let the compiler choose the
;; register to use so we needn't allocate (and maybe even fix) a special
-;; register to use. Since the load and store insns have a 16 bit offset the
+;; register to use. Since the load and store insns have a 16-bit offset the
;; total size of the data area can be 64K. However, if the data area lives
;; above 16M (24 bits), _SDA_BASE_ will have to be loaded with seth/add3 which
;; would then yield 3 instructions to reference an object [though there would
operands[2] = gen_reg_rtx (SImode);
}")
+(define_insn "*load_sda_base_32"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
+ "TARGET_ADDR32"
+ "seth %0,%#shigh(_SDA_BASE_)\;add3 %0,%0,%#low(_SDA_BASE_)"
+ [(set_attr "type" "multi")
+ (set_attr "length" "8")])
+
(define_insn "*load_sda_base"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
[(set_attr "type" "int4")
(set_attr "length" "4")])
-;; 32 bit address support.
+;; 32-bit address support.
(define_expand "movsi_addr32"
[(set (match_dup 2)
/* Everything except mem = const or mem = mem can be done easily. */
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (DImode, operands[1]);
}")
/* Everything except mem = const or mem = mem can be done easily. */
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (SFmode, operands[1]);
}")
/* Everything except mem = const or mem = mem can be done easily. */
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (DFmode, operands[1]);
}")
; (match_operand:SI 2 "int8_operand" "")))]
; "reload_completed
; && REGNO (operands[0]) != REGNO (operands[1])
-; && INT8_P (INTVAL (operands[2]))
+; && satisfies_constraint_I (operands[2])
; && INTVAL (operands[2]) != 0"
; [(set (match_dup 0) (match_dup 1))
; (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
short instructions, which might eliminate a NOP being inserted. */
if (optimize_size
&& m32r_not_same_reg (operands[0], operands[1])
- && GET_CODE (operands[2]) == CONST_INT
- && INT8_P (INTVAL (operands[2])))
+ && satisfies_constraint_I (operands[2]))
return \"#\";
- else if (GET_CODE (operands[2]) == CONST_INT)
+ else if (CONST_INT_P (operands[2]))
return \"and3 %0,%1,%#%X2\";
return \"and %0,%2\";
short instructions, which might eliminate a NOP being inserted. */
if (optimize_size
&& m32r_not_same_reg (operands[0], operands[1])
- && GET_CODE (operands[2]) == CONST_INT
- && INT8_P (INTVAL (operands[2])))
+ && satisfies_constraint_I (operands[2]))
return \"#\";
- else if (GET_CODE (operands[2]) == CONST_INT)
+ else if (CONST_INT_P (operands[2]))
return \"or3 %0,%1,%#%X2\";
return \"or %0,%2\";
short instructions, which might eliminate a NOP being inserted. */
if (optimize_size
&& m32r_not_same_reg (operands[0], operands[1])
- && GET_CODE (operands[2]) == CONST_INT
- && INT8_P (INTVAL (operands[2])))
+ && satisfies_constraint_I (operands[2]))
return \"#\";
- else if (GET_CODE (operands[2]) == CONST_INT)
+ else if (CONST_INT_P (operands[2]))
return \"xor3 %0,%1,%#%X2\";
return \"xor %0,%2\";
;; Compare instructions.
;; This controls RTL generation and register allocation.
-;; We generate RTL for comparisons and branches by having the cmpxx
+;; We generate RTL for comparisons and branches by having the cmpxx
;; patterns store away the operands. Then the bcc patterns
;; emit RTL for both the compare and the branch.
;;
;; thus merge the compare and branch into one instruction, so they are
;; preferred.
-(define_expand "cmpsi"
- [(set (reg:CC 17)
- (compare:CC (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "reg_or_cmp_int16_operand" "")))]
- ""
- "
-{
- m32r_compare_op0 = operands[0];
- m32r_compare_op1 = operands[1];
- DONE;
-}")
-
(define_insn "cmp_eqsi_zero_insn"
[(set (reg:CC 17)
(eq:CC (match_operand:SI 0 "register_operand" "r,r")
\f
;; These control RTL generation for conditional jump insns.
-(define_expand "beq"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_compare (EQ, m32r_compare_op0, m32r_compare_op1, FALSE);
-}")
-
-(define_expand "bne"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_compare (NE, m32r_compare_op0, m32r_compare_op1, FALSE);
-}")
-
-(define_expand "bgt"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_compare (GT, m32r_compare_op0, m32r_compare_op1, FALSE);
-}")
-
-(define_expand "ble"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_compare (LE, m32r_compare_op0, m32r_compare_op1, FALSE);
-}")
-
-(define_expand "bge"
+(define_expand "cbranchsi4"
+ ; the comparison is emitted by gen_compare if needed.
[(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_compare (GE, m32r_compare_op0, m32r_compare_op1, FALSE);
-}")
-
-(define_expand "blt"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_compare (LT, m32r_compare_op0, m32r_compare_op1, FALSE);
-}")
-
-(define_expand "bgtu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "reg_or_cmp_int16_operand" "")])
+ (label_ref (match_operand 3 "" ""))
(pc)))]
""
"
{
- operands[1] = gen_compare (GTU, m32r_compare_op0, m32r_compare_op1, FALSE);
-}")
-
-(define_expand "bleu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_compare (LEU, m32r_compare_op0, m32r_compare_op1, FALSE);
-}")
-
-(define_expand "bgeu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_compare (GEU, m32r_compare_op0, m32r_compare_op1, FALSE);
-}")
-
-(define_expand "bltu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "
-{
- operands[1] = gen_compare (LTU, m32r_compare_op0, m32r_compare_op1, FALSE);
+ operands[0] = gen_compare (GET_CODE (operands[0]), operands[1], operands[2], FALSE);
+ operands[1] = XEXP (operands[0], 0);
+ operands[2] = XEXP (operands[0], 1);
}")
;; Now match both normal and inverted jump.
return instruction;
}"
[(set_attr "type" "branch")
- ; We use 400/800 instead of 512,1024 to account for inaccurate insn
+ ; cf PR gcc/28508
+ ; We use 300/600 instead of 512,1024 to account for inaccurate insn
; lengths and insn alignments that are complex to track.
; It's not important that we be hyper-precise here. It may be more
; important blah blah blah when the chip supports parallel execution
; blah blah blah but until then blah blah blah this is simple and
; suffices.
(set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
- (const_int 400))
- (const_int 800))
+ (const_int 300))
+ (const_int 600))
(const_int 2)
(const_int 4)))])
return instruction;
}"
[(set_attr "type" "branch")
- ; We use 400/800 instead of 512,1024 to account for inaccurate insn
+ ; cf PR gcc/28508
+ ; We use 300/600 instead of 512,1024 to account for inaccurate insn
; lengths and insn alignments that are complex to track.
; It's not important that we be hyper-precise here. It may be more
; important blah blah blah when the chip supports parallel execution
; blah blah blah but until then blah blah blah this is simple and
; suffices.
(set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
- (const_int 400))
- (const_int 800))
+ (const_int 300))
+ (const_int 600))
(const_int 2)
(const_int 4)))])
case LT : br = \"lt\"; invbr = \"ge\"; break;
case GE : br = \"ge\"; invbr = \"lt\"; break;
- default: abort();
+ default: gcc_unreachable ();
}
/* Is branch target reachable with bxxz? */
case LT : br = \"lt\"; invbr = \"ge\"; break;
case GE : br = \"ge\"; invbr = \"lt\"; break;
- default: abort();
+ default: gcc_unreachable ();
}
/* Is branch target reachable with bxxz? */
\f
;; S<cc> operations to set a register to 1/0 based on a comparison
-(define_expand "seq"
- [(match_operand:SI 0 "register_operand" "")]
+(define_expand "cstoresi4"
+ [(match_operand:SI 0 "register_operand" "")
+ (match_operator:SI 1 "ordered_comparison_operator"
+ [(match_operand:SI 2 "register_operand" "")
+ (match_operand:SI 3 "reg_or_cmp_int16_operand" "")])]
""
"
{
- rtx op0 = operands[0];
- rtx op1 = m32r_compare_op0;
- rtx op2 = m32r_compare_op1;
- enum machine_mode mode = GET_MODE (op0);
-
- if (mode != SImode)
+ if (GET_MODE (operands[0]) != SImode)
FAIL;
- if (! register_operand (op1, mode))
- op1 = force_reg (mode, op1);
-
- if (TARGET_M32RX || TARGET_M32R2)
- {
- if (! reg_or_zero_operand (op2, mode))
- op2 = force_reg (mode, op2);
-
- emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
- DONE;
- }
- if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0)
- {
- emit_insn (gen_seq_zero_insn (op0, op1));
- DONE;
- }
-
- if (! reg_or_eq_int16_operand (op2, mode))
- op2 = force_reg (mode, op2);
+ if (!gen_cond_store (GET_CODE (operands[1]),
+ operands[0], operands[2], operands[3]))
+ FAIL;
- emit_insn (gen_seq_insn (op0, op1, op2));
DONE;
}")
rtx op3 = operands[3];
HOST_WIDE_INT value;
- if (GET_CODE (op2) == REG && GET_CODE (op3) == REG
+ if (REG_P (op2) && REG_P (op3)
&& REGNO (op2) == REGNO (op3))
{
op1 = operands[2];
}
start_sequence ();
- if (GET_CODE (op1) == REG && GET_CODE (op3) == REG
+ if (REG_P (op1) && REG_P (op3)
&& REGNO (op1) != REGNO (op3))
{
emit_move_insn (op3, op1);
op1 = op3;
}
- if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
- && CMP_INT16_P (value))
+ if (satisfies_constraint_P (op2) && (value = INTVAL (op2)) != 0)
emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
else
emit_insn (gen_xorsi3 (op3, op1, op2));
end_sequence ();
}")
-(define_expand "sne"
- [(match_operand:SI 0 "register_operand" "")]
- ""
- "
-{
- rtx op0 = operands[0];
- rtx op1 = m32r_compare_op0;
- rtx op2 = m32r_compare_op1;
- enum machine_mode mode = GET_MODE (op0);
-
- if (mode != SImode)
- FAIL;
-
- if (GET_CODE (op2) != CONST_INT
- || (INTVAL (op2) != 0 && UINT16_P (INTVAL (op2))))
- {
- rtx reg;
-
- if (reload_completed || reload_in_progress)
- FAIL;
-
- reg = gen_reg_rtx (SImode);
- emit_insn (gen_xorsi3 (reg, op1, op2));
- op1 = reg;
-
- if (! register_operand (op1, mode))
- op1 = force_reg (mode, op1);
-
- emit_insn (gen_sne_zero_insn (op0, op1));
- DONE;
- }
- else
- FAIL;
-}")
-
(define_insn "sne_zero_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
(ne:SI (match_operand:SI 1 "register_operand" "r")
(set (match_dup 0)
(ne:SI (reg:CC 17) (const_int 0)))]
"")
-
-(define_expand "slt"
- [(match_operand:SI 0 "register_operand" "")]
- ""
- "
-{
- rtx op0 = operands[0];
- rtx op1 = m32r_compare_op0;
- rtx op2 = m32r_compare_op1;
- enum machine_mode mode = GET_MODE (op0);
-
- if (mode != SImode)
- FAIL;
-
- if (! register_operand (op1, mode))
- op1 = force_reg (mode, op1);
-
- if (! reg_or_int16_operand (op2, mode))
- op2 = force_reg (mode, op2);
-
- emit_insn (gen_slt_insn (op0, op1, op2));
- DONE;
-}")
(define_insn "slt_insn"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ne:SI (reg:CC 17) (const_int 0)))]
"")
-(define_expand "sle"
- [(match_operand:SI 0 "register_operand" "")]
- ""
- "
-{
- rtx op0 = operands[0];
- rtx op1 = m32r_compare_op0;
- rtx op2 = m32r_compare_op1;
- enum machine_mode mode = GET_MODE (op0);
-
- if (mode != SImode)
- FAIL;
-
- if (! register_operand (op1, mode))
- op1 = force_reg (mode, op1);
-
- if (GET_CODE (op2) == CONST_INT)
- {
- HOST_WIDE_INT value = INTVAL (op2);
- if (value >= 2147483647)
- {
- emit_move_insn (op0, const1_rtx);
- DONE;
- }
-
- op2 = GEN_INT (value+1);
- if (value < -32768 || value >= 32767)
- op2 = force_reg (mode, op2);
-
- emit_insn (gen_slt_insn (op0, op1, op2));
- DONE;
- }
-
- if (! register_operand (op2, mode))
- op2 = force_reg (mode, op2);
-
- emit_insn (gen_sle_insn (op0, op1, op2));
- DONE;
-}")
-
(define_insn "sle_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
(le:SI (match_operand:SI 1 "register_operand" "r")
(neg:SI (match_dup 0)))]
"")
-(define_expand "sgt"
- [(match_operand:SI 0 "register_operand" "")]
- ""
- "
-{
- rtx op0 = operands[0];
- rtx op1 = m32r_compare_op0;
- rtx op2 = m32r_compare_op1;
- enum machine_mode mode = GET_MODE (op0);
-
- if (mode != SImode)
- FAIL;
-
- if (! register_operand (op1, mode))
- op1 = force_reg (mode, op1);
-
- if (! register_operand (op2, mode))
- op2 = force_reg (mode, op2);
-
- emit_insn (gen_slt_insn (op0, op2, op1));
- DONE;
-}")
-
-(define_expand "sge"
- [(match_operand:SI 0 "register_operand" "")]
- ""
- "
-{
- rtx op0 = operands[0];
- rtx op1 = m32r_compare_op0;
- rtx op2 = m32r_compare_op1;
- enum machine_mode mode = GET_MODE (op0);
-
- if (mode != SImode)
- FAIL;
-
- if (! register_operand (op1, mode))
- op1 = force_reg (mode, op1);
-
- if (! reg_or_int16_operand (op2, mode))
- op2 = force_reg (mode, op2);
-
- emit_insn (gen_sge_insn (op0, op1, op2));
- DONE;
-}")
-
(define_insn "sge_insn"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ge:SI (match_operand:SI 1 "register_operand" "r,r")
(neg:SI (match_dup 0)))]
"")
-(define_expand "sltu"
- [(match_operand:SI 0 "register_operand" "")]
- ""
- "
-{
- rtx op0 = operands[0];
- rtx op1 = m32r_compare_op0;
- rtx op2 = m32r_compare_op1;
- enum machine_mode mode = GET_MODE (op0);
-
- if (mode != SImode)
- FAIL;
-
- if (! register_operand (op1, mode))
- op1 = force_reg (mode, op1);
-
- if (! reg_or_int16_operand (op2, mode))
- op2 = force_reg (mode, op2);
-
- emit_insn (gen_sltu_insn (op0, op1, op2));
- DONE;
-}")
-
(define_insn "sltu_insn"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ltu:SI (match_operand:SI 1 "register_operand" "r,r")
(ne:SI (reg:CC 17) (const_int 0)))]
"")
-(define_expand "sleu"
- [(match_operand:SI 0 "register_operand" "")]
- ""
- "
-{
- rtx op0 = operands[0];
- rtx op1 = m32r_compare_op0;
- rtx op2 = m32r_compare_op1;
- enum machine_mode mode = GET_MODE (op0);
-
- if (mode != SImode)
- FAIL;
-
- if (GET_CODE (op2) == CONST_INT)
- {
- HOST_WIDE_INT value = INTVAL (op2);
- if (value >= 2147483647)
- {
- emit_move_insn (op0, const1_rtx);
- DONE;
- }
-
- op2 = GEN_INT (value+1);
- if (value < 0 || value >= 32767)
- op2 = force_reg (mode, op2);
-
- emit_insn (gen_sltu_insn (op0, op1, op2));
- DONE;
- }
-
- if (! register_operand (op2, mode))
- op2 = force_reg (mode, op2);
-
- emit_insn (gen_sleu_insn (op0, op1, op2));
- DONE;
-}")
-
(define_insn "sleu_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
(leu:SI (match_operand:SI 1 "register_operand" "r")
(neg:SI (match_dup 0)))]
"")
-(define_expand "sgtu"
- [(match_operand:SI 0 "register_operand" "")]
- ""
- "
-{
- rtx op0 = operands[0];
- rtx op1 = m32r_compare_op0;
- rtx op2 = m32r_compare_op1;
- enum machine_mode mode = GET_MODE (op0);
-
- if (mode != SImode)
- FAIL;
-
- if (! register_operand (op1, mode))
- op1 = force_reg (mode, op1);
-
- if (! register_operand (op2, mode))
- op2 = force_reg (mode, op2);
-
- emit_insn (gen_sltu_insn (op0, op2, op1));
- DONE;
-}")
-
-(define_expand "sgeu"
- [(match_operand:SI 0 "register_operand" "")]
- ""
- "
-{
- rtx op0 = operands[0];
- rtx op1 = m32r_compare_op0;
- rtx op2 = m32r_compare_op1;
- enum machine_mode mode = GET_MODE (op0);
-
- if (mode != SImode)
- FAIL;
-
- if (! register_operand (op1, mode))
- op1 = force_reg (mode, op1);
-
- if (! reg_or_int16_operand (op2, mode))
- op2 = force_reg (mode, op2);
-
- emit_insn (gen_sgeu_insn (op0, op1, op2));
- DONE;
-}")
-
(define_insn "sgeu_insn"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(geu:SI (match_operand:SI 1 "register_operand" "r,r")
[(set_attr "type" "uncond_branch")
(set_attr "length" "2")])
-(define_insn "return"
- [(return)]
- "direct_return ()"
+(define_insn "return_lr"
+ [(parallel [(return) (use (reg:SI 14))])]
+ ""
"jmp lr"
[(set_attr "type" "uncond_branch")
(set_attr "length" "2")])
-
+
+(define_insn "return_rte"
+ [(return)]
+ ""
+ "rte"
+ [(set_attr "type" "uncond_branch")
+ (set_attr "length" "2")])
+
+(define_expand "return"
+ [(return)]
+ "direct_return ()"
+ "
+{
+ emit_jump_insn (gen_return_lr ());
+ DONE;
+}")
+
+(define_expand "return_normal"
+ [(return)]
+ "!direct_return ()"
+ "
+{
+ enum m32r_function_type fn_type;
+
+ fn_type = m32r_compute_function_type (current_function_decl);
+ if (M32R_INTERRUPT_P (fn_type))
+ {
+ emit_jump_insn (gen_return_rte ());
+ DONE;
+ }
+
+ emit_jump_insn (gen_return_lr ());
+ DONE;
+}")
+
(define_expand "tablejump"
[(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
(use (label_ref (match_operand 1 "" "")))])]
"
{
if (flag_pic)
- current_function_uses_pic_offset_table = 1;
+ crtl->uses_pic_offset_table = 1;
}")
(define_insn "*call_via_reg"
}"
[(set_attr "type" "call")
(set (attr "length")
- (if_then_else (eq (symbol_ref "call26_operand (operands[0], FUNCTION_MODE)")
- (const_int 0))
+ (if_then_else (not (match_test "call26_operand (operands[0], FUNCTION_MODE)"))
(const_int 12) ; 10 + 2 for nop filler
; The return address must be on a 4 byte boundary so
; there's no point in using a value of 2 here. A 2 byte
(match_operand 2 "" "")))
(clobber (reg:SI 14))])]
""
- "
+ "
{
if (flag_pic)
- current_function_uses_pic_offset_table = 1;
+ crtl->uses_pic_offset_table = 1;
}")
(define_insn "*call_value_via_reg"
int call26_p = call26_operand (operands[1], FUNCTION_MODE);
if (flag_pic)
- current_function_uses_pic_offset_table = 1;
+ crtl->uses_pic_offset_table = 1;
if (! call26_p)
{
}"
[(set_attr "type" "call")
(set (attr "length")
- (if_then_else (eq (symbol_ref "call26_operand (operands[1], FUNCTION_MODE)")
- (const_int 0))
+ (if_then_else (not (match_test "call26_operand (operands[1], FUNCTION_MODE)"))
(const_int 12) ; 10 + 2 for nop filler
; The return address must be on a 4 byte boundary so
; there's no point in using a value of 2 here. A 2 byte
FAIL;
/* Generate the comparison that will set the carry flag. */
- operands[1] = gen_compare (GET_CODE (operands[1]), m32r_compare_op0,
- m32r_compare_op1, TRUE);
+ operands[1] = gen_compare (GET_CODE (operands[1]), XEXP (operands[1], 0),
+ XEXP (operands[1], 1), TRUE);
/* See other movsicc pattern below for reason why. */
emit_insn (gen_blockage ());
;; Argument 2 is the length
;; Argument 3 is the alignment
-(define_expand "movmemsi"
+(define_expand "cpymemsi"
[(parallel [(set (match_operand:BLK 0 "general_operand" "")
(match_operand:BLK 1 "general_operand" ""))
(use (match_operand:SI 2 "immediate_operand" ""))
""
"
{
- if (operands[0]) /* avoid unused code messages */
+ if (operands[0]) /* Avoid unused code messages. */
{
- m32r_expand_block_move (operands);
- DONE;
+ if (m32r_expand_block_move (operands))
+ DONE;
+ else
+ FAIL;
}
}")
;; Insn generated by block moves
-(define_insn "movmemsi_internal"
+(define_insn "cpymemsi_internal"
[(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) ;; destination
(mem:BLK (match_operand:SI 1 "register_operand" "r"))) ;; source
(use (match_operand:SI 2 "m32r_block_immediate_operand" "J"));; # bytes to move
(set (match_operand:SI 3 "register_operand" "=0")
- (plus:SI (match_dup 0)
- (minus (match_dup 2) (const_int 4))))
+ (plus:SI (minus (match_dup 2) (const_int 4))
+ (match_dup 0)))
(set (match_operand:SI 4 "register_operand" "=1")
(plus:SI (match_dup 1)
(match_dup 2)))
"ld24 %0,%#%1"
[(set_attr "type" "int4")])
+(define_insn "gotoff_load_addr"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOTOFF))]
+ "flag_pic"
+ "seth %0, %#shigh(%1@GOTOFF)\;add3 %0, %0, low(%1@GOTOFF)"
+ [(set_attr "type" "int4")
+ (set_attr "length" "8")])
+
;; Load program counter insns.
(define_insn "get_pc"
[(clobber (reg:SI 14))
- (set (match_operand 0 "register_operand" "=r")
+ (set (match_operand 0 "register_operand" "=r,r")
(unspec [(match_operand 1 "" "")] UNSPEC_GET_PC))
- (use (match_operand:SI 2 "immediate_operand" ""))]
+ (use (match_operand:SI 2 "immediate_operand" "W,i"))]
"flag_pic"
- "*
-{
- if (INTVAL(operands[2]))
- return \"bl.s .+4\;ld24 %0,%#%1\;add %0,lr\";
- else
- return \"bl.s .+4\;seth %0,%#shigh(%1)\;add3 %0,%0,%#low(%1+4)\;add %0,lr\";}"
- [(set (attr "length") (if_then_else (ne (match_dup 2) (const_int 0))
- (const_int 8)
- (const_int 12)))])
+ "@
+ bl.s .+4\;seth %0,%#shigh(%1)\;add3 %0,%0,%#low(%1+4)\;add %0,lr
+ bl.s .+4\;ld24 %0,%#%1\;add %0,lr"
+ [(set_attr "length" "12,8")])
(define_expand "builtin_setjmp_receiver"
[(label_ref (match_operand 0 "" ""))]
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