(cond [(eq_attr "type" "load,store")
(const_string "mem")
- (eq_attr "type" "mfhilo,mthilo,imul,imul3,imadd,idiv")
+ (eq_attr "type" "mfhi,mflo,mthi,mtlo,imul,imul3,imadd,idiv")
(const_string "mul")]
(const_string "alu")))
(define_insn_reservation "vr4130_mfhilo" 3
(and (eq_attr "cpu" "r4130")
- (eq_attr "type" "mfhilo"))
+ (eq_attr "type" "mfhi,mflo"))
"vr4130_muldiv")
(define_insn_reservation "vr4130_mthilo" 1
(and (eq_attr "cpu" "r4130")
- (eq_attr "type" "mthilo"))
+ (eq_attr "type" "mthi,mtlo"))
"vr4130_muldiv")
;; The product is available in LO & HI after one cycle. Moving the result