Update copyright years.

[thirdparty/gcc.git] / gcc / config / mips / mips.md

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 658f5e62b842af32d50077a34e8db34d87e6b61e..6383a31a5e396a4ad00f15a09dfe1331ccb35dc6 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1,5 +1,5 @@
 ;;  Mips.md         Machine Description for MIPS based processors
-;;  Copyright (C) 1989-2019 Free Software Foundation, Inc.
+;;  Copyright (C) 1989-2020 Free Software Foundation, Inc.
 ;;  Contributed by   A. Lichnewsky, lich@inria.inria.fr
 ;;  Changes by       Michael Meissner, meissner@osf.org
 ;;  64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
@@ -560,6 +560,12 @@
         (eq_attr "type" "idiv,idiv3")
         (symbol_ref "mips_idiv_insns (GET_MODE (PATTERN (insn)))")
 
+        ;; simd div have 3 instruction if TARGET_CHECK_ZERO_DIV is true.
+        (eq_attr "type" "simd_div")
+        (if_then_else (match_test "TARGET_CHECK_ZERO_DIV")
+                      (const_int 3)
+                      (const_int 1))
+
         (not (eq_attr "sync_mem" "none"))
         (symbol_ref "mips_sync_loop_insns (insn, operands)")]
        (const_int 1)))
@@ -759,7 +765,7 @@
 
 ;; Can the instruction be put into a delay slot?
 (define_attr "can_delay" "no,yes"
-  (if_then_else (and (eq_attr "type" "!branch,call,jump")
+  (if_then_else (and (eq_attr "type" "!branch,call,jump,simd_branch")
                     (eq_attr "hazard" "none")
                     (match_test "get_attr_insn_count (insn) == 1"))
                (const_string "yes")
@@ -1098,7 +1104,7 @@
 
 ;; Branches that have delay slots and don't have likely variants do
 ;; not annul on false.
-(define_delay (and (eq_attr "type" "branch")
+(define_delay (and (eq_attr "type" "branch,simd_branch")
                   (not (match_test "TARGET_MIPS16"))
                   (ior (match_test "TARGET_CB_NEVER")
                        (and (eq_attr "compact_form" "maybe")
@@ -5845,8 +5851,8 @@
   "ISA_HAS_ROR"
 {
   if (CONST_INT_P (operands[2]))
-    gcc_assert (INTVAL (operands[2]) >= 0
-               && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
+    operands[2] = GEN_INT (INTVAL (operands[2])
+                           & (GET_MODE_BITSIZE (<MODE>mode) - 1));
 
   return "<d>ror\t%0,%1,%2";
 }