+; Options for the MIPS port of the compiler
+;
+; Copyright (C) 2005-2024 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 3, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT
+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+; License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING3. If not see
+; <http://www.gnu.org/licenses/>.
+
+HeaderInclude
+config/mips/mips-opts.h
+
+EB
+Driver
+
+EL
+Driver
+
mabi=
-Target RejectNegative Joined
--mabi=ABI Generate code that conforms to the given ABI
+Target RejectNegative Joined Enum(mips_abi) Var(mips_abi) Init(MIPS_ABI_DEFAULT)
+-mabi=ABI Generate code that conforms to the given ABI.
+
+Enum
+Name(mips_abi) Type(int)
+Known MIPS ABIs (for use with the -mabi= option):
+
+EnumValue
+Enum(mips_abi) String(32) Value(ABI_32)
+
+EnumValue
+Enum(mips_abi) String(o64) Value(ABI_O64)
+
+EnumValue
+Enum(mips_abi) String(n32) Value(ABI_N32)
+
+EnumValue
+Enum(mips_abi) String(64) Value(ABI_64)
+
+EnumValue
+Enum(mips_abi) String(eabi) Value(ABI_EABI)
mabicalls
-Target Report Mask(ABICALLS)
-Use SVR4-style PIC
+Target Mask(ABICALLS)
+Generate code that can be used in SVR4-style dynamic objects.
-mad
-Target Report Var(TARGET_MAD)
-Use PMC-style 'mad' instructions
+mmad
+Target Var(TARGET_MAD)
+Use PMC-style 'mad' instructions.
+
+mimadd
+Target Mask(IMADD)
+Use integer madd/msub instructions.
march=
-Target RejectNegative Joined
--march=ISA Generate code for the given ISA
+Target RejectNegative Joined Var(mips_arch_option) ToLower Enum(mips_arch_opt_value)
+-march=ISA Generate code for the given ISA.
+
+mbranch-cost=
+Target RejectNegative Joined UInteger Var(mips_branch_cost)
+-mbranch-cost=COST Set the cost of branches to roughly COST instructions.
mbranch-likely
-Target Report Mask(BRANCHLIKELY)
-Use Branch Likely instructions, overriding the architecture default
+Target Mask(BRANCHLIKELY)
+Use Branch Likely instructions, overriding the architecture default.
+
+mflip-mips16
+Target Var(TARGET_FLIP_MIPS16)
+Switch on/off MIPS16 ASE on alternating functions for compiler testing.
mcheck-zero-division
-Target Report Mask(CHECK_ZERO_DIV)
-Trap on integer divide by zero
+Target Mask(CHECK_ZERO_DIV)
+Trap on integer divide by zero.
+
+mcode-readable=
+Target RejectNegative Joined Enum(mips_code_readable_setting) Var(mips_code_readable) Init(CODE_READABLE_YES)
+-mcode-readable=SETTING Specify when instructions are allowed to access code.
+
+Enum
+Name(mips_code_readable_setting) Type(enum mips_code_readable_setting)
+Valid arguments to -mcode-readable=:
+
+EnumValue
+Enum(mips_code_readable_setting) String(yes) Value(CODE_READABLE_YES)
+
+EnumValue
+Enum(mips_code_readable_setting) String(pcrel) Value(CODE_READABLE_PCREL)
+
+EnumValue
+Enum(mips_code_readable_setting) String(no) Value(CODE_READABLE_NO)
mdivide-breaks
-Target Report Mask(DIVIDE_BREAKS)
-Use branch-and-break sequences to check for integer divide by zero
+Target RejectNegative Mask(DIVIDE_BREAKS)
+Use branch-and-break sequences to check for integer divide by zero.
mdivide-traps
-Target Report InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS)
-Use trap instructions to check for integer divide by zero
+Target RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS)
+Use trap instructions to check for integer divide by zero.
+
+mdmx
+Target RejectNegative Var(TARGET_MDMX)
+Allow the use of MDMX instructions.
mdouble-float
-Target Report RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT)
-Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations
+Target RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT)
+Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
+
+mdsp
+Target Var(TARGET_DSP)
+Use MIPS-DSP instructions.
+
+mdspr2
+Target Var(TARGET_DSPR2)
+Use MIPS-DSP REV 2 instructions.
mdebug
Target Var(TARGET_DEBUG_MODE) Undocumented
Target Var(TARGET_DEBUG_D_MODE) Undocumented
meb
-Target Report RejectNegative Mask(BIG_ENDIAN)
-Use big-endian byte order
+Target RejectNegative Mask(BIG_ENDIAN)
+Use big-endian byte order.
mel
-Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
-Use little-endian byte order
+Target RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
+Use little-endian byte order.
membedded-data
-Target Report Var(TARGET_EMBEDDED_DATA)
-Use ROM instead of RAM
+Target Var(TARGET_EMBEDDED_DATA)
+Use ROM instead of RAM.
+
+meva
+Target Var(TARGET_EVA)
+Use Enhanced Virtual Addressing instructions.
mexplicit-relocs
-Target Report Mask(EXPLICIT_RELOCS)
-Use NewABI-style %reloc() assembly operators
+Target Mask(EXPLICIT_RELOCS)
+Use NewABI-style %reloc() assembly operators.
+
+mextern-sdata
+Target Var(TARGET_EXTERN_SDATA) Init(1)
+Use -G for data that is not defined by the current object.
+
+mfix-24k
+Target Var(TARGET_FIX_24K)
+Work around certain 24K errata.
mfix-r4000
-Target Report Mask(FIX_R4000)
-Work around certain R4000 errata
+Target Mask(FIX_R4000)
+Work around certain R4000 errata.
mfix-r4400
-Target Report Mask(FIX_R4400)
-Work around certain R4400 errata
+Target Mask(FIX_R4400)
+Work around certain R4400 errata.
+
+mfix-r5900
+Target Mask(FIX_R5900)
+Work around the R5900 short loop erratum.
+
+mfix-rm7000
+Target Var(TARGET_FIX_RM7000)
+Work around certain RM7000 errata.
+
+mfix-r10000
+Target Mask(FIX_R10000)
+Work around certain R10000 errata.
mfix-sb1
-Target Report Var(TARGET_FIX_SB1)
-Work around errata for early SB-1 revision 2 cores
+Target Var(TARGET_FIX_SB1)
+Work around errata for early SB-1 revision 2 cores.
mfix-vr4120
-Target Report Var(TARGET_FIX_VR4120)
-Work around certain VR4120 errata
+Target Var(TARGET_FIX_VR4120)
+Work around certain VR4120 errata.
mfix-vr4130
-Target Report Var(TARGET_FIX_VR4130)
-Work around VR4130 mflo/mfhi errata
+Target Var(TARGET_FIX_VR4130)
+Work around VR4130 mflo/mfhi errata.
mfix4300
-Target Report Var(TARGET_4300_MUL_FIX)
-Work around an early 4300 hardware bug
+Target Var(TARGET_4300_MUL_FIX)
+Work around an early 4300 hardware bug.
mfp-exceptions
-Target Report Mask(FP_EXCEPTIONS)
-FP exceptions are enabled
+Target Var(TARGET_FP_EXCEPTIONS) Init(1)
+FP exceptions are enabled.
mfp32
-Target Report RejectNegative InverseMask(FLOAT64)
-Use 32-bit floating-point registers
+Target RejectNegative InverseMask(FLOAT64)
+Use 32-bit floating-point registers.
+
+mfpxx
+Target RejectNegative Mask(FLOATXX)
+Conform to the o32 FPXX ABI.
mfp64
-Target Report RejectNegative Mask(FLOAT64)
-Use 64-bit floating-point registers
+Target RejectNegative Mask(FLOAT64)
+Use 64-bit floating-point registers.
mflush-func=
-Target RejectNegative Joined
--mflush-func=FUNC Use FUNC to flush the cache before calling stack trampolines
+Target RejectNegative Joined Var(mips_cache_flush_func) Init(CACHE_FLUSH_FUNC)
+-mflush-func=FUNC Use FUNC to flush the cache before calling stack trampolines.
+
+mabs=
+Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_abs) Init(MIPS_IEEE_754_DEFAULT)
+-mabs=MODE Select the IEEE 754 ABS/NEG instruction execution mode.
+
+mnan=
+Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_nan) Init(MIPS_IEEE_754_DEFAULT)
+-mnan=ENCODING Select the IEEE 754 NaN data encoding.
-mfused-madd
-Target Report Mask(FUSED_MADD)
-Generate floating-point multiply-add instructions
+Enum
+Name(mips_ieee_754_value) Type(int)
+Known MIPS IEEE 754 settings (for use with the -mabs= and -mnan= options):
+
+EnumValue
+Enum(mips_ieee_754_value) String(2008) Value(MIPS_IEEE_754_2008)
+
+EnumValue
+Enum(mips_ieee_754_value) String(legacy) Value(MIPS_IEEE_754_LEGACY)
mgp32
-Target Report RejectNegative InverseMask(64BIT)
-Use 32-bit general registers
+Target RejectNegative InverseMask(64BIT)
+Use 32-bit general registers.
mgp64
-Target Report RejectNegative Mask(64BIT)
-Use 64-bit general registers
+Target RejectNegative Mask(64BIT)
+Use 64-bit general registers.
+
+mgpopt
+Target Var(TARGET_GPOPT) Init(1)
+Use GP-relative addressing to access small data.
+
+mplt
+Target Var(TARGET_PLT)
+When generating -mabicalls code, allow executables to use PLTs and copy relocations.
mhard-float
-Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
-Allow the use of hardware floating-point instructions
+Target RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
+Allow the use of hardware floating-point ABI and instructions.
-mint64
-Target Report RejectNegative Mask(INT64)
-Use a 64-bit int type
+minterlink-compressed
+Target Var(TARGET_INTERLINK_COMPRESSED) Init(0)
+Generate code that is link-compatible with MIPS16 and microMIPS code.
+
+minterlink-mips16
+Target Var(TARGET_INTERLINK_COMPRESSED) Init(0)
+An alias for minterlink-compressed provided for backward-compatibility.
mips
-Target RejectNegative Joined
--mipsN Generate code for ISA level N
+Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_option)
+-mipsN Generate code for ISA level N.
mips16
-Target Report RejectNegative Mask(MIPS16)
-Generate mips16 code
+Target RejectNegative Mask(MIPS16)
+Generate MIPS16 code.
mips3d
-Target Report RejectNegative Mask(MIPS3D)
-Use MIPS-3D instructions
+Target RejectNegative Var(TARGET_MIPS3D)
+Use MIPS-3D instructions.
+
+mllsc
+Target Mask(LLSC)
+Use ll, sc and sync instructions.
+
+mlocal-sdata
+Target Var(TARGET_LOCAL_SDATA) Init(1)
+Use -G for object-local data.
mlong-calls
-Target Report Var(TARGET_LONG_CALLS)
-Use indirect calls
+Target Var(TARGET_LONG_CALLS)
+Use indirect calls.
mlong32
-Target Report RejectNegative InverseMask(LONG64, LONG32)
-Use a 32-bit long type
+Target RejectNegative InverseMask(LONG64, LONG32)
+Use a 32-bit long type.
mlong64
-Target Report RejectNegative Mask(LONG64)
-Use a 64-bit long type
+Target RejectNegative Mask(LONG64)
+Use a 64-bit long type.
+
+mmcount-ra-address
+Target Var(TARGET_MCOUNT_RA_ADDRESS)
+Pass the address of the ra save location to _mcount in $12.
mmemcpy
-Target Report Var(TARGET_MEMCPY)
-Don't optimize block moves
+Target Mask(MEMCPY)
+Don't optimize block moves.
-mmips-tfile
-Target
-Use the mips-tfile postpass
+mmicromips
+Target Mask(MICROMIPS)
+Use microMIPS instructions.
+
+mmsa
+Target Mask(MSA)
+Use MIPS MSA Extension instructions.
+
+mmt
+Target Var(TARGET_MT)
+Allow the use of MT instructions.
+
+mno-float
+Target RejectNegative Var(TARGET_NO_FLOAT) Condition(TARGET_SUPPORTS_NO_FLOAT)
+Prevent the use of all floating-point operations.
+
+mmcu
+Target Var(TARGET_MCU)
+Use MCU instructions.
mno-flush-func
Target RejectNegative
-Do not use a cache-flushing function before calling stack trampolines
+Do not use a cache-flushing function before calling stack trampolines.
+
+mno-mdmx
+Target RejectNegative Var(TARGET_MDMX, 0)
+Do not use MDMX instructions.
mno-mips16
-Target Report RejectNegative InverseMask(MIPS16)
-Generate normal-mode code
+Target RejectNegative InverseMask(MIPS16)
+Generate normal-mode code.
mno-mips3d
-Target Report RejectNegative InverseMask(MIPS3D)
-Do not use MIPS-3D instructions
+Target RejectNegative Var(TARGET_MIPS3D, 0)
+Do not use MIPS-3D instructions.
mpaired-single
-Target Report Mask(PAIRED_SINGLE_FLOAT)
-Use paired-single floating-point instructions
+Target Mask(PAIRED_SINGLE_FLOAT)
+Use paired-single floating-point instructions.
+
+mr10k-cache-barrier=
+Target Joined RejectNegative Enum(mips_r10k_cache_barrier_setting) Var(mips_r10k_cache_barrier) Init(R10K_CACHE_BARRIER_NONE)
+-mr10k-cache-barrier=SETTING Specify when r10k cache barriers should be inserted.
+
+Enum
+Name(mips_r10k_cache_barrier_setting) Type(enum mips_r10k_cache_barrier_setting)
+Valid arguments to -mr10k-cache-barrier=:
+
+EnumValue
+Enum(mips_r10k_cache_barrier_setting) String(load-store) Value(R10K_CACHE_BARRIER_LOAD_STORE)
+
+EnumValue
+Enum(mips_r10k_cache_barrier_setting) String(store) Value(R10K_CACHE_BARRIER_STORE)
+
+EnumValue
+Enum(mips_r10k_cache_barrier_setting) String(none) Value(R10K_CACHE_BARRIER_NONE)
+
+mrelax-pic-calls
+Target Mask(RELAX_PIC_CALLS)
+Try to allow the linker to turn PIC calls into direct calls.
+
+mshared
+Target Var(TARGET_SHARED) Init(1)
+When generating -mabicalls code, make the code suitable for use in shared libraries.
msingle-float
-Target Report RejectNegative Mask(SINGLE_FLOAT)
-Restrict the use of hardware floating-point instructions to 32-bit operations
+Target RejectNegative Mask(SINGLE_FLOAT)
+Restrict the use of hardware floating-point instructions to 32-bit operations.
+
+msmartmips
+Target Mask(SMARTMIPS)
+Use SmartMIPS instructions.
msoft-float
-Target Report RejectNegative Mask(SOFT_FLOAT)
-Prevent the use of all hardware floating-point instructions
+Target RejectNegative Mask(SOFT_FLOAT_ABI)
+Prevent the use of all hardware floating-point instructions.
msplit-addresses
-Target Report Mask(SPLIT_ADDRESSES)
-Optimize lui/addiu address loads
+Target Mask(SPLIT_ADDRESSES)
+Optimize lui/addiu address loads.
+
+mmips16e2
+Target Var(TARGET_MIPS16E2) Init(0)
+Enable the MIPS16e V2 instructions.
msym32
-Target Report Var(TARGET_SYM32)
-Assume all symbols have 32-bit values
+Target Var(TARGET_SYM32)
+Assume all symbols have 32-bit values.
+
+msynci
+Target Mask(SYNCI)
+Use synci instruction to invalidate i-cache.
+
+mlra
+Target Var(mips_lra_flag) Init(1) Save
+Use LRA instead of reload.
+
+mlxc1-sxc1
+Target Var(mips_lxc1_sxc1) Init(1)
+Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable.
+
+mmadd4
+Target Var(mips_madd4) Init(1)
+Use 4-operand madd.s/madd.d and related instructions where applicable.
mtune=
-Target RejectNegative Joined
--mtune=PROCESSOR Optimize the output for PROCESSOR
+Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
+-mtune=PROCESSOR Optimize the output for PROCESSOR.
+
+munaligned-access
+Target Var(TARGET_UNALIGNED_ACCESS) Init(1)
+Generate code with unaligned load store, valid for MIPS R6.
muninit-const-in-rodata
-Target Report Var(TARGET_UNINIT_CONST_IN_RODATA)
-Put uninitialized constants in ROM (needs -membedded-data)
+Target Var(TARGET_UNINIT_CONST_IN_RODATA)
+Put uninitialized constants in ROM (needs -membedded-data).
+
+mvirt
+Target Var(TARGET_VIRT)
+Use Virtualization (VZ) instructions.
+
+mxpa
+Target Var(TARGET_XPA)
+Use eXtended Physical Address (XPA) instructions.
+
+mcrc
+Target Var(TARGET_CRC)
+Use Cyclic Redundancy Check (CRC) instructions.
+
+mginv
+Target Var(TARGET_GINV)
+Use Global INValidate (GINV) instructions.
mvr4130-align
-Target Report Mask(VR4130_ALIGN)
-Perform VR4130-specific alignment optimizations
+Target Mask(VR4130_ALIGN)
+Perform VR4130-specific alignment optimizations.
mxgot
-Target Report Var(TARGET_XGOT)
-Lift restrictions on GOT size
+Target Var(TARGET_XGOT)
+Lift restrictions on GOT size.
+
+modd-spreg
+Target Mask(ODD_SPREG)
+Enable use of odd-numbered single-precision registers.
+
+mframe-header-opt
+Target Var(flag_frame_header_optimization) Optimization
+Optimize frame header.
+
+noasmopt
+Driver
+
+mload-store-pairs
+Target Var(TARGET_LOAD_STORE_PAIRS) Init(1)
+Enable load/store bonding.
+
+mcompact-branches=
+Target RejectNegative JoinedOrMissing Var(mips_cb) Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL)
+Specify the compact branch usage policy.
+
+Enum
+Name(mips_cb_setting) Type(enum mips_cb_setting)
+Policies available for use with -mcompact-branches=:
+
+EnumValue
+Enum(mips_cb_setting) String(never) Value(MIPS_CB_NEVER)
+
+EnumValue
+Enum(mips_cb_setting) String(optimal) Value(MIPS_CB_OPTIMAL)
+
+EnumValue
+Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS)
+
+mloongson-mmi
+Target Mask(LOONGSON_MMI)
+Use Loongson MultiMedia extensions Instructions (MMI) instructions.
+
+mloongson-ext
+Target Mask(LOONGSON_EXT)
+Use Loongson EXTension (EXT) instructions.
+
+mloongson-ext2
+Target Var(TARGET_LOONGSON_EXT2)
+Use Loongson EXTension R2 (EXT2) instructions.
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