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Update copyright years.
[thirdparty/gcc.git] / gcc / config / mn10300 / mn10300.md
diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md
index 4a004b60e3f32280771ef2af9bdab2070d6d1e58..939f20d5a58322ab22ca19c894d12d2435878e09 100644 (file)
--- a/gcc/config/mn10300/mn10300.md
+++ b/gcc/config/mn10300/mn10300.md
@@ -1,5 +1,5 @@
 ;; GCC machine description for Matsushita MN10300
-;; Copyright (C) 1996-2013 Free Software Foundation, Inc.
+;; Copyright (C) 1996-2024 Free Software Foundation, Inc.
 ;; Contributed by Jeff Law (law@cygnus.com).
 
 ;; This file is part of GCC.
@@ -592,12 +592,12 @@
 
 ;; Note that ADD IMM,SP does not set the flags, so omit that here.
 (define_insn "*addsi3_flags"
-  [(set (match_operand:SI          0 "register_operand"  "=r,!r")
-       (plus:SI (match_operand:SI 1 "register_operand"  "%0, r")
-                (match_operand:SI 2 "nonmemory_operand" "ri, r")))
-   (set (reg CC_REG)
-       (compare (plus:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (plus:SI (match_operand:SI 1 "register_operand"  "%0, r")
+                         (match_operand:SI 2 "nonmemory_operand" "ri, r"))
+                (const_int 0)))
+   (set (match_operand:SI          0 "register_operand"  "=r,!r")
+       (plus:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
   { return mn10300_output_add (operands, true); }
   [(set_attr "timings" "11,22")]
@@ -605,12 +605,12 @@
 
 ;; A helper to expand the above, with the CC_MODE filled in.
 (define_expand "addsi3_flags"
-  [(parallel [(set (match_operand:SI 0 "register_operand")
-                  (plus:SI (match_operand:SI 1 "register_operand")
-                           (match_operand:SI 2 "nonmemory_operand")))
-             (set (reg:CCZNC CC_REG)
+  [(parallel [(set (reg:CCZNC CC_REG)
                   (compare:CCZNC (plus:SI (match_dup 1) (match_dup 2))
-                                 (const_int 0)))])]
+                                 (const_int 0)))
+             (set (match_operand:SI 0 "register_operand")
+                  (plus:SI (match_operand:SI 1 "register_operand")
+                           (match_operand:SI 2 "nonmemory_operand")))])]
   ""
 )
 
@@ -753,7 +753,6 @@
   rtx scratch = NULL_RTX;
   if (!rtx_equal_p (operands[0], operands[2]))
     {
-      gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1]));
       if (reg_overlap_mentioned_p (operands[0], operands[3])
          || reg_overlap_mentioned_p (operands[0], operands[4]))
        {
@@ -791,12 +790,12 @@
 )
 
 (define_insn "*subsi3_flags"
-  [(set (match_operand:SI           0 "register_operand"  "=r, r")
-       (minus:SI (match_operand:SI 1 "register_operand"   "0, r")
-                 (match_operand:SI 2 "nonmemory_operand"  "ri,r")))
-   (set (reg CC_REG)
-       (compare (minus:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (minus:SI (match_operand:SI 1 "register_operand"  "0, r")
+                          (match_operand:SI 2 "nonmemory_operand" "ri,r"))
+                (const_int 0)))
+   (set (match_operand:SI           0 "register_operand"  "=r, r")
+       (minus:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
   "@
    sub %2,%0
@@ -807,12 +806,12 @@
 
 ;; A helper to expand the above, with the CC_MODE filled in.
 (define_expand "subsi3_flags"
-  [(parallel [(set (match_operand:SI 0 "register_operand")
-                  (minus:SI (match_operand:SI 1 "register_operand")
-                            (match_operand:SI 2 "nonmemory_operand")))
-             (set (reg:CCZNC CC_REG)
+  [(parallel [(set (reg:CCZNC CC_REG)
                   (compare:CCZNC (minus:SI (match_dup 1) (match_dup 2))
-                                 (const_int 0)))])]
+                                 (const_int 0)))
+             (set (match_operand:SI 0 "register_operand")
+                  (minus:SI (match_operand:SI 1 "register_operand")
+                            (match_operand:SI 2 "nonmemory_operand")))])]
   ""
 )
 
@@ -1195,12 +1194,12 @@
 )
 
 (define_insn "*andsi3_flags"
-  [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
-       (and:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
-               (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
-   (set (reg CC_REG)
-       (compare (and:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (and:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
+                        (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
+                (const_int 0)))
+   (set (match_operand:SI         0 "register_operand"  "=D,D,r")
+       (and:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
   "@
    and %2,%0
@@ -1282,12 +1281,12 @@
 )
 
 (define_insn "*iorsi3_flags"
-  [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
-       (ior:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
-               (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
-   (set (reg CC_REG)
-       (compare (ior:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (ior:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
+                        (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
+                (const_int 0)))
+   (set (match_operand:SI         0 "register_operand"  "=D,D,r")
+       (ior:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
   "@
    or %2,%0
@@ -1318,12 +1317,12 @@
 )
 
 (define_insn "*xorsi3_flags"
-  [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
-       (xor:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
-               (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
-   (set (reg CC_REG)
-       (compare (xor:SI (match_dup 1) (match_dup 2))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (xor:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
+                        (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
+                (const_int 0)))
+   (set (match_operand:SI         0 "register_operand"  "=D,D,r")
+       (xor:SI (match_dup 1) (match_dup 2)))]
   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
   "@
    xor %2,%0
@@ -1346,11 +1345,11 @@
 )
 
 (define_insn "*one_cmplsi2_flags"
-  [(set (match_operand:SI         0 "register_operand" "=D")
-       (not:SI (match_operand:SI 1 "register_operand" " 0")))
-   (set (reg CC_REG)
-       (compare (not:SI (match_dup 1))
-                (const_int 0)))]
+  [(set (reg CC_REG)
+       (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
+                (const_int 0)))
+   (set (match_operand:SI         0 "register_operand" "=D")
+       (not:SI (match_dup 1)))]
   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
   "not %0"
 )
@@ -2059,8 +2058,7 @@
 {
   fputs ("\tmovm ", asm_out_file);
   mn10300_print_reg_list (asm_out_file,
-                          mn10300_store_multiple_operation (operands[0],
-                                                           VOIDmode));
+                          mn10300_store_multiple_regs (operands[0]));
   fprintf (asm_out_file, ",(sp)\n");
   return "";
 }
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