;; GCC machine description for Matsushita MN10300
-;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
-;; 2005, 2006, 2007, 2008, 2009, 2010, 2011
-;; Free Software Foundation, Inc.
+;; Copyright (C) 1996-2024 Free Software Foundation, Inc.
;; Contributed by Jeff Law (law@cygnus.com).
;; This file is part of GCC.
;; Note that ADD IMM,SP does not set the flags, so omit that here.
(define_insn "*addsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r,!r")
- (plus:SI (match_operand:SI 1 "register_operand" "%0, r")
- (match_operand:SI 2 "nonmemory_operand" "ri, r")))
- (set (reg CC_REG)
- (compare (plus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (plus:SI (match_operand:SI 1 "register_operand" "%0, r")
+ (match_operand:SI 2 "nonmemory_operand" "ri, r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,!r")
+ (plus:SI (match_dup 1) (match_dup 2)))]
"reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
{ return mn10300_output_add (operands, true); }
[(set_attr "timings" "11,22")]
;; A helper to expand the above, with the CC_MODE filled in.
(define_expand "addsi3_flags"
- [(parallel [(set (match_operand:SI 0 "register_operand")
- (plus:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "nonmemory_operand")))
- (set (reg:CCZNC CC_REG)
+ [(parallel [(set (reg:CCZNC CC_REG)
(compare:CCZNC (plus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))])]
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand")
+ (plus:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "nonmemory_operand")))])]
""
)
rtx scratch = NULL_RTX;
if (!rtx_equal_p (operands[0], operands[2]))
{
- gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1]));
if (reg_overlap_mentioned_p (operands[0], operands[3])
|| reg_overlap_mentioned_p (operands[0], operands[4]))
{
)
(define_insn "*subsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=r, r")
- (minus:SI (match_operand:SI 1 "register_operand" "0, r")
- (match_operand:SI 2 "nonmemory_operand" "ri,r")))
- (set (reg CC_REG)
- (compare (minus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (minus:SI (match_operand:SI 1 "register_operand" "0, r")
+ (match_operand:SI 2 "nonmemory_operand" "ri,r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r, r")
+ (minus:SI (match_dup 1) (match_dup 2)))]
"reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
"@
sub %2,%0
;; A helper to expand the above, with the CC_MODE filled in.
(define_expand "subsi3_flags"
- [(parallel [(set (match_operand:SI 0 "register_operand")
- (minus:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "nonmemory_operand")))
- (set (reg:CCZNC CC_REG)
+ [(parallel [(set (reg:CCZNC CC_REG)
(compare:CCZNC (minus:SI (match_dup 1) (match_dup 2))
- (const_int 0)))])]
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand")
+ (minus:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "nonmemory_operand")))])]
""
)
)
(define_insn "*andsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=D,D,r")
- (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
- (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
- (set (reg CC_REG)
- (compare (and:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=D,D,r")
+ (and:SI (match_dup 1) (match_dup 2)))]
"reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
"@
and %2,%0
)
(define_insn "*iorsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=D,D,r")
- (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
- (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
- (set (reg CC_REG)
- (compare (ior:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=D,D,r")
+ (ior:SI (match_dup 1) (match_dup 2)))]
"reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
"@
or %2,%0
)
(define_insn "*xorsi3_flags"
- [(set (match_operand:SI 0 "register_operand" "=D,D,r")
- (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
- (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
- (set (reg CC_REG)
- (compare (xor:SI (match_dup 1) (match_dup 2))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=D,D,r")
+ (xor:SI (match_dup 1) (match_dup 2)))]
"reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
"@
xor %2,%0
)
(define_insn "*one_cmplsi2_flags"
- [(set (match_operand:SI 0 "register_operand" "=D")
- (not:SI (match_operand:SI 1 "register_operand" " 0")))
- (set (reg CC_REG)
- (compare (not:SI (match_dup 1))
- (const_int 0)))]
+ [(set (reg CC_REG)
+ (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=D")
+ (not:SI (match_dup 1)))]
"reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
"not %0"
)
{
fputs ("\tmovm ", asm_out_file);
mn10300_print_reg_list (asm_out_file,
- mn10300_store_multiple_operation (operands[0],
- VOIDmode));
+ mn10300_store_multiple_regs (operands[0]));
fprintf (asm_out_file, ",(sp)\n");
return "";
}