;; Constraint definitions of Andes NDS32 cpu for GNU compiler
-;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
+;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
;; Contributed by Andes Technology Corporation.
;;
;; This file is part of GCC.
(define_register_constraint "x" "FRAME_POINTER_REG"
"Frame pointer register $fp")
+(define_register_constraint "f"
+ "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) ? FP_REGS : NO_REGS"
+ "The Floating point registers $fs0 ~ $fs31")
+
(define_constraint "Iv00"
"Constant value 0"
(and (match_code "const_int")
(and (match_code "const_int")
(match_test "ival < (1 << 4) && ival >= -(1 << 4)")))
+(define_constraint "Cs05"
+ "Signed immediate 5-bit value"
+ (and (match_code "const_double")
+ (match_test "nds32_const_double_range_ok_p (op, SFmode, -(1 << 4), (1 << 4))")))
+
(define_constraint "Iu05"
"Unsigned immediate 5-bit value"
(and (match_code "const_int")
(and (match_code "const_int")
(match_test "IN_RANGE (ival, -31, 0)")))
+(define_constraint "Iu06"
+ "Unsigned immediate 6-bit value"
+ (and (match_code "const_int")
+ (match_test "ival < (1 << 6) && ival >= 0")))
+
;; Ip05 is special and dedicated for v3 movpi45 instruction.
;; movpi45 has imm5u field but the range is 16 ~ 47.
(define_constraint "Ip05"
&& ival >= (0 + 16)
&& (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
-(define_constraint "Iu06"
+(define_constraint "IU06"
"Unsigned immediate 6-bit value constraint for addri36.sp instruction"
(and (match_code "const_int")
- (match_test "ival < (1 << 6)
+ (match_test "ival < (1 << 8)
&& ival >= 0
&& (ival % 4 == 0)
&& (TARGET_ISA_V3 || TARGET_ISA_V3M)")))
(and (match_code "const_int")
(match_test "ival < (1 << 19) && ival >= -(1 << 19)")))
+(define_constraint "Cs20"
+ "Signed immediate 20-bit value"
+ (and (match_code "const_double")
+ (match_test "nds32_const_double_range_ok_p (op, SFmode, -(1 << 19), (1 << 19))")))
(define_constraint "Ihig"
"The immediate value that can be simply set high 20-bit"
(and (match_code "const_int")
(match_test "(ival != 0) && ((ival & 0xfff) == 0)")))
+(define_constraint "Chig"
+ "The immediate value that can be simply set high 20-bit"
+ (and (match_code "high")
+ (match_test "GET_CODE (XEXP (op, 0)) == CONST_DOUBLE")))
+
(define_constraint "Izeb"
"The immediate value 0xff"
(and (match_code "const_int")
(match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
&& (IN_RANGE (exact_log2 (ival + 1), 1, 8))")))
+(define_constraint "CVp5"
+ "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
+ (and (match_code "const_vector")
+ (match_test "nds32_valid_CVp5_p (op)")))
+
+(define_constraint "CVs5"
+ "Signed immediate 5-bit value"
+ (and (match_code "const_vector")
+ (match_test "nds32_valid_CVs5_p (op)")))
+
+(define_constraint "CVs2"
+ "Signed immediate 20-bit value"
+ (and (match_code "const_vector")
+ (match_test "nds32_valid_CVs2_p (op)")))
+
+(define_constraint "CVhi"
+ "The immediate value that can be simply set high 20-bit"
+ (and (match_code "const_vector")
+ (match_test "nds32_valid_CVhi_p (op)")))
(define_memory_constraint "U33"
"Memory constraint for 333 format"
(and (match_code "mem")
- (match_test "nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U")))
+ (match_test "nds32_mem_format (op) == ADDRESS_POST_INC_LO_REG_IMM3U
+ || nds32_mem_format (op) == ADDRESS_POST_MODIFY_LO_REG_IMM3U
+ || nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U")))
(define_memory_constraint "U45"
"Memory constraint for 45 format"
(and (match_code "mem")
(match_test "(nds32_mem_format (op) == ADDRESS_REG)
- && (GET_MODE (op) == SImode)")))
+ && ((GET_MODE (op) == SImode)
+ || (GET_MODE (op) == SFmode))")))
(define_memory_constraint "Ufe"
"Memory constraint for fe format"
(and (match_code "mem")
(match_test "nds32_mem_format (op) == ADDRESS_R8_IMM7U
- && (GET_MODE (op) == SImode)")))
+ && (GET_MODE (op) == SImode
+ || GET_MODE (op) == SFmode)")))
(define_memory_constraint "U37"
"Memory constraint for 37 format"
(and (match_code "mem")
(match_test "(nds32_mem_format (op) == ADDRESS_SP_IMM7U
|| nds32_mem_format (op) == ADDRESS_FP_IMM7U)
- && (GET_MODE (op) == SImode)")))
-
+ && (GET_MODE (op) == SImode
+ || GET_MODE (op) == SFmode)")))
(define_memory_constraint "Umw"
"Memory constraint for lwm/smw"
(and (match_code "mem")
(match_test "nds32_valid_smw_lwm_base_p (op)")))
+(define_memory_constraint "Da"
+ "Memory constraint for non-offset loads/stores"
+ (and (match_code "mem")
+ (match_test "REG_P (XEXP (op, 0))
+ || (GET_CODE (XEXP (op, 0)) == POST_INC)")))
+
+(define_memory_constraint "Q"
+ "Memory constraint for no symbol_ref and const"
+ (and (match_code "mem")
+ (match_test "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
+ && nds32_float_mem_operand_p (op)")))
+
+(define_constraint "S"
+ "@internal
+ A constant call address."
+ (match_operand 0 "nds32_symbolic_operand"))
+
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