/* Definitions of target machine of Andes NDS32 cpu for GNU compiler
- Copyright (C) 2012-2018 Free Software Foundation, Inc.
+ Copyright (C) 2012-2024 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
/* ------------------------------------------------------------------------ */
/* The following are auxiliary macros or structure declarations
- that are used all over the nds32.c and nds32.h. */
+ that are used all over the nds32.cc and nds32.h. */
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
(LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
#define NDS32_SYMBOL_REF_RODATA_P(x) \
((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
+enum nds32_relax_insn_type
+{
+ RELAX_ORI,
+ RELAX_PLT_ADD,
+ RELAX_TLS_ADD_or_LW,
+ RELAX_TLS_ADD_LW,
+ RELAX_TLS_LW_JRAL,
+ RELAX_DONE
+};
+
/* Classifies expand result for expand helper function. */
enum nds32_expand_result_type
{
EXPAND_CREATE_TEMPLATE
};
-/* Check instruction LS-37-FP-implied form.
- Note: actually its immediate range is imm9u
- since it is used for lwi37/swi37 instructions. */
-#define NDS32_LS_37_FP_P(rt, ra, imm) \
- (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
- && REGNO (ra) == FP_REGNUM \
- && satisfies_constraint_Iu09 (imm))
-
-/* Check instruction LS-37-SP-implied form.
- Note: actually its immediate range is imm9u
- since it is used for lwi37/swi37 instructions. */
-#define NDS32_LS_37_SP_P(rt, ra, imm) \
- (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
- && REGNO (ra) == SP_REGNUM \
- && satisfies_constraint_Iu09 (imm))
-
-
-/* Check load/store instruction form : Rt3, Ra3, imm3u. */
-#define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
-
-/* Check load/store instruction form : Rt4, Ra5, const_int_0.
- Note: no need to check ra because Ra5 means it covers all registers. */
-#define NDS32_LS_450_P(rt, ra, imm) \
- ((imm == const0_rtx) \
- && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
- || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
-
-/* Check instruction RRI-333-form. */
-#define NDS32_RRI_333_P(rt, ra, imm) \
- (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
- && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
- && satisfies_constraint_Iu03 (imm))
-
-/* Check instruction RI-45-form. */
-#define NDS32_RI_45_P(rt, ra, imm) \
- (REGNO (rt) == REGNO (ra) \
- && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
- || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
- && satisfies_constraint_Iu05 (imm))
-
-
-/* Check instruction RR-33-form. */
-#define NDS32_RR_33_P(rt, ra) \
- (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
- && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
-
-/* Check instruction RRR-333-form. */
-#define NDS32_RRR_333_P(rt, ra, rb) \
- (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
- && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
- && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
-
-/* Check instruction RR-45-form.
- Note: no need to check rb because Rb5 means it covers all registers. */
-#define NDS32_RR_45_P(rt, ra, rb) \
- (REGNO (rt) == REGNO (ra) \
- && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
- || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
-
/* Classifies address type to distinguish 16-bit/32-bit format. */
enum nds32_16bit_address_type
{
#define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
#define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
+/* Determine whether we would like to have code generation strictly aligned.
+ We set it strictly aligned when -malways-align is enabled.
+ Check gcc/common/config/nds32/nds32-common.cc for the optimizations that
+ apply -malways-align. */
+#define NDS32_ALIGN_P() (TARGET_ALWAYS_ALIGN)
+
+#define NDS32_EXT_DSP_P() (TARGET_EXT_DSP && !TARGET_FORCE_NO_EXT_DSP)
+
/* Get alignment according to mode or type information.
When 'type' is nonnull, there is no need to look at 'mode'. */
#define NDS32_MODE_TYPE_ALIGN(mode, type) \
As long as the register satisfies both criteria above,
it is required to be saved. */
#define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \
- ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
+ (!call_used_or_fixed_reg_p (regno) && df_regs_ever_live_p (regno))
/* This macro is to check if the push25/pop25 are available to be used
for code generation. Because pop25 also performs return behavior,
/* The last required register that should be saved on stack for va_args. */
int va_args_last_regno;
+ /* Number of bytes on the stack for saving exception handling registers. */
+ int eh_return_data_regs_size;
+ /* The first register of passing exception handling information. */
+ int eh_return_data_first_regno;
+ /* The last register of passing exception handling information. */
+ int eh_return_data_last_regno;
+
+ /* Indicate that whether this function
+ calls __builtin_eh_return. */
+ int use_eh_return_p;
+
/* Indicate that whether this function needs
prologue/epilogue code generation. */
int naked_p;
/* Indicate that whether this function
uses fp_as_gp optimization. */
int fp_as_gp_p;
+ /* Indicate that whether this function is under strictly aligned
+ situation for legitimate address checking. This flag informs
+ nds32_legitimate_address_p() how to treat offset alignment:
+ 1. The IVOPT phase needs to detect available range for memory access,
+ such as checking [base + 32767] ~ [base + (-32768)].
+ For this case we do not want address to be strictly aligned.
+ 2. The rtl lowering and optimization are close to target code.
+ For this case we need address to be strictly aligned. */
+ int strict_aligned_p;
+
+ /* Record two similar attributes status. */
+ int attr_naked_p;
+ int attr_no_prologue_p;
};
/* A C structure that contains the arguments information. */
0 for reset handler,
1-8 for exception handler,
and 9-72 for interrupt handler.
- We use an array, which is defined in nds32.c, to record
+ We use an array, which is defined in nds32.cc, to record
essential information for each vector. */
#define NDS32_N_ISR_VECTORS 73
{
NDS32_NESTED,
NDS32_NOT_NESTED,
- NDS32_NESTED_READY
+ NDS32_NESTED_READY,
+ NDS32_CRITICAL
};
/* Define structure to record isr information.
The isr vector array 'isr_vectors[]' with this structure
- is defined in nds32.c. */
+ is defined in nds32.cc. */
struct nds32_isr_info
{
/* The field to identify isr category.
unless user specifies attribute to change it. */
enum nds32_isr_nested_type nested_type;
+ /* Secure isr level.
+ Currently we have 0-3 security level.
+ It should be set to 0 by default.
+ For security processors, this is determined by secure
+ attribute or compiler options. */
+ unsigned int security_level;
+
/* Total vectors.
The total vectors = interrupt + exception numbers + reset.
It should be set to 0 by default.
{
NDS32_BUILTIN_ISYNC,
NDS32_BUILTIN_ISB,
+ NDS32_BUILTIN_DSB,
+ NDS32_BUILTIN_MSYNC_ALL,
+ NDS32_BUILTIN_MSYNC_STORE,
NDS32_BUILTIN_MFSR,
NDS32_BUILTIN_MFUSR,
NDS32_BUILTIN_MTSR,
+ NDS32_BUILTIN_MTSR_ISB,
+ NDS32_BUILTIN_MTSR_DSB,
NDS32_BUILTIN_MTUSR,
NDS32_BUILTIN_SETGIE_EN,
NDS32_BUILTIN_SETGIE_DIS,
NDS32_BUILTIN_FCPYSS,
NDS32_BUILTIN_FCPYNSD,
NDS32_BUILTIN_FCPYSD,
+ NDS32_BUILTIN_ABS,
+ NDS32_BUILTIN_AVE,
+ NDS32_BUILTIN_BCLR,
+ NDS32_BUILTIN_BSET,
+ NDS32_BUILTIN_BTGL,
+ NDS32_BUILTIN_BTST,
+ NDS32_BUILTIN_CLIP,
+ NDS32_BUILTIN_CLIPS,
+ NDS32_BUILTIN_CLZ,
+ NDS32_BUILTIN_CLO,
+ NDS32_BUILTIN_MAX,
+ NDS32_BUILTIN_MIN,
+ NDS32_BUILTIN_PBSAD,
+ NDS32_BUILTIN_PBSADA,
+ NDS32_BUILTIN_BSE,
+ NDS32_BUILTIN_BSP,
NDS32_BUILTIN_FFB,
NDS32_BUILTIN_FFMISM,
NDS32_BUILTIN_FLMISM,
+ NDS32_BUILTIN_KADDW,
+ NDS32_BUILTIN_KSUBW,
+ NDS32_BUILTIN_KADDH,
+ NDS32_BUILTIN_KSUBH,
+ NDS32_BUILTIN_KDMBB,
+ NDS32_BUILTIN_V_KDMBB,
+ NDS32_BUILTIN_KDMBT,
+ NDS32_BUILTIN_V_KDMBT,
+ NDS32_BUILTIN_KDMTB,
+ NDS32_BUILTIN_V_KDMTB,
+ NDS32_BUILTIN_KDMTT,
+ NDS32_BUILTIN_V_KDMTT,
+ NDS32_BUILTIN_KHMBB,
+ NDS32_BUILTIN_V_KHMBB,
+ NDS32_BUILTIN_KHMBT,
+ NDS32_BUILTIN_V_KHMBT,
+ NDS32_BUILTIN_KHMTB,
+ NDS32_BUILTIN_V_KHMTB,
+ NDS32_BUILTIN_KHMTT,
+ NDS32_BUILTIN_V_KHMTT,
+ NDS32_BUILTIN_KSLRAW,
+ NDS32_BUILTIN_KSLRAW_U,
+ NDS32_BUILTIN_RDOV,
+ NDS32_BUILTIN_CLROV,
+ NDS32_BUILTIN_ROTR,
+ NDS32_BUILTIN_SVA,
+ NDS32_BUILTIN_SVS,
+ NDS32_BUILTIN_WSBH,
+ NDS32_BUILTIN_JR_ITOFF,
+ NDS32_BUILTIN_JR_TOFF,
+ NDS32_BUILTIN_JRAL_ITON,
+ NDS32_BUILTIN_JRAL_TON,
+ NDS32_BUILTIN_RET_ITOFF,
+ NDS32_BUILTIN_RET_TOFF,
+ NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT,
+ NDS32_BUILTIN_STANDBY_WAKE_GRANT,
+ NDS32_BUILTIN_STANDBY_WAKE_DONE,
+ NDS32_BUILTIN_TEQZ,
+ NDS32_BUILTIN_TNEZ,
+ NDS32_BUILTIN_TRAP,
+ NDS32_BUILTIN_SETEND_BIG,
+ NDS32_BUILTIN_SETEND_LITTLE,
+ NDS32_BUILTIN_SYSCALL,
+ NDS32_BUILTIN_BREAK,
+ NDS32_BUILTIN_NOP,
+ NDS32_BUILTIN_SCHE_BARRIER,
+ NDS32_BUILTIN_GET_CURRENT_SP,
+ NDS32_BUILTIN_SET_CURRENT_SP,
+ NDS32_BUILTIN_RETURN_ADDRESS,
+ NDS32_BUILTIN_LLW,
+ NDS32_BUILTIN_LWUP,
+ NDS32_BUILTIN_LBUP,
+ NDS32_BUILTIN_SCW,
+ NDS32_BUILTIN_SWUP,
+ NDS32_BUILTIN_SBUP,
NDS32_BUILTIN_CCTL_VA_LCK,
NDS32_BUILTIN_CCTL_IDX_WBINVAL,
NDS32_BUILTIN_CCTL_VA_WBINVAL_L1,
NDS32_BUILTIN_CCTL_L1D_INVALALL,
NDS32_BUILTIN_CCTL_L1D_WBALL_ALVL,
NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL,
+ NDS32_BUILTIN_DPREF_QW,
+ NDS32_BUILTIN_DPREF_HW,
+ NDS32_BUILTIN_DPREF_W,
+ NDS32_BUILTIN_DPREF_DW,
+ NDS32_BUILTIN_TLBOP_TRD,
+ NDS32_BUILTIN_TLBOP_TWR,
+ NDS32_BUILTIN_TLBOP_RWR,
+ NDS32_BUILTIN_TLBOP_RWLK,
+ NDS32_BUILTIN_TLBOP_UNLK,
+ NDS32_BUILTIN_TLBOP_PB,
+ NDS32_BUILTIN_TLBOP_INV,
+ NDS32_BUILTIN_TLBOP_FLUA,
NDS32_BUILTIN_UALOAD_HW,
NDS32_BUILTIN_UALOAD_W,
NDS32_BUILTIN_UALOAD_DW,
NDS32_BUILTIN_UASTORE_HW,
NDS32_BUILTIN_UASTORE_W,
NDS32_BUILTIN_UASTORE_DW,
+ NDS32_BUILTIN_GIE_DIS,
+ NDS32_BUILTIN_GIE_EN,
+ NDS32_BUILTIN_ENABLE_INT,
+ NDS32_BUILTIN_DISABLE_INT,
+ NDS32_BUILTIN_SET_PENDING_SWINT,
+ NDS32_BUILTIN_CLR_PENDING_SWINT,
+ NDS32_BUILTIN_CLR_PENDING_HWINT,
+ NDS32_BUILTIN_GET_ALL_PENDING_INT,
+ NDS32_BUILTIN_GET_PENDING_INT,
+ NDS32_BUILTIN_SET_INT_PRIORITY,
+ NDS32_BUILTIN_GET_INT_PRIORITY,
+ NDS32_BUILTIN_SET_TRIG_LEVEL,
+ NDS32_BUILTIN_SET_TRIG_EDGE,
+ NDS32_BUILTIN_GET_TRIG_TYPE,
+ NDS32_BUILTIN_DSP_BEGIN,
+ NDS32_BUILTIN_ADD16,
+ NDS32_BUILTIN_V_UADD16,
+ NDS32_BUILTIN_V_SADD16,
+ NDS32_BUILTIN_RADD16,
+ NDS32_BUILTIN_V_RADD16,
+ NDS32_BUILTIN_URADD16,
+ NDS32_BUILTIN_V_URADD16,
+ NDS32_BUILTIN_KADD16,
+ NDS32_BUILTIN_V_KADD16,
+ NDS32_BUILTIN_UKADD16,
+ NDS32_BUILTIN_V_UKADD16,
+ NDS32_BUILTIN_SUB16,
+ NDS32_BUILTIN_V_USUB16,
+ NDS32_BUILTIN_V_SSUB16,
+ NDS32_BUILTIN_RSUB16,
+ NDS32_BUILTIN_V_RSUB16,
+ NDS32_BUILTIN_URSUB16,
+ NDS32_BUILTIN_V_URSUB16,
+ NDS32_BUILTIN_KSUB16,
+ NDS32_BUILTIN_V_KSUB16,
+ NDS32_BUILTIN_UKSUB16,
+ NDS32_BUILTIN_V_UKSUB16,
+ NDS32_BUILTIN_CRAS16,
+ NDS32_BUILTIN_V_UCRAS16,
+ NDS32_BUILTIN_V_SCRAS16,
+ NDS32_BUILTIN_RCRAS16,
+ NDS32_BUILTIN_V_RCRAS16,
+ NDS32_BUILTIN_URCRAS16,
+ NDS32_BUILTIN_V_URCRAS16,
+ NDS32_BUILTIN_KCRAS16,
+ NDS32_BUILTIN_V_KCRAS16,
+ NDS32_BUILTIN_UKCRAS16,
+ NDS32_BUILTIN_V_UKCRAS16,
+ NDS32_BUILTIN_CRSA16,
+ NDS32_BUILTIN_V_UCRSA16,
+ NDS32_BUILTIN_V_SCRSA16,
+ NDS32_BUILTIN_RCRSA16,
+ NDS32_BUILTIN_V_RCRSA16,
+ NDS32_BUILTIN_URCRSA16,
+ NDS32_BUILTIN_V_URCRSA16,
+ NDS32_BUILTIN_KCRSA16,
+ NDS32_BUILTIN_V_KCRSA16,
+ NDS32_BUILTIN_UKCRSA16,
+ NDS32_BUILTIN_V_UKCRSA16,
+ NDS32_BUILTIN_ADD8,
+ NDS32_BUILTIN_V_UADD8,
+ NDS32_BUILTIN_V_SADD8,
+ NDS32_BUILTIN_RADD8,
+ NDS32_BUILTIN_V_RADD8,
+ NDS32_BUILTIN_URADD8,
+ NDS32_BUILTIN_V_URADD8,
+ NDS32_BUILTIN_KADD8,
+ NDS32_BUILTIN_V_KADD8,
+ NDS32_BUILTIN_UKADD8,
+ NDS32_BUILTIN_V_UKADD8,
+ NDS32_BUILTIN_SUB8,
+ NDS32_BUILTIN_V_USUB8,
+ NDS32_BUILTIN_V_SSUB8,
+ NDS32_BUILTIN_RSUB8,
+ NDS32_BUILTIN_V_RSUB8,
+ NDS32_BUILTIN_URSUB8,
+ NDS32_BUILTIN_V_URSUB8,
+ NDS32_BUILTIN_KSUB8,
+ NDS32_BUILTIN_V_KSUB8,
+ NDS32_BUILTIN_UKSUB8,
+ NDS32_BUILTIN_V_UKSUB8,
+ NDS32_BUILTIN_SRA16,
+ NDS32_BUILTIN_V_SRA16,
+ NDS32_BUILTIN_SRA16_U,
+ NDS32_BUILTIN_V_SRA16_U,
+ NDS32_BUILTIN_SRL16,
+ NDS32_BUILTIN_V_SRL16,
+ NDS32_BUILTIN_SRL16_U,
+ NDS32_BUILTIN_V_SRL16_U,
+ NDS32_BUILTIN_SLL16,
+ NDS32_BUILTIN_V_SLL16,
+ NDS32_BUILTIN_KSLL16,
+ NDS32_BUILTIN_V_KSLL16,
+ NDS32_BUILTIN_KSLRA16,
+ NDS32_BUILTIN_V_KSLRA16,
+ NDS32_BUILTIN_KSLRA16_U,
+ NDS32_BUILTIN_V_KSLRA16_U,
+ NDS32_BUILTIN_CMPEQ16,
+ NDS32_BUILTIN_V_SCMPEQ16,
+ NDS32_BUILTIN_V_UCMPEQ16,
+ NDS32_BUILTIN_SCMPLT16,
+ NDS32_BUILTIN_V_SCMPLT16,
+ NDS32_BUILTIN_SCMPLE16,
+ NDS32_BUILTIN_V_SCMPLE16,
+ NDS32_BUILTIN_UCMPLT16,
+ NDS32_BUILTIN_V_UCMPLT16,
+ NDS32_BUILTIN_UCMPLE16,
+ NDS32_BUILTIN_V_UCMPLE16,
+ NDS32_BUILTIN_CMPEQ8,
+ NDS32_BUILTIN_V_SCMPEQ8,
+ NDS32_BUILTIN_V_UCMPEQ8,
+ NDS32_BUILTIN_SCMPLT8,
+ NDS32_BUILTIN_V_SCMPLT8,
+ NDS32_BUILTIN_SCMPLE8,
+ NDS32_BUILTIN_V_SCMPLE8,
+ NDS32_BUILTIN_UCMPLT8,
+ NDS32_BUILTIN_V_UCMPLT8,
+ NDS32_BUILTIN_UCMPLE8,
+ NDS32_BUILTIN_V_UCMPLE8,
+ NDS32_BUILTIN_SMIN16,
+ NDS32_BUILTIN_V_SMIN16,
+ NDS32_BUILTIN_UMIN16,
+ NDS32_BUILTIN_V_UMIN16,
+ NDS32_BUILTIN_SMAX16,
+ NDS32_BUILTIN_V_SMAX16,
+ NDS32_BUILTIN_UMAX16,
+ NDS32_BUILTIN_V_UMAX16,
+ NDS32_BUILTIN_SCLIP16,
+ NDS32_BUILTIN_V_SCLIP16,
+ NDS32_BUILTIN_UCLIP16,
+ NDS32_BUILTIN_V_UCLIP16,
+ NDS32_BUILTIN_KHM16,
+ NDS32_BUILTIN_V_KHM16,
+ NDS32_BUILTIN_KHMX16,
+ NDS32_BUILTIN_V_KHMX16,
+ NDS32_BUILTIN_KABS16,
+ NDS32_BUILTIN_V_KABS16,
+ NDS32_BUILTIN_SMIN8,
+ NDS32_BUILTIN_V_SMIN8,
+ NDS32_BUILTIN_UMIN8,
+ NDS32_BUILTIN_V_UMIN8,
+ NDS32_BUILTIN_SMAX8,
+ NDS32_BUILTIN_V_SMAX8,
+ NDS32_BUILTIN_UMAX8,
+ NDS32_BUILTIN_V_UMAX8,
+ NDS32_BUILTIN_KABS8,
+ NDS32_BUILTIN_V_KABS8,
+ NDS32_BUILTIN_SUNPKD810,
+ NDS32_BUILTIN_V_SUNPKD810,
+ NDS32_BUILTIN_SUNPKD820,
+ NDS32_BUILTIN_V_SUNPKD820,
+ NDS32_BUILTIN_SUNPKD830,
+ NDS32_BUILTIN_V_SUNPKD830,
+ NDS32_BUILTIN_SUNPKD831,
+ NDS32_BUILTIN_V_SUNPKD831,
+ NDS32_BUILTIN_ZUNPKD810,
+ NDS32_BUILTIN_V_ZUNPKD810,
+ NDS32_BUILTIN_ZUNPKD820,
+ NDS32_BUILTIN_V_ZUNPKD820,
+ NDS32_BUILTIN_ZUNPKD830,
+ NDS32_BUILTIN_V_ZUNPKD830,
+ NDS32_BUILTIN_ZUNPKD831,
+ NDS32_BUILTIN_V_ZUNPKD831,
+ NDS32_BUILTIN_RADDW,
+ NDS32_BUILTIN_URADDW,
+ NDS32_BUILTIN_RSUBW,
+ NDS32_BUILTIN_URSUBW,
+ NDS32_BUILTIN_SRA_U,
+ NDS32_BUILTIN_KSLL,
+ NDS32_BUILTIN_PKBB16,
+ NDS32_BUILTIN_V_PKBB16,
+ NDS32_BUILTIN_PKBT16,
+ NDS32_BUILTIN_V_PKBT16,
+ NDS32_BUILTIN_PKTB16,
+ NDS32_BUILTIN_V_PKTB16,
+ NDS32_BUILTIN_PKTT16,
+ NDS32_BUILTIN_V_PKTT16,
+ NDS32_BUILTIN_SMMUL,
+ NDS32_BUILTIN_SMMUL_U,
+ NDS32_BUILTIN_KMMAC,
+ NDS32_BUILTIN_KMMAC_U,
+ NDS32_BUILTIN_KMMSB,
+ NDS32_BUILTIN_KMMSB_U,
+ NDS32_BUILTIN_KWMMUL,
+ NDS32_BUILTIN_KWMMUL_U,
+ NDS32_BUILTIN_SMMWB,
+ NDS32_BUILTIN_V_SMMWB,
+ NDS32_BUILTIN_SMMWB_U,
+ NDS32_BUILTIN_V_SMMWB_U,
+ NDS32_BUILTIN_SMMWT,
+ NDS32_BUILTIN_V_SMMWT,
+ NDS32_BUILTIN_SMMWT_U,
+ NDS32_BUILTIN_V_SMMWT_U,
+ NDS32_BUILTIN_KMMAWB,
+ NDS32_BUILTIN_V_KMMAWB,
+ NDS32_BUILTIN_KMMAWB_U,
+ NDS32_BUILTIN_V_KMMAWB_U,
+ NDS32_BUILTIN_KMMAWT,
+ NDS32_BUILTIN_V_KMMAWT,
+ NDS32_BUILTIN_KMMAWT_U,
+ NDS32_BUILTIN_V_KMMAWT_U,
+ NDS32_BUILTIN_SMBB,
+ NDS32_BUILTIN_V_SMBB,
+ NDS32_BUILTIN_SMBT,
+ NDS32_BUILTIN_V_SMBT,
+ NDS32_BUILTIN_SMTT,
+ NDS32_BUILTIN_V_SMTT,
+ NDS32_BUILTIN_KMDA,
+ NDS32_BUILTIN_V_KMDA,
+ NDS32_BUILTIN_KMXDA,
+ NDS32_BUILTIN_V_KMXDA,
+ NDS32_BUILTIN_SMDS,
+ NDS32_BUILTIN_V_SMDS,
+ NDS32_BUILTIN_SMDRS,
+ NDS32_BUILTIN_V_SMDRS,
+ NDS32_BUILTIN_SMXDS,
+ NDS32_BUILTIN_V_SMXDS,
+ NDS32_BUILTIN_KMABB,
+ NDS32_BUILTIN_V_KMABB,
+ NDS32_BUILTIN_KMABT,
+ NDS32_BUILTIN_V_KMABT,
+ NDS32_BUILTIN_KMATT,
+ NDS32_BUILTIN_V_KMATT,
+ NDS32_BUILTIN_KMADA,
+ NDS32_BUILTIN_V_KMADA,
+ NDS32_BUILTIN_KMAXDA,
+ NDS32_BUILTIN_V_KMAXDA,
+ NDS32_BUILTIN_KMADS,
+ NDS32_BUILTIN_V_KMADS,
+ NDS32_BUILTIN_KMADRS,
+ NDS32_BUILTIN_V_KMADRS,
+ NDS32_BUILTIN_KMAXDS,
+ NDS32_BUILTIN_V_KMAXDS,
+ NDS32_BUILTIN_KMSDA,
+ NDS32_BUILTIN_V_KMSDA,
+ NDS32_BUILTIN_KMSXDA,
+ NDS32_BUILTIN_V_KMSXDA,
+ NDS32_BUILTIN_SMAL,
+ NDS32_BUILTIN_V_SMAL,
+ NDS32_BUILTIN_BITREV,
+ NDS32_BUILTIN_WEXT,
+ NDS32_BUILTIN_BPICK,
+ NDS32_BUILTIN_INSB,
+ NDS32_BUILTIN_SADD64,
+ NDS32_BUILTIN_UADD64,
+ NDS32_BUILTIN_RADD64,
+ NDS32_BUILTIN_URADD64,
+ NDS32_BUILTIN_KADD64,
+ NDS32_BUILTIN_UKADD64,
+ NDS32_BUILTIN_SSUB64,
+ NDS32_BUILTIN_USUB64,
+ NDS32_BUILTIN_RSUB64,
+ NDS32_BUILTIN_URSUB64,
+ NDS32_BUILTIN_KSUB64,
+ NDS32_BUILTIN_UKSUB64,
+ NDS32_BUILTIN_SMAR64,
+ NDS32_BUILTIN_SMSR64,
+ NDS32_BUILTIN_UMAR64,
+ NDS32_BUILTIN_UMSR64,
+ NDS32_BUILTIN_KMAR64,
+ NDS32_BUILTIN_KMSR64,
+ NDS32_BUILTIN_UKMAR64,
+ NDS32_BUILTIN_UKMSR64,
+ NDS32_BUILTIN_SMALBB,
+ NDS32_BUILTIN_V_SMALBB,
+ NDS32_BUILTIN_SMALBT,
+ NDS32_BUILTIN_V_SMALBT,
+ NDS32_BUILTIN_SMALTT,
+ NDS32_BUILTIN_V_SMALTT,
+ NDS32_BUILTIN_SMALDA,
+ NDS32_BUILTIN_V_SMALDA,
+ NDS32_BUILTIN_SMALXDA,
+ NDS32_BUILTIN_V_SMALXDA,
+ NDS32_BUILTIN_SMALDS,
+ NDS32_BUILTIN_V_SMALDS,
+ NDS32_BUILTIN_SMALDRS,
+ NDS32_BUILTIN_V_SMALDRS,
+ NDS32_BUILTIN_SMALXDS,
+ NDS32_BUILTIN_V_SMALXDS,
+ NDS32_BUILTIN_SMUL16,
+ NDS32_BUILTIN_V_SMUL16,
+ NDS32_BUILTIN_SMULX16,
+ NDS32_BUILTIN_V_SMULX16,
+ NDS32_BUILTIN_UMUL16,
+ NDS32_BUILTIN_V_UMUL16,
+ NDS32_BUILTIN_UMULX16,
+ NDS32_BUILTIN_V_UMULX16,
+ NDS32_BUILTIN_SMSLDA,
+ NDS32_BUILTIN_V_SMSLDA,
+ NDS32_BUILTIN_SMSLXDA,
+ NDS32_BUILTIN_V_SMSLXDA,
+ NDS32_BUILTIN_UCLIP32,
+ NDS32_BUILTIN_SCLIP32,
+ NDS32_BUILTIN_KABS,
+ NDS32_BUILTIN_UALOAD_U16,
+ NDS32_BUILTIN_UALOAD_S16,
+ NDS32_BUILTIN_UALOAD_U8,
+ NDS32_BUILTIN_UALOAD_S8,
+ NDS32_BUILTIN_UASTORE_U16,
+ NDS32_BUILTIN_UASTORE_S16,
+ NDS32_BUILTIN_UASTORE_U8,
+ NDS32_BUILTIN_UASTORE_S8,
+ NDS32_BUILTIN_DSP_END,
+ NDS32_BUILTIN_UNALIGNED_FEATURE,
+ NDS32_BUILTIN_ENABLE_UNALIGNED,
+ NDS32_BUILTIN_DISABLE_UNALIGNED,
NDS32_BUILTIN_COUNT
};
/* ------------------------------------------------------------------------ */
-#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
+#define TARGET_ISR_VECTOR_SIZE_4_BYTE \
+ (nds32_isr_vector_size == 4)
+#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
#define TARGET_ISA_V3 \
(nds32_arch_option == ARCH_V3 \
+ || nds32_arch_option == ARCH_V3J \
|| nds32_arch_option == ARCH_V3F \
|| nds32_arch_option == ARCH_V3S)
#define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M)
+#define TARGET_PIPELINE_N7 \
+ (nds32_cpu_option == CPU_N7)
+#define TARGET_PIPELINE_N8 \
+ (nds32_cpu_option == CPU_N6 \
+ || nds32_cpu_option == CPU_N8)
+#define TARGET_PIPELINE_N9 \
+ (nds32_cpu_option == CPU_N9)
+#define TARGET_PIPELINE_N10 \
+ (nds32_cpu_option == CPU_N10)
+#define TARGET_PIPELINE_N13 \
+ (nds32_cpu_option == CPU_N12 || nds32_cpu_option == CPU_N13)
+#define TARGET_PIPELINE_GRAYWOLF \
+ (nds32_cpu_option == CPU_GRAYWOLF)
+#define TARGET_PIPELINE_SIMPLE \
+ (nds32_cpu_option == CPU_SIMPLE)
+
#define TARGET_CMODEL_SMALL \
(nds32_cmodel_option == CMODEL_SMALL)
#define TARGET_CMODEL_MEDIUM \
#define TARGET_CMODEL_LARGE \
(nds32_cmodel_option == CMODEL_LARGE)
+#define TARGET_ICT_MODEL_SMALL \
+ (nds32_ict_model == ICT_MODEL_SMALL)
+
+#define TARGET_ICT_MODEL_LARGE \
+ (nds32_ict_model == ICT_MODEL_LARGE)
+
/* When -mcmodel=small or -mcmodel=medium,
compiler may generate gp-base instruction directly. */
#define TARGET_GP_DIRECT \
(nds32_cmodel_option == CMODEL_SMALL\
|| nds32_cmodel_option == CMODEL_MEDIUM)
+#define TARGET_MUL_SLOW \
+ (nds32_mul_config == MUL_TYPE_SLOW)
/* Run-time Target Specification. */
#define TARGET_SOFT_FLOAT (nds32_abi == NDS32_ABI_V2)
#endif
#define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2
+
+/* ------------------------------------------------------------------------ */
+
+#ifdef TARGET_DEFAULT_RELAX
+# define NDS32_RELAX_SPEC " %{!mno-relax:--relax}"
+#else
+# define NDS32_RELAX_SPEC " %{mrelax:--relax}"
+#endif
+
+#ifdef TARGET_DEFAULT_EXT_DSP
+# define NDS32_EXT_DSP_SPEC " %{!mno-ext-dsp:-mext-dsp}"
+#else
+# define NDS32_EXT_DSP_SPEC ""
+#endif
+
/* ------------------------------------------------------------------------ */
\f
/* Controlling the Compilation Driver. */
" %{!mno-ext-fpu-dp:%{!mext-fpu-dp:-mext-fpu-dp}}}" \
" %{march=v3s:%{!mfloat-abi=*:-mfloat-abi=hard}" \
" %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}}" }, \
+ {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
{"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }
#define CC1_SPEC \
- ""
+ NDS32_EXT_DSP_SPEC
#define ASM_SPEC \
" %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
" %{march=*:-march=%*}" \
+ " %{mno-16-bit|mno-16bit:-mno-16bit-ext}" \
+ " %{march=v3m:%{!mfull-regs:%{!mreduced-regs:-mreduced-regs}}}" \
+ " %{mfull-regs:-mno-reduced-regs}" \
+ " %{mreduced-regs:-mreduced-regs}" \
" %{mabi=*:-mabi=v%*}" \
" %{mconfig-fpu=*:-mfpu-freg=%*}" \
" %{mext-fpu-mac:-mmac}" \
" %{mext-fpu-sp:-mfpu-sp-ext}" \
" %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \
" %{mext-fpu-dp:-mfpu-dp-ext}" \
- " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}"
-
-/* If user issues -mrelax, we need to pass '--relax' to linker. */
-#define LINK_SPEC \
- " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
- " %{mrelax:--relax}"
-
-#define LIB_SPEC \
- " -lc -lgloss"
-
-/* The option -mno-ctor-dtor can disable constructor/destructor feature
- by applying different crt stuff. In the convention, crt0.o is the
- startup file without constructor/destructor;
- crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
- startup files with constructor/destructor.
- Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
- by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
- currently provided by GCC for nds32 target.
-
- For nds32 target so far:
- If -mno-ctor-dtor, we are going to link
- "crt0.o [user objects]".
- If general cases, we are going to link
- "crt1.o crtbegin1.o [user objects] crtend1.o". */
-#define STARTFILE_SPEC \
- " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
- " %{!mno-ctor-dtor:crtbegin1.o%s}"
-#define ENDFILE_SPEC \
- " %{!mno-ctor-dtor:crtend1.o%s}"
+ " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}" \
+ " %{mext-dsp:-mdsp-ext}" \
+ " %{O|O1|O2|O3|Ofast:-O1;:-Os}"
/* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
configure gcc with --target=nds32be-* setting.
# define NDS32_ENDIAN_DEFAULT "mlittle-endian"
#endif
-/* Currently we only have elf toolchain,
- where -mcmodel=medium is always the default. */
-#define NDS32_CMODEL_DEFAULT "mcmodel=medium"
+#if TARGET_ELF
+# define NDS32_CMODEL_DEFAULT "mcmodel=medium"
+#else
+# define NDS32_CMODEL_DEFAULT "mcmodel=large"
+#endif
#define MULTILIB_DEFAULTS \
{ NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
#define STACK_BOUNDARY 64
-#define FUNCTION_BOUNDARY 32
+#define FUNCTION_BOUNDARY \
+ ((NDS32_ALIGN_P () || TARGET_ALIGN_FUNCTION) ? 32 : 16)
#define BIGGEST_ALIGNMENT 64
+#define DATA_ALIGNMENT(constant, basic_align) \
+ nds32_data_alignment (constant, basic_align)
+
+#define LOCAL_ALIGNMENT(type, basic_align) \
+ nds32_local_alignment (type, basic_align)
+
#define EMPTY_FIELD_BOUNDARY 32
#define STRUCTURE_SIZE_BOUNDARY 8
#define FIRST_PARM_OFFSET(fundecl) \
(NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
+/* A C expression whose value is RTL representing the address in a stack frame
+ where the pointer to the caller's frame is stored. */
+#define DYNAMIC_CHAIN_ADDRESS(frameaddr) \
+ nds32_dynamic_chain_address (frameaddr)
+
#define RETURN_ADDR_RTX(count, frameaddr) \
nds32_return_addr_rtx (count, frameaddr)
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LP_REGNUM)
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LP_REGNUM)
-#define DBX_REGISTER_NUMBER(REGNO) nds32_dbx_register_number (REGNO)
+/* Use $r0 $r1 to pass exception handling information. */
+#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) : INVALID_REGNUM)
+/* The register $r2 that represents a location in which to store a stack
+ adjustment to be applied before function return.
+ This is used to unwind the stack to an exception handler's call frame. */
+#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
+
+#define DEBUGGER_REGNO(REGNO) nds32_debugger_regno (REGNO)
#define STACK_POINTER_REGNUM SP_REGNUM
chain_value
nested function address
- Please check nds32.c implementation for more information. */
+ Please check nds32.cc implementation for more information. */
#define TRAMPOLINE_SIZE 24
/* Because all instructions/data in trampoline template are 4-byte size,
/* We have "LW.bi Rt, [Ra], Rb" instruction form. */
#define HAVE_POST_MODIFY_REG 1
+#define USE_LOAD_POST_INCREMENT(mode) \
+ nds32_use_load_post_increment(mode)
+#define USE_LOAD_POST_DECREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
+#define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
+#define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
+
#define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
#define MAX_REGS_PER_ADDRESS 3
#define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
+#define SYMBOLIC_CONST_P(X) \
+(GET_CODE (X) == SYMBOL_REF \
+ || GET_CODE (X) == LABEL_REF \
+ || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
+
\f
/* Defining the Output Assembler Language. */
#define ASM_COMMENT_START "!"
-#define ASM_APP_ON "! #APP"
+#define ASM_APP_ON "! #APP\n"
#define ASM_APP_OFF "! #NO_APP\n"
#define DWARF2_UNWIND_INFO 1
#define JUMP_ALIGN(x) \
- (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
+ (align_jumps.levels[0].log \
+ ? align_jumps : align_flags (nds32_target_alignment (x)))
#define LOOP_ALIGN(x) \
- (align_loops_log ? align_loops_log : nds32_target_alignment (x))
+ (align_loops.levels[0].log \
+ ? align_loops : align_flags (nds32_target_alignment (x)))
#define LABEL_ALIGN(x) \
- (align_labels_log ? align_labels_log : nds32_target_alignment (x))
+ (align_labels.levels[0].log \
+ ? align_labels : align_flags (nds32_target_alignment (x)))
#define ASM_OUTPUT_ALIGN(stream, power) \
fprintf (stream, "\t.align\t%d\n", power)
/* Return the preferred mode for and addr_diff_vec when the mininum
and maximum offset are known. */
#define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \
- ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode \
- : (max_offset >= 100) ? HImode \
- : QImode)
+ nds32_case_vector_shorten_mode (min_offset, max_offset, body)
/* Generate pc relative jump table when -fpic or -Os. */
#define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
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