/* Definitions of target machine of Andes NDS32 cpu for GNU compiler
- Copyright (C) 2012-2018 Free Software Foundation, Inc.
+ Copyright (C) 2012-2024 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
/* ------------------------------------------------------------------------ */
/* The following are auxiliary macros or structure declarations
- that are used all over the nds32.c and nds32.h. */
+ that are used all over the nds32.cc and nds32.h. */
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
(LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
/* Determine whether we would like to have code generation strictly aligned.
We set it strictly aligned when -malways-align is enabled.
- Check gcc/common/config/nds32/nds32-common.c for the optimizations that
+ Check gcc/common/config/nds32/nds32-common.cc for the optimizations that
apply -malways-align. */
#define NDS32_ALIGN_P() (TARGET_ALWAYS_ALIGN)
As long as the register satisfies both criteria above,
it is required to be saved. */
#define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \
- ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
+ (!call_used_or_fixed_reg_p (regno) && df_regs_ever_live_p (regno))
/* This macro is to check if the push25/pop25 are available to be used
for code generation. Because pop25 also performs return behavior,
2. The rtl lowering and optimization are close to target code.
For this case we need address to be strictly aligned. */
int strict_aligned_p;
+
+ /* Record two similar attributes status. */
+ int attr_naked_p;
+ int attr_no_prologue_p;
};
/* A C structure that contains the arguments information. */
0 for reset handler,
1-8 for exception handler,
and 9-72 for interrupt handler.
- We use an array, which is defined in nds32.c, to record
+ We use an array, which is defined in nds32.cc, to record
essential information for each vector. */
#define NDS32_N_ISR_VECTORS 73
{
NDS32_NESTED,
NDS32_NOT_NESTED,
- NDS32_NESTED_READY
+ NDS32_NESTED_READY,
+ NDS32_CRITICAL
};
/* Define structure to record isr information.
The isr vector array 'isr_vectors[]' with this structure
- is defined in nds32.c. */
+ is defined in nds32.cc. */
struct nds32_isr_info
{
/* The field to identify isr category.
unless user specifies attribute to change it. */
enum nds32_isr_nested_type nested_type;
+ /* Secure isr level.
+ Currently we have 0-3 security level.
+ It should be set to 0 by default.
+ For security processors, this is determined by secure
+ attribute or compiler options. */
+ unsigned int security_level;
+
/* Total vectors.
The total vectors = interrupt + exception numbers + reset.
It should be set to 0 by default.
/* ------------------------------------------------------------------------ */
-#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
+#define TARGET_ISR_VECTOR_SIZE_4_BYTE \
+ (nds32_isr_vector_size == 4)
+#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
#define TARGET_ISA_V3 \
(nds32_arch_option == ARCH_V3 \
+ || nds32_arch_option == ARCH_V3J \
|| nds32_arch_option == ARCH_V3F \
|| nds32_arch_option == ARCH_V3S)
#define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M)
+#define TARGET_PIPELINE_N7 \
+ (nds32_cpu_option == CPU_N7)
+#define TARGET_PIPELINE_N8 \
+ (nds32_cpu_option == CPU_N6 \
+ || nds32_cpu_option == CPU_N8)
#define TARGET_PIPELINE_N9 \
(nds32_cpu_option == CPU_N9)
+#define TARGET_PIPELINE_N10 \
+ (nds32_cpu_option == CPU_N10)
+#define TARGET_PIPELINE_N13 \
+ (nds32_cpu_option == CPU_N12 || nds32_cpu_option == CPU_N13)
+#define TARGET_PIPELINE_GRAYWOLF \
+ (nds32_cpu_option == CPU_GRAYWOLF)
#define TARGET_PIPELINE_SIMPLE \
(nds32_cpu_option == CPU_SIMPLE)
#define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2
+/* ------------------------------------------------------------------------ */
+
+#ifdef TARGET_DEFAULT_RELAX
+# define NDS32_RELAX_SPEC " %{!mno-relax:--relax}"
+#else
+# define NDS32_RELAX_SPEC " %{mrelax:--relax}"
+#endif
+
#ifdef TARGET_DEFAULT_EXT_DSP
# define NDS32_EXT_DSP_SPEC " %{!mno-ext-dsp:-mext-dsp}"
#else
" %{mext-dsp:-mdsp-ext}" \
" %{O|O1|O2|O3|Ofast:-O1;:-Os}"
-/* If user issues -mrelax, we need to pass '--relax' to linker. */
-#define LINK_SPEC \
- " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
- " %{mrelax:--relax}"
-
-#define LIB_SPEC \
- " -lc -lgloss"
-
-/* The option -mno-ctor-dtor can disable constructor/destructor feature
- by applying different crt stuff. In the convention, crt0.o is the
- startup file without constructor/destructor;
- crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
- startup files with constructor/destructor.
- Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
- by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
- currently provided by GCC for nds32 target.
-
- For nds32 target so far:
- If -mno-ctor-dtor, we are going to link
- "crt0.o [user objects]".
- If general cases, we are going to link
- "crt1.o crtbegin1.o [user objects] crtend1.o". */
-#define STARTFILE_SPEC \
- " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
- " %{!mno-ctor-dtor:crtbegin1.o%s}"
-#define ENDFILE_SPEC \
- " %{!mno-ctor-dtor:crtend1.o%s}"
-
/* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
configure gcc with --target=nds32be-* setting.
Check gcc/config.gcc for more information. */
# define NDS32_ENDIAN_DEFAULT "mlittle-endian"
#endif
-/* Currently we only have elf toolchain,
- where -mcmodel=medium is always the default. */
-#define NDS32_CMODEL_DEFAULT "mcmodel=medium"
+#if TARGET_ELF
+# define NDS32_CMODEL_DEFAULT "mcmodel=medium"
+#else
+# define NDS32_CMODEL_DEFAULT "mcmodel=large"
+#endif
#define MULTILIB_DEFAULTS \
{ NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
This is used to unwind the stack to an exception handler's call frame. */
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
-#define DBX_REGISTER_NUMBER(REGNO) nds32_dbx_register_number (REGNO)
+#define DEBUGGER_REGNO(REGNO) nds32_debugger_regno (REGNO)
#define STACK_POINTER_REGNUM SP_REGNUM
chain_value
nested function address
- Please check nds32.c implementation for more information. */
+ Please check nds32.cc implementation for more information. */
#define TRAMPOLINE_SIZE 24
/* Because all instructions/data in trampoline template are 4-byte size,
#define DWARF2_UNWIND_INFO 1
#define JUMP_ALIGN(x) \
- (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
+ (align_jumps.levels[0].log \
+ ? align_jumps : align_flags (nds32_target_alignment (x)))
#define LOOP_ALIGN(x) \
- (align_loops_log ? align_loops_log : nds32_target_alignment (x))
+ (align_loops.levels[0].log \
+ ? align_loops : align_flags (nds32_target_alignment (x)))
#define LABEL_ALIGN(x) \
- (align_labels_log ? align_labels_log : nds32_target_alignment (x))
+ (align_labels.levels[0].log \
+ ? align_labels : align_flags (nds32_target_alignment (x)))
#define ASM_OUTPUT_ALIGN(stream, power) \
fprintf (stream, "\t.align\t%d\n", power)
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