/* Builtins macros for RISC-V 'V' Extension for GNU compiler.
- Copyright (C) 2022-2022 Free Software Foundation, Inc.
+ Copyright (C) 2022-2024 Free Software Foundation, Inc.
Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
This file is part of GCC.
<http://www.gnu.org/licenses/>. */
/* Use "DEF_RVV_TYPE" macro to define RVV datatype builtins.
- 1.The 1 argument is the name exposed to users.
+ 1.The 'NAME' argument is the name exposed to users.
For example, "vint32m1_t".
- 2.The 2 argument is the length of ABI-name.
+ 2.The 'NCHARS' argument is the length of ABI-name.
For example, length of "__rvv_int32m1_t" is 15.
- 3.The 3 argument is the ABI-name. For example, "__rvv_int32m1_t".
- 4.The 4 argument is associated scalar type which is used in
+ 3.The 'ABI_NAME' argument is the ABI-name. For example, "__rvv_int32m1_t".
+ 4.The 'SCALAR_TYPE' argument is associated scalar type which is used in
"build_vector_type_for_mode". For "vint32m1_t", we use "intSI_type_node" in
RV64. Otherwise, we use "long_integer_type_node".
- 5.The 5 and 6 argument are the machine modes of corresponding RVV type used
- in "build_vector_type_for_mode". For "vint32m1_t", we use VNx2SImode when
- TARGET_MIN_VLEN > 32. Otherwise the machine mode is VNx1SImode. */
+ 5.The 'VECTOR_MODE' is the machine modes of corresponding RVV type used
+ in "build_vector_type_for_mode".
+ For example: VECTOR_MODE = RVVM1SImode for "vint32m1_t".
+ 6.The 'VECTOR_SUFFIX' define mode suffix for vector type.
+ For example: type_suffixes[VECTOR_TYPE_vin32m1_t].vector = i32m1.
+ 7.The 'SCALAR_SUFFIX' define mode suffix for scalar type.
+ For example: type_suffixes[VECTOR_TYPE_vin32m1_t].scalar = i32.
+ 8.The 'VSETVL_SUFFIX' define mode suffix for vsetvli instruction.
+ For example: type_suffixes[VECTOR_TYPE_vin32m1_t].vsetvl = e32m1.
+*/
#ifndef DEF_RVV_TYPE
-#define DEF_RVV_TYPE(USER_NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE, \
- VECTOR_MODE_MIN_VLEN_32)
+#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE, \
+ VECTOR_SUFFIX, SCALAR_SUFFIX, VSETVL_SUFFIX)
+#endif
+
+#ifndef DEF_RVV_TUPLE_TYPE
+#define DEF_RVV_TUPLE_TYPE(NAME, NCHARS, ABI_NAME, SUBPART_TYPE, SCALAR_TYPE, \
+ NF, VECTOR_SUFFIX)
+#endif
+
+/* Use "DEF_RVV_OP_TYPE" macro to define RVV operand types.
+ The 'NAME' will be concatenated into intrinsic function name. */
+#ifndef DEF_RVV_OP_TYPE
+#define DEF_RVV_OP_TYPE(NAME)
+#endif
+
+/* Use "DEF_RVV_PRED_TYPE" macro to define RVV predication types.
+ The 'NAME' will be concatenated into intrinsic function name. */
+#ifndef DEF_RVV_PRED_TYPE
+#define DEF_RVV_PRED_TYPE(NAME)
+#endif
+
+/* Use "DEF_RVV_BASE_TYPE" macro to define RVV base types.
+ The 'NAME' will be concatenated into intrinsic function name. */
+#ifndef DEF_RVV_BASE_TYPE
+#define DEF_RVV_BASE_TYPE(NAME, TYPE)
+#endif
+
+/* Use "DEF_RVV_TYPE_INDEX" macro to define RVV function types. */
+#ifndef DEF_RVV_TYPE_INDEX
+#define DEF_RVV_TYPE_INDEX( \
+ VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX, EEW16_INDEX, EEW32_INDEX, \
+ EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, OCT_TRUNC, \
+ DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED, \
+ DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, \
+ EEW8_INTERPRET, EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, \
+ BOOL1_INTERPRET, BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, \
+ BOOL16_INTERPRET, BOOL32_INTERPRET, BOOL64_INTERPRET, \
+ SIGNED_EEW8_LMUL1_INTERPRET, SIGNED_EEW16_LMUL1_INTERPRET, \
+ SIGNED_EEW32_LMUL1_INTERPRET, SIGNED_EEW64_LMUL1_INTERPRET, \
+ UNSIGNED_EEW8_LMUL1_INTERPRET, UNSIGNED_EEW16_LMUL1_INTERPRET, \
+ UNSIGNED_EEW32_LMUL1_INTERPRET, UNSIGNED_EEW64_LMUL1_INTERPRET, \
+ X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT, \
+ X64_VLMUL_EXT, TUPLE_SUBPART)
+#endif
+
+/* Define RVV_VXRM rounding mode enum for fixed-point intrinsics. */
+#ifndef DEF_RVV_VXRM_ENUM
+#define DEF_RVV_VXRM_ENUM(NAME, VALUE)
+#endif
+
+/* Define RVV_FRM rounding mode enum for floating-point intrinsics. */
+#ifndef DEF_RVV_FRM_ENUM
+#define DEF_RVV_FRM_ENUM(NAME, VALUE)
#endif
/* SEW/LMUL = 64:
- Only enable when TARGET_MIN_VLEN > 32 and machine mode = VNx1BImode. */
-DEF_RVV_TYPE (vbool64_t, 14, __rvv_bool64_t, boolean, VNx1BI, VOID)
+ Only enable when TARGET_MIN_VLEN > 32.
+ Machine mode = RVVMF64BImode. */
+DEF_RVV_TYPE (vbool64_t, 14, __rvv_bool64_t, boolean, RVVMF64BI, _b64, , )
/* SEW/LMUL = 32:
- Machine mode = VNx2BImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx1BImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vbool32_t, 14, __rvv_bool32_t, boolean, VNx2BI, VNx1BI)
+ Machine mode = RVVMF32BImode. */
+DEF_RVV_TYPE (vbool32_t, 14, __rvv_bool32_t, boolean, RVVMF32BI, _b32, , )
/* SEW/LMUL = 16:
- Machine mode = VNx2BImode when TARGET_MIN_VLEN = 32.
- Machine mode = VNx4BImode when TARGET_MIN_VLEN > 32. */
-DEF_RVV_TYPE (vbool16_t, 14, __rvv_bool16_t, boolean, VNx4BI, VNx2BI)
+ Machine mode = RVVMF16BImode. */
+DEF_RVV_TYPE (vbool16_t, 14, __rvv_bool16_t, boolean, RVVMF16BI, _b16, , )
/* SEW/LMUL = 8:
- Machine mode = VNx8BImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx4BImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vbool8_t, 13, __rvv_bool8_t, boolean, VNx8BI, VNx4BI)
+ Machine mode = RVVMF8BImode. */
+DEF_RVV_TYPE (vbool8_t, 13, __rvv_bool8_t, boolean, RVVMF8BI, _b8, , )
/* SEW/LMUL = 4:
- Machine mode = VNx16BImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx8BImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vbool4_t, 13, __rvv_bool4_t, boolean, VNx16BI, VNx8BI)
+ Machine mode = RVVMF4BImode. */
+DEF_RVV_TYPE (vbool4_t, 13, __rvv_bool4_t, boolean, RVVMF4BI, _b4, , )
/* SEW/LMUL = 2:
- Machine mode = VNx32BImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx16BImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vbool2_t, 13, __rvv_bool2_t, boolean, VNx32BI, VNx16BI)
+ Machine mode = RVVMF2BImode. */
+DEF_RVV_TYPE (vbool2_t, 13, __rvv_bool2_t, boolean, RVVMF2BI, _b2, , )
/* SEW/LMUL = 1:
- Machine mode = VNx64BImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx32BImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vbool1_t, 13, __rvv_bool1_t, boolean, VNx64BI, VNx32BI)
+ Machine mode = RVVM1BImode. */
+DEF_RVV_TYPE (vbool1_t, 13, __rvv_bool1_t, boolean, RVVM1BI, _b1, , )
/* LMUL = 1/8:
- Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1QImode. */
-DEF_RVV_TYPE (vint8mf8_t, 15, __rvv_int8mf8_t, intQI, VNx1QI, VOID)
-DEF_RVV_TYPE (vuint8mf8_t, 16, __rvv_uint8mf8_t, unsigned_intQI, VNx1QI, VOID)
+ Only enble when TARGET_MIN_VLEN > 32.
+ Machine mode = RVVMF8QImode. */
+DEF_RVV_TYPE (vint8mf8_t, 15, __rvv_int8mf8_t, int8, RVVMF8QI, _i8mf8, _i8,
+ _e8mf8)
+DEF_RVV_TYPE (vuint8mf8_t, 16, __rvv_uint8mf8_t, uint8, RVVMF8QI, _u8mf8, _u8,
+ _e8mf8)
+/* Define tuple types for SEW = 8, LMUL = MF8. */
+DEF_RVV_TUPLE_TYPE (vint8mf8x2_t, 17, __rvv_int8mf8x2_t, vint8mf8_t, int8, 2, _i8mf8x2)
+DEF_RVV_TUPLE_TYPE (vuint8mf8x2_t, 18, __rvv_uint8mf8x2_t, vuint8mf8_t, uint8, 2, _u8mf8x2)
+DEF_RVV_TUPLE_TYPE (vint8mf8x3_t, 17, __rvv_int8mf8x3_t, vint8mf8_t, int8, 3, _i8mf8x3)
+DEF_RVV_TUPLE_TYPE (vuint8mf8x3_t, 18, __rvv_uint8mf8x3_t, vuint8mf8_t, uint8, 3, _u8mf8x3)
+DEF_RVV_TUPLE_TYPE (vint8mf8x4_t, 17, __rvv_int8mf8x4_t, vint8mf8_t, int8, 4, _i8mf8x4)
+DEF_RVV_TUPLE_TYPE (vuint8mf8x4_t, 18, __rvv_uint8mf8x4_t, vuint8mf8_t, uint8, 4, _u8mf8x4)
+DEF_RVV_TUPLE_TYPE (vint8mf8x5_t, 17, __rvv_int8mf8x5_t, vint8mf8_t, int8, 5, _i8mf8x5)
+DEF_RVV_TUPLE_TYPE (vuint8mf8x5_t, 18, __rvv_uint8mf8x5_t, vuint8mf8_t, uint8, 5, _u8mf8x5)
+DEF_RVV_TUPLE_TYPE (vint8mf8x6_t, 17, __rvv_int8mf8x6_t, vint8mf8_t, int8, 6, _i8mf8x6)
+DEF_RVV_TUPLE_TYPE (vuint8mf8x6_t, 18, __rvv_uint8mf8x6_t, vuint8mf8_t, uint8, 6, _u8mf8x6)
+DEF_RVV_TUPLE_TYPE (vint8mf8x7_t, 17, __rvv_int8mf8x7_t, vint8mf8_t, int8, 7, _i8mf8x7)
+DEF_RVV_TUPLE_TYPE (vuint8mf8x7_t, 18, __rvv_uint8mf8x7_t, vuint8mf8_t, uint8, 7, _u8mf8x7)
+DEF_RVV_TUPLE_TYPE (vint8mf8x8_t, 17, __rvv_int8mf8x8_t, vint8mf8_t, int8, 8, _i8mf8x8)
+DEF_RVV_TUPLE_TYPE (vuint8mf8x8_t, 18, __rvv_uint8mf8x8_t, vuint8mf8_t, uint8, 8, _u8mf8x8)
/* LMUL = 1/4:
- Machine mode = VNx2QImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx1QImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint8mf4_t, 15, __rvv_int8mf4_t, intQI, VNx2QI, VNx1QI)
-DEF_RVV_TYPE (vuint8mf4_t, 16, __rvv_uint8mf4_t, unsigned_intQI, VNx2QI, VNx1QI)
+ Machine mode = RVVMF4QImode. */
+DEF_RVV_TYPE (vint8mf4_t, 15, __rvv_int8mf4_t, int8, RVVMF4QI, _i8mf4, _i8,
+ _e8mf4)
+DEF_RVV_TYPE (vuint8mf4_t, 16, __rvv_uint8mf4_t, uint8, RVVMF4QI, _u8mf4, _u8,
+ _e8mf4)
+/* Define tuple types for SEW = 8, LMUL = MF4. */
+DEF_RVV_TUPLE_TYPE (vint8mf4x2_t, 17, __rvv_int8mf4x2_t, vint8mf4_t, int8, 2, _i8mf4x2)
+DEF_RVV_TUPLE_TYPE (vuint8mf4x2_t, 18, __rvv_uint8mf4x2_t, vuint8mf4_t, uint8, 2, _u8mf4x2)
+DEF_RVV_TUPLE_TYPE (vint8mf4x3_t, 17, __rvv_int8mf4x3_t, vint8mf4_t, int8, 3, _i8mf4x3)
+DEF_RVV_TUPLE_TYPE (vuint8mf4x3_t, 18, __rvv_uint8mf4x3_t, vuint8mf4_t, uint8, 3, _u8mf4x3)
+DEF_RVV_TUPLE_TYPE (vint8mf4x4_t, 17, __rvv_int8mf4x4_t, vint8mf4_t, int8, 4, _i8mf4x4)
+DEF_RVV_TUPLE_TYPE (vuint8mf4x4_t, 18, __rvv_uint8mf4x4_t, vuint8mf4_t, uint8, 4, _u8mf4x4)
+DEF_RVV_TUPLE_TYPE (vint8mf4x5_t, 17, __rvv_int8mf4x5_t, vint8mf4_t, int8, 5, _i8mf4x5)
+DEF_RVV_TUPLE_TYPE (vuint8mf4x5_t, 18, __rvv_uint8mf4x5_t, vuint8mf4_t, uint8, 5, _u8mf4x5)
+DEF_RVV_TUPLE_TYPE (vint8mf4x6_t, 17, __rvv_int8mf4x6_t, vint8mf4_t, int8, 6, _i8mf4x6)
+DEF_RVV_TUPLE_TYPE (vuint8mf4x6_t, 18, __rvv_uint8mf4x6_t, vuint8mf4_t, uint8, 6, _u8mf4x6)
+DEF_RVV_TUPLE_TYPE (vint8mf4x7_t, 17, __rvv_int8mf4x7_t, vint8mf4_t, int8, 7, _i8mf4x7)
+DEF_RVV_TUPLE_TYPE (vuint8mf4x7_t, 18, __rvv_uint8mf4x7_t, vuint8mf4_t, uint8, 7, _u8mf4x7)
+DEF_RVV_TUPLE_TYPE (vint8mf4x8_t, 17, __rvv_int8mf4x8_t, vint8mf4_t, int8, 8, _i8mf4x8)
+DEF_RVV_TUPLE_TYPE (vuint8mf4x8_t, 18, __rvv_uint8mf4x8_t, vuint8mf4_t, uint8, 8, _u8mf4x8)
/* LMUL = 1/2:
- Machine mode = VNx4QImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx2QImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint8mf2_t, 15, __rvv_int8mf2_t, intQI, VNx4QI, VNx2QI)
-DEF_RVV_TYPE (vuint8mf2_t, 16, __rvv_uint8mf2_t, unsigned_intQI, VNx4QI, VNx2QI)
+ Machine mode = RVVMF2QImode. */
+DEF_RVV_TYPE (vint8mf2_t, 15, __rvv_int8mf2_t, int8, RVVMF2QI, _i8mf2, _i8,
+ _e8mf2)
+DEF_RVV_TYPE (vuint8mf2_t, 16, __rvv_uint8mf2_t, uint8, RVVMF2QI, _u8mf2, _u8,
+ _e8mf2)
+/* Define tuple types for SEW = 8, LMUL = MF2. */
+DEF_RVV_TUPLE_TYPE (vint8mf2x2_t, 17, __rvv_int8mf2x2_t, vint8mf2_t, int8, 2, _i8mf2x2)
+DEF_RVV_TUPLE_TYPE (vuint8mf2x2_t, 18, __rvv_uint8mf2x2_t, vuint8mf2_t, uint8, 2, _u8mf2x2)
+DEF_RVV_TUPLE_TYPE (vint8mf2x3_t, 17, __rvv_int8mf2x3_t, vint8mf2_t, int8, 3, _i8mf2x3)
+DEF_RVV_TUPLE_TYPE (vuint8mf2x3_t, 18, __rvv_uint8mf2x3_t, vuint8mf2_t, uint8, 3, _u8mf2x3)
+DEF_RVV_TUPLE_TYPE (vint8mf2x4_t, 17, __rvv_int8mf2x4_t, vint8mf2_t, int8, 4, _i8mf2x4)
+DEF_RVV_TUPLE_TYPE (vuint8mf2x4_t, 18, __rvv_uint8mf2x4_t, vuint8mf2_t, uint8, 4, _u8mf2x4)
+DEF_RVV_TUPLE_TYPE (vint8mf2x5_t, 17, __rvv_int8mf2x5_t, vint8mf2_t, int8, 5, _i8mf2x5)
+DEF_RVV_TUPLE_TYPE (vuint8mf2x5_t, 18, __rvv_uint8mf2x5_t, vuint8mf2_t, uint8, 5, _u8mf2x5)
+DEF_RVV_TUPLE_TYPE (vint8mf2x6_t, 17, __rvv_int8mf2x6_t, vint8mf2_t, int8, 6, _i8mf2x6)
+DEF_RVV_TUPLE_TYPE (vuint8mf2x6_t, 18, __rvv_uint8mf2x6_t, vuint8mf2_t, uint8, 6, _u8mf2x6)
+DEF_RVV_TUPLE_TYPE (vint8mf2x7_t, 17, __rvv_int8mf2x7_t, vint8mf2_t, int8, 7, _i8mf2x7)
+DEF_RVV_TUPLE_TYPE (vuint8mf2x7_t, 18, __rvv_uint8mf2x7_t, vuint8mf2_t, uint8, 7, _u8mf2x7)
+DEF_RVV_TUPLE_TYPE (vint8mf2x8_t, 17, __rvv_int8mf2x8_t, vint8mf2_t, int8, 8, _i8mf2x8)
+DEF_RVV_TUPLE_TYPE (vuint8mf2x8_t, 18, __rvv_uint8mf2x8_t, vuint8mf2_t, uint8, 8, _u8mf2x8)
/* LMUL = 1:
- Machine mode = VNx8QImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx4QImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint8m1_t, 14, __rvv_int8m1_t, intQI, VNx8QI, VNx4QI)
-DEF_RVV_TYPE (vuint8m1_t, 15, __rvv_uint8m1_t, unsigned_intQI, VNx8QI, VNx4QI)
+ Machine mode = RVVM1QImode. */
+DEF_RVV_TYPE (vint8m1_t, 14, __rvv_int8m1_t, int8, RVVM1QI, _i8m1, _i8, _e8m1)
+DEF_RVV_TYPE (vuint8m1_t, 15, __rvv_uint8m1_t, uint8, RVVM1QI, _u8m1, _u8,
+ _e8m1)
+/* Define tuple types for SEW = 8, LMUL = M1. */
+DEF_RVV_TUPLE_TYPE (vint8m1x2_t, 16, __rvv_int8m1x2_t, vint8m1_t, int8, 2, _i8m1x2)
+DEF_RVV_TUPLE_TYPE (vuint8m1x2_t, 17, __rvv_uint8m1x2_t, vuint8m1_t, uint8, 2, _u8m1x2)
+DEF_RVV_TUPLE_TYPE (vint8m1x3_t, 16, __rvv_int8m1x3_t, vint8m1_t, int8, 3, _i8m1x3)
+DEF_RVV_TUPLE_TYPE (vuint8m1x3_t, 17, __rvv_uint8m1x3_t, vuint8m1_t, uint8, 3, _u8m1x3)
+DEF_RVV_TUPLE_TYPE (vint8m1x4_t, 16, __rvv_int8m1x4_t, vint8m1_t, int8, 4, _i8m1x4)
+DEF_RVV_TUPLE_TYPE (vuint8m1x4_t, 17, __rvv_uint8m1x4_t, vuint8m1_t, uint8, 4, _u8m1x4)
+DEF_RVV_TUPLE_TYPE (vint8m1x5_t, 16, __rvv_int8m1x5_t, vint8m1_t, int8, 5, _i8m1x5)
+DEF_RVV_TUPLE_TYPE (vuint8m1x5_t, 17, __rvv_uint8m1x5_t, vuint8m1_t, uint8, 5, _u8m1x5)
+DEF_RVV_TUPLE_TYPE (vint8m1x6_t, 16, __rvv_int8m1x6_t, vint8m1_t, int8, 6, _i8m1x6)
+DEF_RVV_TUPLE_TYPE (vuint8m1x6_t, 17, __rvv_uint8m1x6_t, vuint8m1_t, uint8, 6, _u8m1x6)
+DEF_RVV_TUPLE_TYPE (vint8m1x7_t, 16, __rvv_int8m1x7_t, vint8m1_t, int8, 7, _i8m1x7)
+DEF_RVV_TUPLE_TYPE (vuint8m1x7_t, 17, __rvv_uint8m1x7_t, vuint8m1_t, uint8, 7, _u8m1x7)
+DEF_RVV_TUPLE_TYPE (vint8m1x8_t, 16, __rvv_int8m1x8_t, vint8m1_t, int8, 8, _i8m1x8)
+DEF_RVV_TUPLE_TYPE (vuint8m1x8_t, 17, __rvv_uint8m1x8_t, vuint8m1_t, uint8, 8, _u8m1x8)
/* LMUL = 2:
- Machine mode = VNx16QImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx8QImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint8m2_t, 14, __rvv_int8m2_t, intQI, VNx16QI, VNx8QI)
-DEF_RVV_TYPE (vuint8m2_t, 15, __rvv_uint8m2_t, unsigned_intQI, VNx16QI, VNx8QI)
+ Machine mode = RVVM2QImode. */
+DEF_RVV_TYPE (vint8m2_t, 14, __rvv_int8m2_t, int8, RVVM2QI, _i8m2, _i8, _e8m2)
+DEF_RVV_TYPE (vuint8m2_t, 15, __rvv_uint8m2_t, uint8, RVVM2QI, _u8m2, _u8,
+ _e8m2)
+/* Define tuple types for SEW = 8, LMUL = M2. */
+DEF_RVV_TUPLE_TYPE (vint8m2x2_t, 16, __rvv_int8m2x2_t, vint8m2_t, int8, 2, _i8m2x2)
+DEF_RVV_TUPLE_TYPE (vuint8m2x2_t, 17, __rvv_uint8m2x2_t, vuint8m2_t, uint8, 2, _u8m2x2)
+DEF_RVV_TUPLE_TYPE (vint8m2x3_t, 16, __rvv_int8m2x3_t, vint8m2_t, int8, 3, _i8m2x3)
+DEF_RVV_TUPLE_TYPE (vuint8m2x3_t, 17, __rvv_uint8m2x3_t, vuint8m2_t, uint8, 3, _u8m2x3)
+DEF_RVV_TUPLE_TYPE (vint8m2x4_t, 16, __rvv_int8m2x4_t, vint8m2_t, int8, 4, _i8m2x4)
+DEF_RVV_TUPLE_TYPE (vuint8m2x4_t, 17, __rvv_uint8m2x4_t, vuint8m2_t, uint8, 4, _u8m2x4)
/* LMUL = 4:
- Machine mode = VNx32QImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx16QImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint8m4_t, 14, __rvv_int8m4_t, intQI, VNx32QI, VNx16QI)
-DEF_RVV_TYPE (vuint8m4_t, 15, __rvv_uint8m4_t, unsigned_intQI, VNx32QI, VNx16QI)
+ Machine mode = RVVM4QImode. */
+DEF_RVV_TYPE (vint8m4_t, 14, __rvv_int8m4_t, int8, RVVM4QI, _i8m4, _i8, _e8m4)
+DEF_RVV_TYPE (vuint8m4_t, 15, __rvv_uint8m4_t, uint8, RVVM4QI, _u8m4, _u8,
+ _e8m4)
+/* Define tuple types for SEW = 8, LMUL = M4. */
+DEF_RVV_TUPLE_TYPE (vint8m4x2_t, 16, __rvv_int8m4x2_t, vint8m4_t, int8, 2, _i8m4x2)
+DEF_RVV_TUPLE_TYPE (vuint8m4x2_t, 17, __rvv_uint8m4x2_t, vuint8m4_t, uint8, 2, _u8m4x2)
/* LMUL = 8:
- Machine mode = VNx64QImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx32QImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint8m8_t, 14, __rvv_int8m8_t, intQI, VNx64QI, VNx32QI)
-DEF_RVV_TYPE (vuint8m8_t, 15, __rvv_uint8m8_t, unsigned_intQI, VNx64QI, VNx32QI)
+ Machine mode = RVVM8QImode. */
+DEF_RVV_TYPE (vint8m8_t, 14, __rvv_int8m8_t, int8, RVVM8QI, _i8m8, _i8, _e8m8)
+DEF_RVV_TYPE (vuint8m8_t, 15, __rvv_uint8m8_t, uint8, RVVM8QI, _u8m8, _u8,
+ _e8m8)
/* LMUL = 1/4:
- Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1HImode. */
-DEF_RVV_TYPE (vint16mf4_t, 16, __rvv_int16mf4_t, intHI, VNx1HI, VOID)
-DEF_RVV_TYPE (vuint16mf4_t, 17, __rvv_uint16mf4_t, unsigned_intHI, VNx1HI, VOID)
+ Only enble when TARGET_MIN_VLEN > 32.
+ Machine mode = RVVMF4HImode. */
+DEF_RVV_TYPE (vint16mf4_t, 16, __rvv_int16mf4_t, int16, RVVMF4HI, _i16mf4, _i16,
+ _e16mf4)
+DEF_RVV_TYPE (vuint16mf4_t, 17, __rvv_uint16mf4_t, uint16, RVVMF4HI, _u16mf4,
+ _u16, _e16mf4)
+/* Define tuple types for SEW = 16, LMUL = MF4. */
+DEF_RVV_TUPLE_TYPE (vint16mf4x2_t, 18, __rvv_int16mf4x2_t, vint16mf4_t, int16, 2, _i16mf4x2)
+DEF_RVV_TUPLE_TYPE (vuint16mf4x2_t, 19, __rvv_uint16mf4x2_t, vuint16mf4_t, uint16, 2, _u16mf4x2)
+DEF_RVV_TUPLE_TYPE (vint16mf4x3_t, 18, __rvv_int16mf4x3_t, vint16mf4_t, int16, 3, _i16mf4x3)
+DEF_RVV_TUPLE_TYPE (vuint16mf4x3_t, 19, __rvv_uint16mf4x3_t, vuint16mf4_t, uint16, 3, _u16mf4x3)
+DEF_RVV_TUPLE_TYPE (vint16mf4x4_t, 18, __rvv_int16mf4x4_t, vint16mf4_t, int16, 4, _i16mf4x4)
+DEF_RVV_TUPLE_TYPE (vuint16mf4x4_t, 19, __rvv_uint16mf4x4_t, vuint16mf4_t, uint16, 4, _u16mf4x4)
+DEF_RVV_TUPLE_TYPE (vint16mf4x5_t, 18, __rvv_int16mf4x5_t, vint16mf4_t, int16, 5, _i16mf4x5)
+DEF_RVV_TUPLE_TYPE (vuint16mf4x5_t, 19, __rvv_uint16mf4x5_t, vuint16mf4_t, uint16, 5, _u16mf4x5)
+DEF_RVV_TUPLE_TYPE (vint16mf4x6_t, 18, __rvv_int16mf4x6_t, vint16mf4_t, int16, 6, _i16mf4x6)
+DEF_RVV_TUPLE_TYPE (vuint16mf4x6_t, 19, __rvv_uint16mf4x6_t, vuint16mf4_t, uint16, 6, _u16mf4x6)
+DEF_RVV_TUPLE_TYPE (vint16mf4x7_t, 18, __rvv_int16mf4x7_t, vint16mf4_t, int16, 7, _i16mf4x7)
+DEF_RVV_TUPLE_TYPE (vuint16mf4x7_t, 19, __rvv_uint16mf4x7_t, vuint16mf4_t, uint16, 7, _u16mf4x7)
+DEF_RVV_TUPLE_TYPE (vint16mf4x8_t, 18, __rvv_int16mf4x8_t, vint16mf4_t, int16, 8, _i16mf4x8)
+DEF_RVV_TUPLE_TYPE (vuint16mf4x8_t, 19, __rvv_uint16mf4x8_t, vuint16mf4_t, uint16, 8, _u16mf4x8)
/* LMUL = 1/2:
- Machine mode = VNx2HImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx1HImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint16mf2_t, 16, __rvv_int16mf2_t, intHI, VNx2HI, VNx1HI)
-DEF_RVV_TYPE (vuint16mf2_t, 17, __rvv_uint16mf2_t, unsigned_intHI, VNx2HI,
- VNx1HI)
+ Machine mode = RVVMF2HImode. */
+DEF_RVV_TYPE (vint16mf2_t, 16, __rvv_int16mf2_t, int16, RVVMF2HI, _i16mf2, _i16,
+ _e16mf2)
+DEF_RVV_TYPE (vuint16mf2_t, 17, __rvv_uint16mf2_t, uint16, RVVMF2HI, _u16mf2,
+ _u16, _e16mf2)
+/* Define tuple types for SEW = 16, LMUL = MF2. */
+DEF_RVV_TUPLE_TYPE (vint16mf2x2_t, 18, __rvv_int16mf2x2_t, vint16mf2_t, int16, 2, _i16mf2x2)
+DEF_RVV_TUPLE_TYPE (vuint16mf2x2_t, 19, __rvv_uint16mf2x2_t, vuint16mf2_t, uint16, 2, _u16mf2x2)
+DEF_RVV_TUPLE_TYPE (vint16mf2x3_t, 18, __rvv_int16mf2x3_t, vint16mf2_t, int16, 3, _i16mf2x3)
+DEF_RVV_TUPLE_TYPE (vuint16mf2x3_t, 19, __rvv_uint16mf2x3_t, vuint16mf2_t, uint16, 3, _u16mf2x3)
+DEF_RVV_TUPLE_TYPE (vint16mf2x4_t, 18, __rvv_int16mf2x4_t, vint16mf2_t, int16, 4, _i16mf2x4)
+DEF_RVV_TUPLE_TYPE (vuint16mf2x4_t, 19, __rvv_uint16mf2x4_t, vuint16mf2_t, uint16, 4, _u16mf2x4)
+DEF_RVV_TUPLE_TYPE (vint16mf2x5_t, 18, __rvv_int16mf2x5_t, vint16mf2_t, int16, 5, _i16mf2x5)
+DEF_RVV_TUPLE_TYPE (vuint16mf2x5_t, 19, __rvv_uint16mf2x5_t, vuint16mf2_t, uint16, 5, _u16mf2x5)
+DEF_RVV_TUPLE_TYPE (vint16mf2x6_t, 18, __rvv_int16mf2x6_t, vint16mf2_t, int16, 6, _i16mf2x6)
+DEF_RVV_TUPLE_TYPE (vuint16mf2x6_t, 19, __rvv_uint16mf2x6_t, vuint16mf2_t, uint16, 6, _u16mf2x6)
+DEF_RVV_TUPLE_TYPE (vint16mf2x7_t, 18, __rvv_int16mf2x7_t, vint16mf2_t, int16, 7, _i16mf2x7)
+DEF_RVV_TUPLE_TYPE (vuint16mf2x7_t, 19, __rvv_uint16mf2x7_t, vuint16mf2_t, uint16, 7, _u16mf2x7)
+DEF_RVV_TUPLE_TYPE (vint16mf2x8_t, 18, __rvv_int16mf2x8_t, vint16mf2_t, int16, 8, _i16mf2x8)
+DEF_RVV_TUPLE_TYPE (vuint16mf2x8_t, 19, __rvv_uint16mf2x8_t, vuint16mf2_t, uint16, 8, _u16mf2x8)
/* LMUL = 1:
- Machine mode = VNx4HImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx2HImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint16m1_t, 15, __rvv_int16m1_t, intHI, VNx4HI, VNx2HI)
-DEF_RVV_TYPE (vuint16m1_t, 16, __rvv_uint16m1_t, unsigned_intHI, VNx4HI, VNx2HI)
+ Machine mode = RVVM1HImode. */
+DEF_RVV_TYPE (vint16m1_t, 15, __rvv_int16m1_t, int16, RVVM1HI, _i16m1, _i16,
+ _e16m1)
+DEF_RVV_TYPE (vuint16m1_t, 16, __rvv_uint16m1_t, uint16, RVVM1HI, _u16m1, _u16,
+ _e16m1)
+/* Define tuple types for SEW = 16, LMUL = M1. */
+DEF_RVV_TUPLE_TYPE (vint16m1x2_t, 17, __rvv_int16m1x2_t, vint16m1_t, int16, 2, _i16m1x2)
+DEF_RVV_TUPLE_TYPE (vuint16m1x2_t, 18, __rvv_uint16m1x2_t, vuint16m1_t, uint16, 2, _u16m1x2)
+DEF_RVV_TUPLE_TYPE (vint16m1x3_t, 17, __rvv_int16m1x3_t, vint16m1_t, int16, 3, _i16m1x3)
+DEF_RVV_TUPLE_TYPE (vuint16m1x3_t, 18, __rvv_uint16m1x3_t, vuint16m1_t, uint16, 3, _u16m1x3)
+DEF_RVV_TUPLE_TYPE (vint16m1x4_t, 17, __rvv_int16m1x4_t, vint16m1_t, int16, 4, _i16m1x4)
+DEF_RVV_TUPLE_TYPE (vuint16m1x4_t, 18, __rvv_uint16m1x4_t, vuint16m1_t, uint16, 4, _u16m1x4)
+DEF_RVV_TUPLE_TYPE (vint16m1x5_t, 17, __rvv_int16m1x5_t, vint16m1_t, int16, 5, _i16m1x5)
+DEF_RVV_TUPLE_TYPE (vuint16m1x5_t, 18, __rvv_uint16m1x5_t, vuint16m1_t, uint16, 5, _u16m1x5)
+DEF_RVV_TUPLE_TYPE (vint16m1x6_t, 17, __rvv_int16m1x6_t, vint16m1_t, int16, 6, _i16m1x6)
+DEF_RVV_TUPLE_TYPE (vuint16m1x6_t, 18, __rvv_uint16m1x6_t, vuint16m1_t, uint16, 6, _u16m1x6)
+DEF_RVV_TUPLE_TYPE (vint16m1x7_t, 17, __rvv_int16m1x7_t, vint16m1_t, int16, 7, _i16m1x7)
+DEF_RVV_TUPLE_TYPE (vuint16m1x7_t, 18, __rvv_uint16m1x7_t, vuint16m1_t, uint16, 7, _u16m1x7)
+DEF_RVV_TUPLE_TYPE (vint16m1x8_t, 17, __rvv_int16m1x8_t, vint16m1_t, int16, 8, _i16m1x8)
+DEF_RVV_TUPLE_TYPE (vuint16m1x8_t, 18, __rvv_uint16m1x8_t, vuint16m1_t, uint16, 8, _u16m1x8)
/* LMUL = 2:
- Machine mode = VNx8HImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx4HImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint16m2_t, 15, __rvv_int16m2_t, intHI, VNx8HI, VNx4HI)
-DEF_RVV_TYPE (vuint16m2_t, 16, __rvv_uint16m2_t, unsigned_intHI, VNx8HI, VNx4HI)
+ Machine mode = RVVM1H2mode. */
+DEF_RVV_TYPE (vint16m2_t, 15, __rvv_int16m2_t, int16, RVVM2HI, _i16m2, _i16,
+ _e16m2)
+DEF_RVV_TYPE (vuint16m2_t, 16, __rvv_uint16m2_t, uint16, RVVM2HI, _u16m2, _u16,
+ _e16m2)
+/* Define tuple types for SEW = 16, LMUL = M2. */
+DEF_RVV_TUPLE_TYPE (vint16m2x2_t, 17, __rvv_int16m2x2_t, vint16m2_t, int16, 2, _i16m2x2)
+DEF_RVV_TUPLE_TYPE (vuint16m2x2_t, 18, __rvv_uint16m2x2_t, vuint16m2_t, uint16, 2, _u16m2x2)
+DEF_RVV_TUPLE_TYPE (vint16m2x3_t, 17, __rvv_int16m2x3_t, vint16m2_t, int16, 3, _i16m2x3)
+DEF_RVV_TUPLE_TYPE (vuint16m2x3_t, 18, __rvv_uint16m2x3_t, vuint16m2_t, uint16, 3, _u16m2x3)
+DEF_RVV_TUPLE_TYPE (vint16m2x4_t, 17, __rvv_int16m2x4_t, vint16m2_t, int16, 4, _i16m2x4)
+DEF_RVV_TUPLE_TYPE (vuint16m2x4_t, 18, __rvv_uint16m2x4_t, vuint16m2_t, uint16, 4, _u16m2x4)
/* LMUL = 4:
- Machine mode = VNx16HImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx8HImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint16m4_t, 15, __rvv_int16m4_t, intHI, VNx16HI, VNx8HI)
-DEF_RVV_TYPE (vuint16m4_t, 16, __rvv_uint16m4_t, unsigned_intHI, VNx16HI,
- VNx8HI)
+ Machine mode = RVVM4HImode. */
+DEF_RVV_TYPE (vint16m4_t, 15, __rvv_int16m4_t, int16, RVVM4HI, _i16m4, _i16,
+ _e16m4)
+DEF_RVV_TYPE (vuint16m4_t, 16, __rvv_uint16m4_t, uint16, RVVM4HI, _u16m4, _u16,
+ _e16m4)
+/* Define tuple types for SEW = 16, LMUL = M4. */
+DEF_RVV_TUPLE_TYPE (vint16m4x2_t, 17, __rvv_int16m4x2_t, vint16m4_t, int16, 2, _i16m4x2)
+DEF_RVV_TUPLE_TYPE (vuint16m4x2_t, 18, __rvv_uint16m4x2_t, vuint16m4_t, uint16, 2, _u16m4x2)
/* LMUL = 8:
- Machine mode = VNx32HImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx16HImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint16m8_t, 15, __rvv_int16m8_t, intHI, VNx32HI, VNx16HI)
-DEF_RVV_TYPE (vuint16m8_t, 16, __rvv_uint16m8_t, unsigned_intHI, VNx32HI,
- VNx16HI)
+ Machine mode = RVVM8HImode. */
+DEF_RVV_TYPE (vint16m8_t, 15, __rvv_int16m8_t, int16, RVVM8HI, _i16m8, _i16,
+ _e16m8)
+DEF_RVV_TYPE (vuint16m8_t, 16, __rvv_uint16m8_t, uint16, RVVM8HI, _u16m8, _u16,
+ _e16m8)
/* LMUL = 1/2:
- Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1SImode. */
-DEF_RVV_TYPE (vint32mf2_t, 16, __rvv_int32mf2_t, int32, VNx1SI, VOID)
-DEF_RVV_TYPE (vuint32mf2_t, 17, __rvv_uint32mf2_t, unsigned_int32, VNx1SI, VOID)
+ Only enble when TARGET_MIN_VLEN > 32.
+ Machine mode = RVVMF2SImode. */
+DEF_RVV_TYPE (vint32mf2_t, 16, __rvv_int32mf2_t, int32, RVVMF2SI, _i32mf2, _i32,
+ _e32mf2)
+DEF_RVV_TYPE (vuint32mf2_t, 17, __rvv_uint32mf2_t, uint32, RVVMF2SI, _u32mf2,
+ _u32, _e32mf2)
+/* Define tuple types for SEW = 32, LMUL = MF2. */
+DEF_RVV_TUPLE_TYPE (vint32mf2x2_t, 18, __rvv_int32mf2x2_t, vint32mf2_t, int32, 2, _i32mf2x2)
+DEF_RVV_TUPLE_TYPE (vuint32mf2x2_t, 19, __rvv_uint32mf2x2_t, vuint32mf2_t, uint32, 2, _u32mf2x2)
+DEF_RVV_TUPLE_TYPE (vint32mf2x3_t, 18, __rvv_int32mf2x3_t, vint32mf2_t, int32, 3, _i32mf2x3)
+DEF_RVV_TUPLE_TYPE (vuint32mf2x3_t, 19, __rvv_uint32mf2x3_t, vuint32mf2_t, uint32, 3, _u32mf2x3)
+DEF_RVV_TUPLE_TYPE (vint32mf2x4_t, 18, __rvv_int32mf2x4_t, vint32mf2_t, int32, 4, _i32mf2x4)
+DEF_RVV_TUPLE_TYPE (vuint32mf2x4_t, 19, __rvv_uint32mf2x4_t, vuint32mf2_t, uint32, 4, _u32mf2x4)
+DEF_RVV_TUPLE_TYPE (vint32mf2x5_t, 18, __rvv_int32mf2x5_t, vint32mf2_t, int32, 5, _i32mf2x5)
+DEF_RVV_TUPLE_TYPE (vuint32mf2x5_t, 19, __rvv_uint32mf2x5_t, vuint32mf2_t, uint32, 5, _u32mf2x5)
+DEF_RVV_TUPLE_TYPE (vint32mf2x6_t, 18, __rvv_int32mf2x6_t, vint32mf2_t, int32, 6, _i32mf2x6)
+DEF_RVV_TUPLE_TYPE (vuint32mf2x6_t, 19, __rvv_uint32mf2x6_t, vuint32mf2_t, uint32, 6, _u32mf2x6)
+DEF_RVV_TUPLE_TYPE (vint32mf2x7_t, 18, __rvv_int32mf2x7_t, vint32mf2_t, int32, 7, _i32mf2x7)
+DEF_RVV_TUPLE_TYPE (vuint32mf2x7_t, 19, __rvv_uint32mf2x7_t, vuint32mf2_t, uint32, 7, _u32mf2x7)
+DEF_RVV_TUPLE_TYPE (vint32mf2x8_t, 18, __rvv_int32mf2x8_t, vint32mf2_t, int32, 8, _i32mf2x8)
+DEF_RVV_TUPLE_TYPE (vuint32mf2x8_t, 19, __rvv_uint32mf2x8_t, vuint32mf2_t, uint32, 8, _u32mf2x8)
/* LMUL = 1:
- Machine mode = VNx2SImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx1SImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint32m1_t, 15, __rvv_int32m1_t, int32, VNx2SI, VNx1SI)
-DEF_RVV_TYPE (vuint32m1_t, 16, __rvv_uint32m1_t, unsigned_int32, VNx2SI, VNx1SI)
+ Machine mode = RVVM1SImode. */
+DEF_RVV_TYPE (vint32m1_t, 15, __rvv_int32m1_t, int32, RVVM1SI, _i32m1, _i32,
+ _e32m1)
+DEF_RVV_TYPE (vuint32m1_t, 16, __rvv_uint32m1_t, uint32, RVVM1SI, _u32m1, _u32,
+ _e32m1)
+/* Define tuple types for SEW = 32, LMUL = M1. */
+DEF_RVV_TUPLE_TYPE (vint32m1x2_t, 17, __rvv_int32m1x2_t, vint32m1_t, int32, 2, _i32m1x2)
+DEF_RVV_TUPLE_TYPE (vuint32m1x2_t, 18, __rvv_uint32m1x2_t, vuint32m1_t, uint32, 2, _u32m1x2)
+DEF_RVV_TUPLE_TYPE (vint32m1x3_t, 17, __rvv_int32m1x3_t, vint32m1_t, int32, 3, _i32m1x3)
+DEF_RVV_TUPLE_TYPE (vuint32m1x3_t, 18, __rvv_uint32m1x3_t, vuint32m1_t, uint32, 3, _u32m1x3)
+DEF_RVV_TUPLE_TYPE (vint32m1x4_t, 17, __rvv_int32m1x4_t, vint32m1_t, int32, 4, _i32m1x4)
+DEF_RVV_TUPLE_TYPE (vuint32m1x4_t, 18, __rvv_uint32m1x4_t, vuint32m1_t, uint32, 4, _u32m1x4)
+DEF_RVV_TUPLE_TYPE (vint32m1x5_t, 17, __rvv_int32m1x5_t, vint32m1_t, int32, 5, _i32m1x5)
+DEF_RVV_TUPLE_TYPE (vuint32m1x5_t, 18, __rvv_uint32m1x5_t, vuint32m1_t, uint32, 5, _u32m1x5)
+DEF_RVV_TUPLE_TYPE (vint32m1x6_t, 17, __rvv_int32m1x6_t, vint32m1_t, int32, 6, _i32m1x6)
+DEF_RVV_TUPLE_TYPE (vuint32m1x6_t, 18, __rvv_uint32m1x6_t, vuint32m1_t, uint32, 6, _u32m1x6)
+DEF_RVV_TUPLE_TYPE (vint32m1x7_t, 17, __rvv_int32m1x7_t, vint32m1_t, int32, 7, _i32m1x7)
+DEF_RVV_TUPLE_TYPE (vuint32m1x7_t, 18, __rvv_uint32m1x7_t, vuint32m1_t, uint32, 7, _u32m1x7)
+DEF_RVV_TUPLE_TYPE (vint32m1x8_t, 17, __rvv_int32m1x8_t, vint32m1_t, int32, 8, _i32m1x8)
+DEF_RVV_TUPLE_TYPE (vuint32m1x8_t, 18, __rvv_uint32m1x8_t, vuint32m1_t, uint32, 8, _u32m1x8)
/* LMUL = 2:
- Machine mode = VNx4SImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx2SImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint32m2_t, 15, __rvv_int32m2_t, int32, VNx4SI, VNx2SI)
-DEF_RVV_TYPE (vuint32m2_t, 16, __rvv_uint32m2_t, unsigned_int32, VNx4SI, VNx2SI)
+ Machine mode = RVVM2SImode. */
+DEF_RVV_TYPE (vint32m2_t, 15, __rvv_int32m2_t, int32, RVVM2SI, _i32m2, _i32,
+ _e32m2)
+DEF_RVV_TYPE (vuint32m2_t, 16, __rvv_uint32m2_t, uint32, RVVM2SI, _u32m2, _u32,
+ _e32m2)
+/* Define tuple types for SEW = 32, LMUL = M2. */
+DEF_RVV_TUPLE_TYPE (vint32m2x2_t, 17, __rvv_int32m2x2_t, vint32m2_t, int32, 2, _i32m2x2)
+DEF_RVV_TUPLE_TYPE (vuint32m2x2_t, 18, __rvv_uint32m2x2_t, vuint32m2_t, uint32, 2, _u32m2x2)
+DEF_RVV_TUPLE_TYPE (vint32m2x3_t, 17, __rvv_int32m2x3_t, vint32m2_t, int32, 3, _i32m2x3)
+DEF_RVV_TUPLE_TYPE (vuint32m2x3_t, 18, __rvv_uint32m2x3_t, vuint32m2_t, uint32, 3, _u32m2x3)
+DEF_RVV_TUPLE_TYPE (vint32m2x4_t, 17, __rvv_int32m2x4_t, vint32m2_t, int32, 4, _i32m2x4)
+DEF_RVV_TUPLE_TYPE (vuint32m2x4_t, 18, __rvv_uint32m2x4_t, vuint32m2_t, uint32, 4, _u32m2x4)
/* LMUL = 4:
- Machine mode = VNx8SImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx4SImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint32m4_t, 15, __rvv_int32m4_t, int32, VNx8SI, VNx4SI)
-DEF_RVV_TYPE (vuint32m4_t, 16, __rvv_uint32m4_t, unsigned_int32, VNx8SI, VNx4SI)
+ Machine mode = RVVM4SImode. */
+DEF_RVV_TYPE (vint32m4_t, 15, __rvv_int32m4_t, int32, RVVM4SI, _i32m4, _i32,
+ _e32m4)
+DEF_RVV_TYPE (vuint32m4_t, 16, __rvv_uint32m4_t, uint32, RVVM4SI, _u32m4, _u32,
+ _e32m4)
+/* Define tuple types for SEW = 32, LMUL = M4. */
+DEF_RVV_TUPLE_TYPE (vint32m4x2_t, 17, __rvv_int32m4x2_t, vint32m4_t, int32, 2, _i32m4x2)
+DEF_RVV_TUPLE_TYPE (vuint32m4x2_t, 18, __rvv_uint32m4x2_t, vuint32m4_t, uint32, 2, _u32m4x2)
/* LMUL = 8:
- Machine mode = VNx16SImode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx8SImode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vint32m8_t, 15, __rvv_int32m8_t, int32, VNx16SI, VNx8SI)
-DEF_RVV_TYPE (vuint32m8_t, 16, __rvv_uint32m8_t, unsigned_int32, VNx16SI,
- VNx8SI)
+ Machine mode = RVVM8SImode. */
+DEF_RVV_TYPE (vint32m8_t, 15, __rvv_int32m8_t, int32, RVVM8SI, _i32m8, _i32,
+ _e32m8)
+DEF_RVV_TYPE (vuint32m8_t, 16, __rvv_uint32m8_t, uint32, RVVM8SI, _u32m8, _u32,
+ _e32m8)
/* SEW = 64:
- Disable when TARGET_MIN_VLEN > 32. */
-DEF_RVV_TYPE (vint64m1_t, 15, __rvv_int64m1_t, intDI, VNx1DI, VOID)
-DEF_RVV_TYPE (vuint64m1_t, 16, __rvv_uint64m1_t, unsigned_intDI, VNx1DI, VOID)
-DEF_RVV_TYPE (vint64m2_t, 15, __rvv_int64m2_t, intDI, VNx2DI, VOID)
-DEF_RVV_TYPE (vuint64m2_t, 16, __rvv_uint64m2_t, unsigned_intDI, VNx2DI, VOID)
-DEF_RVV_TYPE (vint64m4_t, 15, __rvv_int64m4_t, intDI, VNx4DI, VOID)
-DEF_RVV_TYPE (vuint64m4_t, 16, __rvv_uint64m4_t, unsigned_intDI, VNx4DI, VOID)
-DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, intDI, VNx8DI, VOID)
-DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, unsigned_intDI, VNx8DI, VOID)
+ Disable when !TARGET_VECTOR_ELEN_64. */
+DEF_RVV_TYPE (vint64m1_t, 15, __rvv_int64m1_t, int64, RVVM1DI, _i64m1, _i64,
+ _e64m1)
+DEF_RVV_TYPE (vuint64m1_t, 16, __rvv_uint64m1_t, uint64, RVVM1DI, _u64m1, _u64,
+ _e64m1)
+/* Define tuple types for SEW = 64, LMUL = M1. */
+DEF_RVV_TUPLE_TYPE (vint64m1x2_t, 17, __rvv_int64m1x2_t, vint64m1_t, int64, 2, _i64m1x2)
+DEF_RVV_TUPLE_TYPE (vuint64m1x2_t, 18, __rvv_uint64m1x2_t, vuint64m1_t, uint64, 2, _u64m1x2)
+DEF_RVV_TUPLE_TYPE (vint64m1x3_t, 17, __rvv_int64m1x3_t, vint64m1_t, int64, 3, _i64m1x3)
+DEF_RVV_TUPLE_TYPE (vuint64m1x3_t, 18, __rvv_uint64m1x3_t, vuint64m1_t, uint64, 3, _u64m1x3)
+DEF_RVV_TUPLE_TYPE (vint64m1x4_t, 17, __rvv_int64m1x4_t, vint64m1_t, int64, 4, _i64m1x4)
+DEF_RVV_TUPLE_TYPE (vuint64m1x4_t, 18, __rvv_uint64m1x4_t, vuint64m1_t, uint64, 4, _u64m1x4)
+DEF_RVV_TUPLE_TYPE (vint64m1x5_t, 17, __rvv_int64m1x5_t, vint64m1_t, int64, 5, _i64m1x5)
+DEF_RVV_TUPLE_TYPE (vuint64m1x5_t, 18, __rvv_uint64m1x5_t, vuint64m1_t, uint64, 5, _u64m1x5)
+DEF_RVV_TUPLE_TYPE (vint64m1x6_t, 17, __rvv_int64m1x6_t, vint64m1_t, int64, 6, _i64m1x6)
+DEF_RVV_TUPLE_TYPE (vuint64m1x6_t, 18, __rvv_uint64m1x6_t, vuint64m1_t, uint64, 6, _u64m1x6)
+DEF_RVV_TUPLE_TYPE (vint64m1x7_t, 17, __rvv_int64m1x7_t, vint64m1_t, int64, 7, _i64m1x7)
+DEF_RVV_TUPLE_TYPE (vuint64m1x7_t, 18, __rvv_uint64m1x7_t, vuint64m1_t, uint64, 7, _u64m1x7)
+DEF_RVV_TUPLE_TYPE (vint64m1x8_t, 17, __rvv_int64m1x8_t, vint64m1_t, int64, 8, _i64m1x8)
+DEF_RVV_TUPLE_TYPE (vuint64m1x8_t, 18, __rvv_uint64m1x8_t, vuint64m1_t, uint64, 8, _u64m1x8)
+DEF_RVV_TYPE (vint64m2_t, 15, __rvv_int64m2_t, int64, RVVM2DI, _i64m2, _i64,
+ _e64m2)
+DEF_RVV_TYPE (vuint64m2_t, 16, __rvv_uint64m2_t, uint64, RVVM2DI, _u64m2, _u64,
+ _e64m2)
+/* Define tuple types for SEW = 64, LMUL = M2. */
+DEF_RVV_TUPLE_TYPE (vint64m2x2_t, 17, __rvv_int64m2x2_t, vint64m2_t, int64, 2, _i64m2x2)
+DEF_RVV_TUPLE_TYPE (vuint64m2x2_t, 18, __rvv_uint64m2x2_t, vuint64m2_t, uint64, 2, _u64m2x2)
+DEF_RVV_TUPLE_TYPE (vint64m2x3_t, 17, __rvv_int64m2x3_t, vint64m2_t, int64, 3, _i64m2x3)
+DEF_RVV_TUPLE_TYPE (vuint64m2x3_t, 18, __rvv_uint64m2x3_t, vuint64m2_t, uint64, 3, _u64m2x3)
+DEF_RVV_TUPLE_TYPE (vint64m2x4_t, 17, __rvv_int64m2x4_t, vint64m2_t, int64, 4, _i64m2x4)
+DEF_RVV_TUPLE_TYPE (vuint64m2x4_t, 18, __rvv_uint64m2x4_t, vuint64m2_t, uint64, 4, _u64m2x4)
+DEF_RVV_TYPE (vint64m4_t, 15, __rvv_int64m4_t, int64, RVVM4DI, _i64m4, _i64,
+ _e64m4)
+DEF_RVV_TYPE (vuint64m4_t, 16, __rvv_uint64m4_t, uint64, RVVM4DI, _u64m4, _u64,
+ _e64m4)
+/* Define tuple types for SEW = 64, LMUL = M4. */
+DEF_RVV_TUPLE_TYPE (vint64m4x2_t, 17, __rvv_int64m4x2_t, vint64m4_t, int64, 2, _i64m4x2)
+DEF_RVV_TUPLE_TYPE (vuint64m4x2_t, 18, __rvv_uint64m4x2_t, vuint64m4_t, uint64, 2, _u64m4x2)
+DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, int64, RVVM8DI, _i64m8, _i64,
+ _e64m8)
+DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, RVVM8DI, _u64m8, _u64,
+ _e64m8)
+/* Enabled if TARGET_VECTOR_ELEN_FP_16 && (TARGET_ZVFH or TARGET_ZVFHMIN). */
+/* LMUL = 1/4. */
+DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, RVVMF4HF, _f16mf4,
+ _f16, _e16mf4)
+/* Define tuple types for SEW = 16, LMUL = MF4. */
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x2_t, 20, __rvv_float16mf4x2_t, vfloat16mf4_t, float16, 2, _f16mf4x2)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x3_t, 20, __rvv_float16mf4x3_t, vfloat16mf4_t, float16, 3, _f16mf4x3)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x4_t, 20, __rvv_float16mf4x4_t, vfloat16mf4_t, float16, 4, _f16mf4x4)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x5_t, 20, __rvv_float16mf4x5_t, vfloat16mf4_t, float16, 5, _f16mf4x5)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x6_t, 20, __rvv_float16mf4x6_t, vfloat16mf4_t, float16, 6, _f16mf4x6)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x7_t, 20, __rvv_float16mf4x7_t, vfloat16mf4_t, float16, 7, _f16mf4x7)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x8_t, 20, __rvv_float16mf4x8_t, vfloat16mf4_t, float16, 8, _f16mf4x8)
+/* LMUL = 1/2. */
+DEF_RVV_TYPE (vfloat16mf2_t, 18, __rvv_float16mf2_t, float16, RVVMF2HF, _f16mf2,
+ _f16, _e16mf2)
+/* Define tuple types for SEW = 16, LMUL = MF2. */
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x2_t, 20, __rvv_float16mf2x2_t, vfloat16mf2_t, float16, 2, _f16mf2x2)
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x3_t, 20, __rvv_float16mf2x3_t, vfloat16mf2_t, float16, 3, _f16mf2x3)
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x4_t, 20, __rvv_float16mf2x4_t, vfloat16mf2_t, float16, 4, _f16mf2x4)
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x5_t, 20, __rvv_float16mf2x5_t, vfloat16mf2_t, float16, 5, _f16mf2x5)
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x6_t, 20, __rvv_float16mf2x6_t, vfloat16mf2_t, float16, 6, _f16mf2x6)
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x7_t, 20, __rvv_float16mf2x7_t, vfloat16mf2_t, float16, 7, _f16mf2x7)
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x8_t, 20, __rvv_float16mf2x8_t, vfloat16mf2_t, float16, 8, _f16mf2x8)
+/* LMUL = 1. */
+DEF_RVV_TYPE (vfloat16m1_t, 17, __rvv_float16m1_t, float16, RVVM1HF, _f16m1,
+ _f16, _e16m1)
+/* Define tuple types for SEW = 16, LMUL = M1. */
+DEF_RVV_TUPLE_TYPE (vfloat16m1x2_t, 19, __rvv_float16m1x2_t, vfloat16m1_t, float16, 2, _f16m1x2)
+DEF_RVV_TUPLE_TYPE (vfloat16m1x3_t, 19, __rvv_float16m1x3_t, vfloat16m1_t, float16, 3, _f16m1x3)
+DEF_RVV_TUPLE_TYPE (vfloat16m1x4_t, 19, __rvv_float16m1x4_t, vfloat16m1_t, float16, 4, _f16m1x4)
+DEF_RVV_TUPLE_TYPE (vfloat16m1x5_t, 19, __rvv_float16m1x5_t, vfloat16m1_t, float16, 5, _f16m1x5)
+DEF_RVV_TUPLE_TYPE (vfloat16m1x6_t, 19, __rvv_float16m1x6_t, vfloat16m1_t, float16, 6, _f16m1x6)
+DEF_RVV_TUPLE_TYPE (vfloat16m1x7_t, 19, __rvv_float16m1x7_t, vfloat16m1_t, float16, 7, _f16m1x7)
+DEF_RVV_TUPLE_TYPE (vfloat16m1x8_t, 19, __rvv_float16m1x8_t, vfloat16m1_t, float16, 8, _f16m1x8)
+/* LMUL = 2. */
+DEF_RVV_TYPE (vfloat16m2_t, 17, __rvv_float16m2_t, float16, RVVM2HF, _f16m2,
+ _f16, _e16m2)
+/* Define tuple types for SEW = 16, LMUL = M2. */
+DEF_RVV_TUPLE_TYPE (vfloat16m2x2_t, 19, __rvv_float16m2x2_t, vfloat16m2_t, float16, 2, _f16m2x2)
+DEF_RVV_TUPLE_TYPE (vfloat16m2x3_t, 19, __rvv_float16m2x3_t, vfloat16m2_t, float16, 3, _f16m2x3)
+DEF_RVV_TUPLE_TYPE (vfloat16m2x4_t, 19, __rvv_float16m2x4_t, vfloat16m2_t, float16, 4, _f16m2x4)
+/* LMUL = 4. */
+DEF_RVV_TYPE (vfloat16m4_t, 17, __rvv_float16m4_t, float16, RVVM4HF, _f16m4,
+ _f16, _e16m4)
+/* Define tuple types for SEW = 16, LMUL = M4. */
+DEF_RVV_TUPLE_TYPE (vfloat16m4x2_t, 19, __rvv_float16m4x2_t, vfloat16m4_t, float16, 2, _f16m4x2)
+/* LMUL = 8. */
+DEF_RVV_TYPE (vfloat16m8_t, 16, __rvv_float16m8_t, float16, RVVM8HF, _f16m8,
+ _f16, _e16m8)
+
+/* Disable all when !TARGET_VECTOR_ELEN_FP_32. */
/* LMUL = 1/2:
- Only enble when TARGET_MIN_VLEN > 32 and machine mode = VNx1SFmode. */
-DEF_RVV_TYPE (vfloat32mf2_t, 18, __rvv_float32mf2_t, float, VNx1SF, VOID)
+ Only enble when TARGET_MIN_VLEN > 32.
+ Machine mode = RVVMF2SFmode. */
+DEF_RVV_TYPE (vfloat32mf2_t, 18, __rvv_float32mf2_t, float, RVVMF2SF, _f32mf2,
+ _f32, _e32mf2)
+/* Define tuple types for SEW = 32, LMUL = MF2. */
+DEF_RVV_TUPLE_TYPE (vfloat32mf2x2_t, 20, __rvv_float32mf2x2_t, vfloat32mf2_t, float, 2, _f32mf2x2)
+DEF_RVV_TUPLE_TYPE (vfloat32mf2x3_t, 20, __rvv_float32mf2x3_t, vfloat32mf2_t, float, 3, _f32mf2x3)
+DEF_RVV_TUPLE_TYPE (vfloat32mf2x4_t, 20, __rvv_float32mf2x4_t, vfloat32mf2_t, float, 4, _f32mf2x4)
+DEF_RVV_TUPLE_TYPE (vfloat32mf2x5_t, 20, __rvv_float32mf2x5_t, vfloat32mf2_t, float, 5, _f32mf2x5)
+DEF_RVV_TUPLE_TYPE (vfloat32mf2x6_t, 20, __rvv_float32mf2x6_t, vfloat32mf2_t, float, 6, _f32mf2x6)
+DEF_RVV_TUPLE_TYPE (vfloat32mf2x7_t, 20, __rvv_float32mf2x7_t, vfloat32mf2_t, float, 7, _f32mf2x7)
+DEF_RVV_TUPLE_TYPE (vfloat32mf2x8_t, 20, __rvv_float32mf2x8_t, vfloat32mf2_t, float, 8, _f32mf2x8)
/* LMUL = 1:
- Machine mode = VNx2SFmode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx1SFmode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vfloat32m1_t, 17, __rvv_float32m1_t, float, VNx2SF, VNx1SF)
+ Machine mode = RVVM1SFmode. */
+DEF_RVV_TYPE (vfloat32m1_t, 17, __rvv_float32m1_t, float, RVVM1SF, _f32m1, _f32,
+ _e32m1)
+/* Define tuple types for SEW = 32, LMUL = M1. */
+DEF_RVV_TUPLE_TYPE (vfloat32m1x2_t, 19, __rvv_float32m1x2_t, vfloat32m1_t, float, 2, _f32m1x2)
+DEF_RVV_TUPLE_TYPE (vfloat32m1x3_t, 19, __rvv_float32m1x3_t, vfloat32m1_t, float, 3, _f32m1x3)
+DEF_RVV_TUPLE_TYPE (vfloat32m1x4_t, 19, __rvv_float32m1x4_t, vfloat32m1_t, float, 4, _f32m1x4)
+DEF_RVV_TUPLE_TYPE (vfloat32m1x5_t, 19, __rvv_float32m1x5_t, vfloat32m1_t, float, 5, _f32m1x5)
+DEF_RVV_TUPLE_TYPE (vfloat32m1x6_t, 19, __rvv_float32m1x6_t, vfloat32m1_t, float, 6, _f32m1x6)
+DEF_RVV_TUPLE_TYPE (vfloat32m1x7_t, 19, __rvv_float32m1x7_t, vfloat32m1_t, float, 7, _f32m1x7)
+DEF_RVV_TUPLE_TYPE (vfloat32m1x8_t, 19, __rvv_float32m1x8_t, vfloat32m1_t, float, 8, _f32m1x8)
/* LMUL = 2:
- Machine mode = VNx4SFmode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx2SFmode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vfloat32m2_t, 17, __rvv_float32m2_t, float, VNx4SF, VNx2SF)
+ Machine mode = RVVM2SFmode. */
+DEF_RVV_TYPE (vfloat32m2_t, 17, __rvv_float32m2_t, float, RVVM2SF, _f32m2, _f32,
+ _e32m2)
+/* Define tuple types for SEW = 32, LMUL = M2. */
+DEF_RVV_TUPLE_TYPE (vfloat32m2x2_t, 19, __rvv_float32m2x2_t, vfloat32m2_t, float, 2, _f32m2x2)
+DEF_RVV_TUPLE_TYPE (vfloat32m2x3_t, 19, __rvv_float32m2x3_t, vfloat32m2_t, float, 3, _f32m2x3)
+DEF_RVV_TUPLE_TYPE (vfloat32m2x4_t, 19, __rvv_float32m2x4_t, vfloat32m2_t, float, 4, _f32m2x4)
/* LMUL = 4:
- Machine mode = VNx8SFmode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx4SFmode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vfloat32m4_t, 17, __rvv_float32m4_t, float, VNx8SF, VNx4SF)
+ Machine mode = RVVM4SFmode. */
+DEF_RVV_TYPE (vfloat32m4_t, 17, __rvv_float32m4_t, float, RVVM4SF, _f32m4, _f32,
+ _e32m4)
+/* Define tuple types for SEW = 32, LMUL = M4. */
+DEF_RVV_TUPLE_TYPE (vfloat32m4x2_t, 19, __rvv_float32m4x2_t, vfloat32m4_t, float, 2, _f32m4x2)
/* LMUL = 8:
- Machine mode = VNx16SFmode when TARGET_MIN_VLEN > 32.
- Machine mode = VNx8SFmode when TARGET_MIN_VLEN = 32. */
-DEF_RVV_TYPE (vfloat32m8_t, 17, __rvv_float32m8_t, float, VNx16SF, VNx8SF)
+ Machine mode = RVVM8SFmode. */
+DEF_RVV_TYPE (vfloat32m8_t, 17, __rvv_float32m8_t, float, RVVM8SF, _f32m8, _f32,
+ _e32m8)
/* SEW = 64:
- Disable when TARGET_VECTOR_FP64. */
-DEF_RVV_TYPE (vfloat64m1_t, 17, __rvv_float64m1_t, double, VNx1DF, VOID)
-DEF_RVV_TYPE (vfloat64m2_t, 17, __rvv_float64m2_t, double, VNx2DF, VOID)
-DEF_RVV_TYPE (vfloat64m4_t, 17, __rvv_float64m4_t, double, VNx4DF, VOID)
-DEF_RVV_TYPE (vfloat64m8_t, 17, __rvv_float64m8_t, double, VNx8DF, VOID)
+ Disable when !TARGET_VECTOR_ELEN_FP_64. */
+DEF_RVV_TYPE (vfloat64m1_t, 17, __rvv_float64m1_t, double, RVVM1DF, _f64m1,
+ _f64, _e64m1)
+/* Define tuple types for SEW = 64, LMUL = M1. */
+DEF_RVV_TUPLE_TYPE (vfloat64m1x2_t, 19, __rvv_float64m1x2_t, vfloat64m1_t, double, 2, _f64m1x2)
+DEF_RVV_TUPLE_TYPE (vfloat64m1x3_t, 19, __rvv_float64m1x3_t, vfloat64m1_t, double, 3, _f64m1x3)
+DEF_RVV_TUPLE_TYPE (vfloat64m1x4_t, 19, __rvv_float64m1x4_t, vfloat64m1_t, double, 4, _f64m1x4)
+DEF_RVV_TUPLE_TYPE (vfloat64m1x5_t, 19, __rvv_float64m1x5_t, vfloat64m1_t, double, 5, _f64m1x5)
+DEF_RVV_TUPLE_TYPE (vfloat64m1x6_t, 19, __rvv_float64m1x6_t, vfloat64m1_t, double, 6, _f64m1x6)
+DEF_RVV_TUPLE_TYPE (vfloat64m1x7_t, 19, __rvv_float64m1x7_t, vfloat64m1_t, double, 7, _f64m1x7)
+DEF_RVV_TUPLE_TYPE (vfloat64m1x8_t, 19, __rvv_float64m1x8_t, vfloat64m1_t, double, 8, _f64m1x8)
+DEF_RVV_TYPE (vfloat64m2_t, 17, __rvv_float64m2_t, double, RVVM2DF, _f64m2,
+ _f64, _e64m2)
+/* Define tuple types for SEW = 64, LMUL = M2. */
+DEF_RVV_TUPLE_TYPE (vfloat64m2x2_t, 19, __rvv_float64m2x2_t, vfloat64m2_t, double, 2, _f64m2x2)
+DEF_RVV_TUPLE_TYPE (vfloat64m2x3_t, 19, __rvv_float64m2x3_t, vfloat64m2_t, double, 3, _f64m2x3)
+DEF_RVV_TUPLE_TYPE (vfloat64m2x4_t, 19, __rvv_float64m2x4_t, vfloat64m2_t, double, 4, _f64m2x4)
+DEF_RVV_TYPE (vfloat64m4_t, 17, __rvv_float64m4_t, double, RVVM4DF, _f64m4,
+ _f64, _e64m4)
+/* Define tuple types for SEW = 64, LMUL = M4. */
+DEF_RVV_TUPLE_TYPE (vfloat64m4x2_t, 19, __rvv_float64m4x2_t, vfloat64m4_t, double, 2, _f64m4x2)
+DEF_RVV_TYPE (vfloat64m8_t, 17, __rvv_float64m8_t, double, RVVM8DF, _f64m8,
+ _f64, _e64m8)
+
+DEF_RVV_OP_TYPE (vv)
+DEF_RVV_OP_TYPE (vx)
+DEF_RVV_OP_TYPE (v)
+DEF_RVV_OP_TYPE (wv)
+DEF_RVV_OP_TYPE (wx)
+DEF_RVV_OP_TYPE (x_v)
+DEF_RVV_OP_TYPE (vf2)
+DEF_RVV_OP_TYPE (vf4)
+DEF_RVV_OP_TYPE (vf8)
+DEF_RVV_OP_TYPE (vvm)
+DEF_RVV_OP_TYPE (vxm)
+DEF_RVV_OP_TYPE (x_w)
+DEF_RVV_OP_TYPE (x)
+DEF_RVV_OP_TYPE (vs)
+DEF_RVV_OP_TYPE (mm)
+DEF_RVV_OP_TYPE (m)
+DEF_RVV_OP_TYPE (vf)
+DEF_RVV_OP_TYPE (vm)
+DEF_RVV_OP_TYPE (wf)
+DEF_RVV_OP_TYPE (vfm)
+DEF_RVV_OP_TYPE (f)
+DEF_RVV_OP_TYPE (f_v)
+DEF_RVV_OP_TYPE (xu_v)
+DEF_RVV_OP_TYPE (f_w)
+DEF_RVV_OP_TYPE (xu_w)
+DEF_RVV_OP_TYPE (s)
+
+DEF_RVV_PRED_TYPE (ta)
+DEF_RVV_PRED_TYPE (tu)
+DEF_RVV_PRED_TYPE (ma)
+DEF_RVV_PRED_TYPE (mu)
+DEF_RVV_PRED_TYPE (tama)
+DEF_RVV_PRED_TYPE (tamu)
+DEF_RVV_PRED_TYPE (tuma)
+DEF_RVV_PRED_TYPE (tumu)
+DEF_RVV_PRED_TYPE (m)
+DEF_RVV_PRED_TYPE (tam)
+DEF_RVV_PRED_TYPE (tum)
+
+DEF_RVV_BASE_TYPE (vector, builtin_types[type_idx].vector)
+DEF_RVV_BASE_TYPE (scalar, builtin_types[type_idx].scalar)
+DEF_RVV_BASE_TYPE (mask, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (signed_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (unsigned_vector, get_vector_type (type_idx))
+/* According to riscv-vector-builtins-types.def, the unsigned
+ type is always the signed type + 1 (They have same SEW and LMUL).
+ For example 'vuint8mf8_t' enum = 'vint8mf8_t' enum + 1.
+ Note: We dont't allow type_idx to be unsigned type. */
+DEF_RVV_BASE_TYPE (unsigned_scalar, builtin_types[type_idx + 1].scalar)
+DEF_RVV_BASE_TYPE (vector_ptr, builtin_types[type_idx].vector_ptr)
+/* According to the latest rvv-intrinsic-doc, it defines vsm.v intrinsic:
+ __riscv_vsm (uint8_t *base, vbool1_t value, size_t vl). */
+DEF_RVV_BASE_TYPE (scalar_ptr, get_scalar_ptr_type (type_idx))
+/* According to the latest rvv-intrinsic-doc, it defines vlm.v intrinsic:
+ __riscv_vlm_v_b1 (const uint8_t *base, size_t vl). */
+DEF_RVV_BASE_TYPE (scalar_const_ptr, get_scalar_const_ptr_type (type_idx))
+DEF_RVV_BASE_TYPE (void, void_type_node)
+DEF_RVV_BASE_TYPE (size, size_type_node)
+DEF_RVV_BASE_TYPE (ptrdiff, ptrdiff_type_node)
+DEF_RVV_BASE_TYPE (unsigned_long, long_unsigned_type_node)
+DEF_RVV_BASE_TYPE (long, long_integer_type_node)
+DEF_RVV_BASE_TYPE (eew8_index, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (eew16_index, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (eew32_index, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (eew64_index, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (shift_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (double_trunc_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (quad_trunc_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (oct_trunc_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (double_trunc_scalar, get_scalar_type (type_idx))
+DEF_RVV_BASE_TYPE (double_trunc_signed_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (double_trunc_unsigned_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (double_trunc_unsigned_scalar, get_scalar_type (type_idx))
+DEF_RVV_BASE_TYPE (double_trunc_float_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (float_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (lmul1_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (widen_lmul1_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (eew8_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (eew16_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (eew32_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (eew64_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool1_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool2_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool4_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool8_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool16_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool32_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool64_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (signed_eew8_lmul1_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (signed_eew16_lmul1_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (signed_eew32_lmul1_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (signed_eew64_lmul1_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (unsigned_eew8_lmul1_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (unsigned_eew16_lmul1_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (unsigned_eew32_lmul1_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (unsigned_eew64_lmul1_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (vlmul_ext_x2, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (vlmul_ext_x4, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (vlmul_ext_x8, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (vlmul_ext_x16, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (vlmul_ext_x32, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (vlmul_ext_x64, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (size_ptr, build_pointer_type (size_type_node))
+DEF_RVV_BASE_TYPE (tuple_subpart, get_tuple_subpart_type (type_idx))
+
+DEF_RVV_VXRM_ENUM (RNU, VXRM_RNU)
+DEF_RVV_VXRM_ENUM (RNE, VXRM_RNE)
+DEF_RVV_VXRM_ENUM (RDN, VXRM_RDN)
+DEF_RVV_VXRM_ENUM (ROD, VXRM_ROD)
+
+DEF_RVV_FRM_ENUM (RNE, FRM_RNE)
+DEF_RVV_FRM_ENUM (RTZ, FRM_RTZ)
+DEF_RVV_FRM_ENUM (RDN, FRM_RDN)
+DEF_RVV_FRM_ENUM (RUP, FRM_RUP)
+DEF_RVV_FRM_ENUM (RMM, FRM_RMM)
+
+#include "riscv-vector-type-indexer.gen.def"
+#undef DEF_RVV_PRED_TYPE
+#undef DEF_RVV_OP_TYPE
#undef DEF_RVV_TYPE
+#undef DEF_RVV_TUPLE_TYPE
+#undef DEF_RVV_BASE_TYPE
+#undef DEF_RVV_TYPE_INDEX
+#undef DEF_RVV_VXRM_ENUM
+#undef DEF_RVV_FRM_ENUM
projects / thirdparty / gcc.git / blobdiff