RISC-V: Add interrupt attribute modes.

[thirdparty/gcc.git] / gcc / config / riscv / riscv.md

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b9faf00d076eb625f30876831ce961a595beb7a0..a5940dcc4253edfdca937d786700cf2e86b99763 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -58,6 +58,8 @@
 
   ;; Interrupt handler instructions.
   UNSPECV_MRET
+  UNSPECV_SRET
+  UNSPECV_URET
 
   ;; Blockage and synchronization.
   UNSPECV_BLOCKAGE
@@ -2298,6 +2300,16 @@
   ""
   "mret")
 
+(define_insn "riscv_sret"
+  [(unspec_volatile [(const_int 0)] UNSPECV_SRET)]
+  ""
+  "sret")
+
+(define_insn "riscv_uret"
+  [(unspec_volatile [(const_int 0)] UNSPECV_URET)]
+  ""
+  "uret")
+
 (define_insn "stack_tie<mode>"
   [(set (mem:BLK (scratch))
        (unspec:BLK [(match_operand:X 0 "register_operand" "r")