Update copyright years.

[thirdparty/gcc.git] / gcc / config / rs6000 / e6500.md

diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md
index b84f7038b18d5bc351f4e8015a12872c6ce13fd1..2f0eec67a267222fa73a8a6425b0d39b5ea5cbe7 100644 (file)
--- a/gcc/config/rs6000/e6500.md
+++ b/gcc/config/rs6000/e6500.md
@@ -1,5 +1,5 @@
 ;; Pipeline description for Freescale PowerPC e6500 core.
-;;   Copyright (C) 2012-2014 Free Software Foundation, Inc.
+;;   Copyright (C) 2012-2024 Free Software Foundation, Inc.
 ;;   Contributed by Edmar Wienskoski (edmar@freescale.com)
 ;;
 ;; This file is part of GCC.
@@ -59,18 +59,28 @@
 
 ;; SFX.
 (define_insn_reservation "e6500_sfx" 1
-  (and (eq_attr "type" "integer,insert,delayed_compare,\
-       shift,cntlz,exts")
+  (and (ior (eq_attr "type" "integer,insert,cntlz")
+           (and (eq_attr "type" "add,logical,exts")
+                (eq_attr "dot"  "no"))
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot"  "no")
+                (eq_attr "var_shift" "no")))
        (eq_attr "cpu" "ppce6500"))
   "e6500_decode,e6500_sfx")
 
 (define_insn_reservation "e6500_sfx2" 2
-  (and (eq_attr "type" "cmp,compare,fast_compare,trap")
+  (and (ior (eq_attr "type" "cmp,trap")
+           (and (eq_attr "type" "add,logical,exts")
+                (eq_attr "dot"  "yes"))
+           (and (eq_attr "type" "shift")
+                (eq_attr "dot"  "yes")
+                (eq_attr "var_shift" "no")))
        (eq_attr "cpu" "ppce6500"))
   "e6500_decode,e6500_sfx")
 
 (define_insn_reservation "e6500_delayed" 2
-  (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
+  (and (eq_attr "type" "shift")
+       (eq_attr "var_shift" "yes")
        (eq_attr "cpu" "ppce6500"))
   "e6500_decode,e6500_sfx*2")
 
@@ -120,13 +130,15 @@
 
 ;; CFX - Divide.
 (define_insn_reservation "e6500_divide" 16
-  (and (eq_attr "type" "idiv")
+  (and (eq_attr "type" "div")
+       (eq_attr "size" "32")
        (eq_attr "cpu" "ppce6500"))
   "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
    e6500_cfx_div*15")
 
 (define_insn_reservation "e6500_divide_d" 26
-  (and (eq_attr "type" "ldiv")
+  (and (eq_attr "type" "div")
+       (eq_attr "size" "64")
        (eq_attr "cpu" "ppce6500"))
   "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
    e6500_cfx_div*25")
@@ -187,13 +199,13 @@
 
 ;; BU - CR logical.
 (define_insn_reservation "e6500_cr_logical" 1
-  (and (eq_attr "type" "cr_logical,delayed_cr")
+  (and (eq_attr "type" "cr_logical")
        (eq_attr "cpu" "ppce6500"))
   "e6500_decode,e6500_bu")
 
 ;; VSFX.
 (define_insn_reservation "e6500_vecsimple" 1
-  (and (eq_attr "type" "vecsimple,veccmp")
+  (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
        (eq_attr "cpu" "ppce6500"))
   "e6500_decode,e6500_vec")