;; Pipeline description for Freescale PowerPC e6500 core.
-;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
+;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
;; Contributed by Edmar Wienskoski (edmar@freescale.com)
;;
;; This file is part of GCC.
;; SFX.
(define_insn_reservation "e6500_sfx" 1
- (and (ior (eq_attr "type" "integer,insert,cntlz,exts")
- (and (eq_attr "type" "add,logical")
+ (and (ior (eq_attr "type" "integer,insert,cntlz")
+ (and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
(define_insn_reservation "e6500_sfx2" 2
- (and (ior (eq_attr "type" "cmp,compare,trap")
- (and (eq_attr "type" "add,logical")
- (eq_attr "dot" "yes")))
+ (and (ior (eq_attr "type" "cmp,trap")
+ (and (eq_attr "type" "add,logical,exts")
+ (eq_attr "dot" "yes"))
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")
+ (eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
;; BU - CR logical.
(define_insn_reservation "e6500_cr_logical" 1
- (and (eq_attr "type" "cr_logical,delayed_cr")
+ (and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_bu")
;; VSFX.
(define_insn_reservation "e6500_vecsimple" 1
- (and (eq_attr "type" "vecsimple,veccmp")
+ (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_vec")