;; Scheduling description for Motorola PowerPC processor cores.
-;; Copyright (C) 2003-2014 Free Software Foundation, Inc.
+;; Copyright (C) 2003-2020 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
"lsu_mpc")
(define_insn_reservation "mpccore-integer" 1
- (and (eq_attr "type" "integer,insert,shift,trap,\
- var_shift_rotate,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
+ (and (eq_attr "type" "add,logical,shift,exts")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "mpccore"))
"iu_mpc")
"mciu_mpc*6")
(define_insn_reservation "mpccore-compare" 3
- (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
- var_delayed_compare")
+ (and (ior (eq_attr "type" "cmp")
+ (and (eq_attr "type" "add,logical,shift,exts")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "mpccore"))
"iu_mpc,nothing,bpu_mpc")
"fpu_mpc,bpu_mpc")
(define_insn_reservation "mpccore-fp" 4
- (and (eq_attr "type" "fp")
+ (and (eq_attr "type" "fp,fpsimple")
(eq_attr "cpu" "mpccore"))
"fpu_mpc*2")
"bpu_mpc")
(define_insn_reservation "mpccore-jmpreg" 1
- (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr,isync")
+ (and (eq_attr "type" "jmpreg,branch,cr_logical,mfcr,mtcr,isync")
(eq_attr "cpu" "mpccore"))
"bpu_mpc")