Update copyright years.

[thirdparty/gcc.git] / gcc / config / rs6000 / power5.md

diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md
index 5df009e45207deb5bda892788e10608cbb15c277..d406d5f4ce619cd2df73e62915da3c9d77a9870b 100644 (file)
--- a/gcc/config/rs6000/power5.md
+++ b/gcc/config/rs6000/power5.md
@@ -1,5 +1,5 @@
 ;; Scheduling description for IBM POWER5 processor.
-;;   Copyright (C) 2003-2014 Free Software Foundation, Inc.
+;;   Copyright (C) 2003-2020 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
@@ -166,8 +166,8 @@
 
 ; Integer latency is 2 cycles
 (define_insn_reservation "power5-integer" 2
-  (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel,popcnt")
-           (and (eq_attr "type" "add,shift")
+  (and (ior (eq_attr "type" "integer,trap,cntlz,isel,popcnt")
+           (and (eq_attr "type" "add,logical,shift,exts")
                 (eq_attr "dot" "no"))
            (and (eq_attr "type" "insert")
                 (eq_attr "size" "64")))
@@ -203,16 +203,15 @@
   "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
 
 (define_insn_reservation "power5-cmp" 3
-  (and (ior (eq_attr "type" "cmp,fast_compare")
-           (and (eq_attr "type" "add")
+  (and (ior (eq_attr "type" "cmp")
+           (and (eq_attr "type" "add,logical")
                 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "power5"))
   "iq_power5")
 
 (define_insn_reservation "power5-compare" 2
-  (and (ior (eq_attr "type" "compare")
-           (and (eq_attr "type" "shift")
-                (eq_attr "dot" "yes")))
+  (and (eq_attr "type" "shift,exts")
+       (eq_attr "dot" "yes")
        (eq_attr "cpu" "power5"))
   "du1_power5+du2_power5,iu1_power5,iu2_power5")
 
@@ -293,11 +292,13 @@
 ; Condition Register logical ops are split if non-destructive (RT != RB)
 (define_insn_reservation "power5-crlogical" 2
   (and (eq_attr "type" "cr_logical")
+       (eq_attr "cr_logical_3op" "no")
        (eq_attr "cpu" "power5"))
   "du1_power5,cru_power5")
 
 (define_insn_reservation "power5-delayedcr" 4
-  (and (eq_attr "type" "delayed_cr")
+  (and (eq_attr "type" "cr_logical")
+       (eq_attr "cr_logical_3op" "yes")
        (eq_attr "cpu" "power5"))
   "du1_power5+du2_power5,cru_power5,cru_power5")
 
@@ -323,7 +324,7 @@
 
 ; Basic FP latency is 6 cycles
 (define_insn_reservation "power5-fp" 6
-  (and (eq_attr "type" "fp,dmul")
+  (and (eq_attr "type" "fp,fpsimple,dmul")
        (eq_attr "cpu" "power5"))
   "fpq_power5")