Update copyright years.

[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000-cpus.def

diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index ccc0eb128edd717f94ae6170987ce92ef2e7f525..83604b65cef8eadae5261ef74c1725971e8051c5 100644 (file)
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -1,5 +1,5 @@
 /* IBM RS/6000 CPU names..
-   Copyright (C) 1991-2018 Free Software Foundation, Inc.
+   Copyright (C) 1991-2020 Free Software Foundation, Inc.
    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
 
    This file is part of GCC.
@@ -24,10 +24,9 @@
 #define ISA_2_2_MASKS          (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
 #define ISA_2_4_MASKS          (ISA_2_2_MASKS | OPTION_MASK_FPRND)
 
-  /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
-     ALTIVEC, since in general it isn't a win on power6.  In ISA 2.04, fsel,
-     fre, fsqrt, etc. were no longer documented as optional.  Group masks by
-     server and embedded. */
+  /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
+     power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
+     as optional.  Group masks by server and embedded. */
 #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS                          \
                                 | OPTION_MASK_CMPB                     \
                                 | OPTION_MASK_RECIP_PRECISION          \
@@ -44,9 +43,10 @@
                                 | OPTION_MASK_ALTIVEC                  \
                                 | OPTION_MASK_VSX)
 
-/* For now, don't provide an embedded version of ISA 2.07.  */
+/* For now, don't provide an embedded version of ISA 2.07.  Do not set power8
+   fusion here, instead set it in rs6000.c if we are tuning for a power8
+   system.  */
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER                   \
-                                | OPTION_MASK_P8_FUSION                \
                                 | OPTION_MASK_P8_VECTOR                \
                                 | OPTION_MASK_CRYPTO                   \
                                 | OPTION_MASK_DIRECT_MOVE              \
@@ -55,22 +55,35 @@
                                 | OPTION_MASK_QUAD_MEMORY              \
                                 | OPTION_MASK_QUAD_MEMORY_ATOMIC)
 
+/* ISA masks setting fusion options.  */
+#define OTHER_FUSION_MASKS     (OPTION_MASK_P8_FUSION                  \
+                                | OPTION_MASK_P8_FUSION_SIGN)
+
 /* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
    FLOAT128_HW here until we are ready to make -mfloat128 on by default.  */
-#define ISA_3_0_MASKS_SERVER   (ISA_2_7_MASKS_SERVER                   \
-                                | OPTION_MASK_ISEL                     \
-                                | OPTION_MASK_MODULO                   \
-                                | OPTION_MASK_P9_FUSION                \
-                                | OPTION_MASK_P9_MINMAX                \
-                                | OPTION_MASK_P9_MISC                  \
-                                | OPTION_MASK_P9_VECTOR)
+#define ISA_3_0_MASKS_SERVER   ((ISA_2_7_MASKS_SERVER                  \
+                                 | OPTION_MASK_ISEL                    \
+                                 | OPTION_MASK_MODULO                  \
+                                 | OPTION_MASK_P9_MINMAX               \
+                                 | OPTION_MASK_P9_MISC                 \
+                                 | OPTION_MASK_P9_VECTOR)              \
+                                & ~OTHER_FUSION_MASKS)
 
 /* Support for the IEEE 128-bit floating point hardware requires a lot of the
    VSX instructions that are part of ISA 3.0.  */
 #define ISA_3_0_MASKS_IEEE     (OPTION_MASK_VSX                        \
                                 | OPTION_MASK_P8_VECTOR                \
-                                | OPTION_MASK_P9_VECTOR                \
-                                | OPTION_MASK_DIRECT_MOVE)
+                                | OPTION_MASK_P9_VECTOR)
+
+/* Support for a future processor's features.  Do not enable -mpcrel until it
+   is fully functional.  */
+#define ISA_FUTURE_MASKS_SERVER        (ISA_3_0_MASKS_SERVER                   \
+                                | OPTION_MASK_FUTURE                   \
+                                | OPTION_MASK_PREFIXED_ADDR)
+
+/* Flags that need to be turned off if -mno-future.  */
+#define OTHER_FUTURE_MASKS     (OPTION_MASK_PCREL                      \
+                                | OPTION_MASK_PREFIXED_ADDR)
 
 /* Flags that need to be turned off if -mno-power9-vector.  */
 #define OTHER_P9_VECTOR_MASKS  (OPTION_MASK_FLOAT128_HW                \
@@ -112,24 +125,25 @@
                                 | OPTION_MASK_FLOAT128_HW              \
                                 | OPTION_MASK_FLOAT128_KEYWORD         \
                                 | OPTION_MASK_FPRND                    \
+                                | OPTION_MASK_FUTURE                   \
                                 | OPTION_MASK_HTM                      \
                                 | OPTION_MASK_ISEL                     \
                                 | OPTION_MASK_MFCRF                    \
-                                | OPTION_MASK_MFPGPR                   \
                                 | OPTION_MASK_MODULO                   \
                                 | OPTION_MASK_MULHW                    \
                                 | OPTION_MASK_NO_UPDATE                \
                                 | OPTION_MASK_P8_FUSION                \
                                 | OPTION_MASK_P8_VECTOR                \
-                                | OPTION_MASK_P9_FUSION                \
                                 | OPTION_MASK_P9_MINMAX                \
                                 | OPTION_MASK_P9_MISC                  \
                                 | OPTION_MASK_P9_VECTOR                \
+                                | OPTION_MASK_PCREL                    \
                                 | OPTION_MASK_POPCNTB                  \
                                 | OPTION_MASK_POPCNTD                  \
                                 | OPTION_MASK_POWERPC64                \
                                 | OPTION_MASK_PPC_GFXOPT               \
                                 | OPTION_MASK_PPC_GPOPT                \
+                                | OPTION_MASK_PREFIXED_ADDR            \
                                 | OPTION_MASK_QUAD_MEMORY              \
                                 | OPTION_MASK_QUAD_MEMORY_ATOMIC       \
                                 | OPTION_MASK_RECIP_PRECISION          \
@@ -220,7 +234,7 @@ RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
            | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
 RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
            | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
-           | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
+           | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
 RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
 RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
 RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
@@ -228,3 +242,5 @@ RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
 RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
 RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
 RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64
+           | ISA_FUTURE_MASKS_SERVER)