Update copyright years.

[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000-modes.def

diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def
index a77aa26e850e5ac1966d1017b399c7e43085454c..8ef910869c577cdd57333eeff430df59466b3720 100644 (file)
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -1,5 +1,5 @@
 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
-   Copyright (C) 2002-2013 Free Software Foundation, Inc.
+   Copyright (C) 2002-2022 Free Software Foundation, Inc.
    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
 
    This file is part of GCC.
@@ -18,9 +18,39 @@
    along with GCC; see the file COPYING3.  If not see
    <http://www.gnu.org/licenses/>.  */
 
-/* 128-bit floating point.  ABI_V4 uses IEEE quad, AIX/Darwin
-   adjust this in rs6000_option_override_internal.  */
-FLOAT_MODE (TF, 16, ieee_quad_format);
+/* We order the 3 128-bit floating point types so that IFmode (IBM 128-bit
+   floating point) is the 128-bit floating point type with the highest
+   precision (128 bits).  This so that machine independent parts of the
+   compiler do not try to widen IFmode to TFmode on ISA 3.0 (power9) that has
+   hardware support for IEEE 128-bit.  We set TFmode (long double mode) in
+   between, and KFmode (explicit __float128) below it.
+
+   Previously, IFmode and KFmode were defined to be fractional modes and TFmode
+   was the standard mode.  Since IFmode does not define the normal arithmetic
+   insns (other than neg/abs), on a ISA 3.0 system, the machine independent
+   parts of the compiler would see that TFmode has the necessary hardware
+   support, and widen the operation from IFmode to TFmode.  However, IEEE
+   128-bit is not strictly a super-set of IBM extended double and the
+   conversion to/from IEEE 128-bit was a function call.
+
+   We now make IFmode the highest fractional mode, which means its values are
+   not considered for widening.  Since we don't define insns for IFmode, the
+   IEEE 128-bit modes would not widen to IFmode.  */
+
+#ifndef RS6000_MODES_H
+#include "config/rs6000/rs6000-modes.h"
+#endif
+
+/* IBM 128-bit floating point.  */
+FRACTIONAL_FLOAT_MODE (IF, FLOAT_PRECISION_IFmode, 16, ibm_extended_format);
+
+/* Explicit IEEE 128-bit floating point.  */
+FRACTIONAL_FLOAT_MODE (KF, FLOAT_PRECISION_KFmode, 16, ieee_quad_format);
+
+/* 128-bit floating point, either IBM 128-bit or IEEE 128-bit.  This is
+   adjusted in rs6000_option_override_internal to be the appropriate floating
+   point type.  */
+FRACTIONAL_FLOAT_MODE (TF, FLOAT_PRECISION_TFmode, 16, ieee_quad_format);
 
 /* Add any extra modes needed to represent the condition code.
 
@@ -34,15 +64,25 @@ CC_MODE (CCFP);
 CC_MODE (CCEQ);
 
 /* Vector modes.  */
-VECTOR_MODES (INT, 8);        /*       V8QI  V4HI V2SI */
+
+/* VMX/VSX.  */
 VECTOR_MODES (INT, 16);       /* V16QI V8HI  V4SI V2DI */
-VECTOR_MODES (INT, 32);       /* V32QI V16HI V8SI V4DI */
-VECTOR_MODE (INT, DI, 1);
-VECTOR_MODES (FLOAT, 8);      /*             V4HF V2SF */
+VECTOR_MODE (INT, TI, 1);     /*                  V1TI */
 VECTOR_MODES (FLOAT, 16);     /*       V8HF  V4SF V2DF */
+
+/* Two VMX/VSX vectors (for permute, select, concat, etc.)  */
+VECTOR_MODES (INT, 32);       /* V32QI V16HI V8SI V4DI */
 VECTOR_MODES (FLOAT, 32);     /*       V16HF V8SF V4DF */
 
+/* Half VMX/VSX vector (for internal use)  */
+VECTOR_MODE (FLOAT, SF, 2);   /*                 V2SF  */
+VECTOR_MODE (INT, SI, 2);     /*                 V2SI  */
+
 /* Replacement for TImode that only is allowed in GPRs.  We also use PTImode
    for quad memory atomic operations to force getting an even/odd register
    combination.  */
 PARTIAL_INT_MODE (TI, 128, PTI);
+
+/* Modes used by __vector_pair and __vector_quad.  */
+OPAQUE_MODE (OO, 32);
+OPAQUE_MODE (XO, 64);