Update copyright years.

[thirdparty/gcc.git] / gcc / config / s390 / 2064.md

diff --git a/gcc/config/s390/2064.md b/gcc/config/s390/2064.md
index 143cd1b9ca2a2418bd5efa4497df2964f298c6c1..6fd96bd4bf60ec9df0b68eea9e18656676373a3b 100644 (file)
--- a/gcc/config/s390/2064.md
+++ b/gcc/config/s390/2064.md
@@ -1,5 +1,5 @@
 ;; Scheduling description for z900 (cpu 2064).
-;;   Copyright (C) 2003 Free Software Foundation, Inc.
+;;   Copyright (C) 2003-2020 Free Software Foundation, Inc.
 ;;   Contributed by Hartmut Penner (hpenner@de.ibm.com) and
 ;;                  Ulrich Weigand (uweigand@de.ibm.com).
 
@@ -7,7 +7,7 @@
 
 ;; GCC is free software; you can redistribute it and/or modify it under
 ;; the terms of the GNU General Public License as published by the Free
-;; Software Foundation; either version 2, or (at your option) any later
+;; Software Foundation; either version 3, or (at your option) any later
 ;; version.
 
 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
@@ -16,28 +16,27 @@
 ;; for more details.
 
 ;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING.  If not, write to the Free
-;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-;; 02111-1307, USA.
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
 
 ;;
 ;; References:
-;;   The microarchitecture of the IBM eServer z900 processor. 
+;;   The microarchitecture of the IBM eServer z900 processor.
 ;;   E.M. Schwarz et al.
 ;;   IBM Journal of Research and Development Vol. 46 No 4/5, 2002.
-;; 
+;;
 ;;            z900 (cpu 2064) pipeline
-;;     
+;;
 ;;                 dec
 ;;              --> | <---
 ;;  LA bypass  |  agen    |
-;;             |    |     | 
+;;             |    |     |
 ;;              --- c1    |  Load bypass
-;;                  |     | 
+;;                  |     |
 ;;                  c2----
 ;;                  |
-;;                  e1 
-;;                  | 
+;;                  e1
+;;                  |
 ;;                  wr
 
 (define_automaton "z_ipu")
@@ -45,12 +44,12 @@
 (define_cpu_unit "z_wr"   "z_ipu")
 
 
-(define_insn_reservation "z_la" 1 
+(define_insn_reservation "z_la" 1
   (and (eq_attr "cpu" "z900")
        (eq_attr "type" "la"))
   "z_e1,z_wr")
 
-(define_insn_reservation "z_larl" 1 
+(define_insn_reservation "z_larl" 1
   (and (eq_attr "cpu" "z900")
        (eq_attr "type" "larl"))
   "z_e1,z_wr")
@@ -65,64 +64,67 @@
        (eq_attr "type" "store"))
   "z_e1,z_wr")
 
+(define_insn_reservation "z_sem" 2
+  (and (eq_attr "cpu" "z900")
+       (eq_attr "type" "sem"))
+  "z_e1*2,z_wr")
+
 (define_insn_reservation "z_call" 5
   (and (eq_attr "cpu" "z900")
        (eq_attr "type" "jsr"))
   "z_e1*5,z_wr")
 
-(define_insn_reservation "z_o2" 2
+(define_insn_reservation "z_mul" 5
   (and (eq_attr "cpu" "z900")
-       (eq_attr "type" "o2"))
-  "z_e1*2,z_wr")
+       (eq_attr "type" "imulsi,imulhi"))
+  "z_e1*5,z_wr")
 
-(define_insn_reservation "z_o3" 3
+(define_insn_reservation "z_inf" 10
   (and (eq_attr "cpu" "z900")
-       (eq_attr "type" "o3"))
-  "z_e1*3,z_wr")
+       (eq_attr "type" "idiv,imuldi"))
+  "z_e1*10,z_wr")
 
-;
-; Insn still not mentioned are check for
-; the usage of the agen unit 
-;
+;; For everything else we check the atype flag.
 
 (define_insn_reservation "z_int" 1
   (and (eq_attr "cpu" "z900")
-       (eq_attr "atype" "reg"))
+       (and (not (eq_attr "type" "la,larl,load,store,jsr"))
+            (eq_attr "atype" "reg")))
   "z_e1,z_wr")
 
 (define_insn_reservation "z_agen" 1
   (and (eq_attr "cpu" "z900")
-       (eq_attr "atype" "agen"))
+       (and (not (eq_attr "type" "la,larl,load,store,jsr"))
+            (eq_attr "atype" "agen")))
   "z_e1,z_wr")
 
-
 ;;
-;; s390_agen_dep_p returns 1, if a register is set in the 
+;; s390_agen_dep_p returns 1, if a register is set in the
 ;; first insn and used in the dependent insn to form a address.
 ;;
 
 ;;
 ;; If an instruction uses a register to address memory, it needs
 ;; to be set 5 cycles in advance.
-;; 
+;;
 
-(define_bypass 5 "z_int,z_agen" 
+(define_bypass 5 "z_int,z_agen"
               "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
 
 ;;
-;; A load type instruction uses a bypass to feed the result back       
-;; to the address generation pipeline stage. 
+;; A load type instruction uses a bypass to feed the result back
+;; to the address generation pipeline stage.
 ;;
 
-(define_bypass 3 "z_load"    
+(define_bypass 3 "z_load"
                 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
 
 ;;
-;; A load address type instruction uses a bypass to feed the 
-;; result back to the address generation pipeline stage. 
+;; A load address type instruction uses a bypass to feed the
+;; result back to the address generation pipeline stage.
 ;;
 
-(define_bypass 2 "z_larl,z_la" 
+(define_bypass 2 "z_larl,z_la"
                 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")