;; Scheduling description for z990 (cpu 2084).
-;; Copyright (C) 2003,2004 Free Software Foundation, Inc.
+;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
;; Ulrich Weigand (uweigand@de.ibm.com).
;; GCC is free software; you can redistribute it and/or modify it under
;; the terms of the GNU General Public License as published by the Free
-;; Software Foundation; either version 2, or (at your option) any later
+;; Software Foundation; either version 3, or (at your option) any later
;; version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
;; for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING. If not, write to the Free
-;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-;; 02111-1307, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
(define_automaton "x_ipu")
;; Simple insns
;;
+(define_insn_reservation "x_int" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (and (eq_attr "type" "integer")
+ (eq_attr "atype" "reg")))
+ "x-e1-st,x-wr-st")
+
+(define_insn_reservation "x_agen" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (and (eq_attr "type" "integer")
+ (eq_attr "atype" "agen")))
+ "x-e1-st,x-wr-st")
+
(define_insn_reservation "x_lr" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
(eq_attr "type" "lr"))
- "x-e1-st,x-wr-st")
+ "x-e1-st,x-wr-st")
-(define_insn_reservation "x_la" 1
- (and (eq_attr "cpu" "z990")
+(define_insn_reservation "x_la" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
(eq_attr "type" "la"))
- "x-e1-st,x-wr-st")
+ "x-e1-st,x-wr-st")
-(define_insn_reservation "x_larl" 1
- (and (eq_attr "cpu" "z990")
+(define_insn_reservation "x_larl" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
(eq_attr "type" "larl"))
- "x-e1-st,x-wr-st")
+ "x-e1-st,x-wr-st")
-(define_insn_reservation "x_load" 1
- (and (eq_attr "cpu" "z990")
+(define_insn_reservation "x_load" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
(eq_attr "type" "load"))
- "x-e1-st+x-mem,x-wr-st")
+ "x-e1-st+x-mem,x-wr-st")
-(define_insn_reservation "x_store" 1
- (and (eq_attr "cpu" "z990")
+(define_insn_reservation "x_store" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
(eq_attr "type" "store"))
- "x-e1-st+x_store_tok,x-wr-st")
+ "x-e1-st+x_store_tok,x-wr-st")
-(define_insn_reservation "x_branch" 1
- (and (eq_attr "cpu" "z990")
+(define_insn_reservation "x_branch" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
(eq_attr "type" "branch"))
- "x_e1_r,x_wr_r")
+ "x_e1_r,x_wr_r")
-(define_insn_reservation "x_call" 5
- (and (eq_attr "cpu" "z990")
+(define_insn_reservation "x_call" 5
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
(eq_attr "type" "jsr"))
- "x-e1-np*5,x-wr-np")
+ "x-e1-np*5,x-wr-np")
+
+(define_insn_reservation "x_mul_hi" 2
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "imulhi"))
+ "x-e1-np*2,x-wr-np")
+
+(define_insn_reservation "x_mul_sidi" 4
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "imulsi,imuldi"))
+ "x-e1-np*4,x-wr-np")
+
+(define_insn_reservation "x_div" 10
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "idiv"))
+ "x-e1-np*10,x-wr-np")
+
+(define_insn_reservation "x_sem" 17
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "sem"))
+ "x-e1-np+x-mem,x-e1-np*16,x-wr-st")
;;
;; Multicycle insns
;;
-(define_insn_reservation "x_ss" 1
- (and (eq_attr "cpu" "z990")
- (eq_attr "op_type" "SS"))
- "x-e1-np,x-wr-np")
+(define_insn_reservation "x_cs" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "cs"))
+ "x-e1-np,x-wr-np")
+
+(define_insn_reservation "x_vs" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "vs"))
+ "x-e1-np*10,x-wr-np")
-(define_insn_reservation "x_stm" 1
- (and (eq_attr "cpu" "z990")
+(define_insn_reservation "x_stm" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
(eq_attr "type" "stm"))
- "(x-e1-np+x_store_tok)*10,x-wr-np")
+ "(x-e1-np+x_store_tok)*10,x-wr-np")
-(define_insn_reservation "x_lm" 1
- (and (eq_attr "cpu" "z990")
+(define_insn_reservation "x_lm" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
(eq_attr "type" "lm"))
- "x-e1-np*10,x-wr-np")
+ "x-e1-np*10,x-wr-np")
-(define_insn_reservation "x_nn" 1
- (and (eq_attr "cpu" "z990")
- (eq_attr "op_type" "NN"))
- "x-e1-np,x-wr-np")
+(define_insn_reservation "x_other" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "other"))
+ "x-e1-np,x-wr-np")
;;
;; Floating point insns
;;
-(define_insn_reservation "x_fsimpd" 6
- (and (eq_attr "cpu" "z990")
- (eq_attr "type" "fsimpd,fmuld"))
- "x_e1_t,x-wr-fp")
-
-(define_insn_reservation "x_fsimps" 6
- (and (eq_attr "cpu" "z990")
- (eq_attr "type" "fsimps,fmuls"))
- "x_e1_t,x-wr-fp")
-
-(define_insn_reservation "x_fdivd" 36
- (and (eq_attr "cpu" "z990")
- (eq_attr "type" "fdivd,fsqrtd"))
- "x_e1_t*30,x-wr-fp")
-
-(define_insn_reservation "x_fdivs" 36
- (and (eq_attr "cpu" "z990")
- (eq_attr "type" "fdivs,fsqrts"))
- "x_e1_t*30,x-wr-fp")
-
-(define_insn_reservation "x_floadd" 6
- (and (eq_attr "cpu" "z990")
- (eq_attr "type" "floadd"))
- "x_e1_t,x-wr-fp")
-
-(define_insn_reservation "x_floads" 6
- (and (eq_attr "cpu" "z990")
- (eq_attr "type" "floads"))
- "x_e1_t,x-wr-fp")
-
-(define_insn_reservation "x_fstored" 1
- (and (eq_attr "cpu" "z990")
- (eq_attr "type" "fstored"))
- "x_e1_t,x-wr-fp")
-
-(define_insn_reservation "x_fstores" 1
- (and (eq_attr "cpu" "z990")
- (eq_attr "type" "fstores"))
- "x_e1_t,x-wr-fp")
-
-(define_insn_reservation "x_ftoi" 1
- (and (eq_attr "cpu" "z990")
- (eq_attr "type" "ftoi"))
- "x_e1_t*3,x-wr-fp")
+(define_insn_reservation "x_fsimptf" 7
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "fsimptf,fhex"))
+ "x_e1_t*2,x-wr-fp")
-(define_insn_reservation "x_itof" 7
- (and (eq_attr "cpu" "z990")
- (eq_attr "type" "itof"))
- "x_e1_t*3,x-wr-fp")
+(define_insn_reservation "x_fsimpdf" 6
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "fsimpdf,fmuldf,fmadddf,fhex"))
+ "x_e1_t,x-wr-fp")
-(define_bypass 1 "x_fsimpd" "x_fstored")
+(define_insn_reservation "x_fsimpsf" 6
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "fsimpsf,fmulsf,fmaddsf,fhex"))
+ "x_e1_t,x-wr-fp")
-(define_bypass 1 "x_fsimps" "x_fstores")
-(define_bypass 1 "x_floadd" "x_fsimpd,x_fstored,x_floadd")
-
-(define_bypass 1 "x_floads" "x_fsimps,x_fstores,x_floads")
+(define_insn_reservation "x_fmultf" 33
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "fmultf"))
+ "x_e1_t*27,x-wr-fp")
-;;
-;; Insns still not mentioned are checked for
-;; the usage of the agen unit
-;;
-(define_insn_reservation "x_int" 1
- (and (eq_attr "cpu" "z990")
- (eq_attr "atype" "reg"))
- "x-e1-st,x-wr-st")
+(define_insn_reservation "x_fdivtf" 82
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "fdivtf,fsqrttf"))
+ "x_e1_t*76,x-wr-fp")
-(define_insn_reservation "x_agen" 1
- (and (eq_attr "cpu" "z990")
- (eq_attr "atype" "agen"))
- "x-e1-st+x-mem,x-wr-st")
+(define_insn_reservation "x_fdivdf" 36
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "fdivdf,fsqrtdf"))
+ "x_e1_t*30,x-wr-fp")
+
+(define_insn_reservation "x_fdivsf" 36
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "fdivsf,fsqrtsf"))
+ "x_e1_t*30,x-wr-fp")
+
+
+(define_insn_reservation "x_floadtf" 6
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "floadtf"))
+ "x_e1_t,x-wr-fp")
+
+(define_insn_reservation "x_floaddf" 6
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "floaddf"))
+ "x_e1_t,x-wr-fp")
+
+(define_insn_reservation "x_floadsf" 6
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "floadsf"))
+ "x_e1_t,x-wr-fp")
+
+
+(define_insn_reservation "x_fstoredf" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "fstoredf"))
+ "x_e1_t,x-wr-fp")
+
+(define_insn_reservation "x_fstoresf" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "fstoresf"))
+ "x_e1_t,x-wr-fp")
+
+
+(define_insn_reservation "x_ftrunctf" 16
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "ftrunctf"))
+ "x_e1_t*10,x-wr-fp")
+
+(define_insn_reservation "x_ftruncdf" 11
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "ftruncdf"))
+ "x_e1_t*5,x-wr-fp")
+
+
+(define_insn_reservation "x_ftoi" 1
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "ftoi"))
+ "x_e1_t*3,x-wr-fp")
+
+(define_insn_reservation "x_itof" 7
+ (and (eq_attr "cpu" "z990,z9_109,z9_ec")
+ (eq_attr "type" "itoftf,itofdf,itofsf"))
+ "x_e1_t*3,x-wr-fp")
+
+(define_bypass 1 "x_fsimpdf" "x_fstoredf")
+
+(define_bypass 1 "x_fsimpsf" "x_fstoresf")
+
+(define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf")
+
+(define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf")
;;
-;; s390_agen_dep_p returns 1, if a register is set in the
+;; s390_agen_dep_p returns 1, if a register is set in the
;; first insn and used in the dependent insn to form a address.
;;
;;
;; If an instruction uses a register to address memory, it needs
;; to be set 5 cycles in advance.
-;;
+;;
-(define_bypass 5 "x_int,x_agen,x_lr"
- "x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
+(define_bypass 5 "x_int,x_agen,x_lr"
+ "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
"s390_agen_dep_p")
-(define_bypass 9 "x_int,x_agen,x_lr"
- "x_floadd, x_floads, x_fstored, x_fstores,\
- x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
+(define_bypass 9 "x_int,x_agen,x_lr"
+ "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
+ x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
"s390_agen_dep_p")
;;
-;; A load type instruction uses a bypass to feed the result back
-;; to the address generation pipeline stage.
+;; A load type instruction uses a bypass to feed the result back
+;; to the address generation pipeline stage.
;;
-(define_bypass 4 "x_load"
- "x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
+(define_bypass 4 "x_load"
+ "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
"s390_agen_dep_p")
(define_bypass 5 "x_load"
- "x_floadd, x_floads, x_fstored, x_fstores,\
- x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
+ "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
+ x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
"s390_agen_dep_p")
;;
-;; A load address type instruction uses a bypass to feed the
-;; result back to the address generation pipeline stage.
+;; A load address type instruction uses a bypass to feed the
+;; result back to the address generation pipeline stage.
;;
-(define_bypass 3 "x_larl,x_la"
- "x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
+(define_bypass 3 "x_larl,x_la"
+ "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
"s390_agen_dep_p")
(define_bypass 5 "x_larl, x_la"
- "x_floadd, x_floads, x_fstored, x_fstores,\
- x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
+ "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
+ x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
"s390_agen_dep_p")
;;
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