;; Constraints definitions belonging to the gcc backend for IBM S/390.
-;; Copyright (C) 2006-2015 Free Software Foundation, Inc.
+;; Copyright (C) 2006-2020 Free Software Foundation, Inc.
;; Written by Wolfgang Gellerich, using code and information found in
;; files s390.md, s390.h, and s390.c.
;;
;; c -- Condition code register 33.
;; d -- Any register from 0 to 15.
;; f -- Floating point registers.
+;; j -- Multiple letter constraint for constant scalar and vector values
+;; j00: constant zero scalar or vector
+;; jm1: constant scalar or vector with all bits set
+;; jxx: contiguous bitmask of 0 or 1 in all vector elements
+;; jyy: constant consisting of byte chunks being either 0 or 0xff
+;; jKK: constant vector with all elements having the same value and
+;; matching K constraint
+;; jm6: An integer operand with the lowest order 6 bits all ones.
+;; jdd: A constant operand that fits into the data section.
;; t -- Access registers 36 and 37.
+;; v -- Vector registers v0-v31.
;; C -- A signed 8-bit constant (-128..127)
;; D -- An unsigned 16-bit constant (0..65535)
;; G -- Const double zero operand
;; M -- Constant integer with a value of 0x7fffffff.
;; N -- Multiple letter constraint followed by 4 parameter letters.
;; 0..9,x: number of the part counting from most to least significant
-;; H,Q: mode of the part
+;; S,H,Q: mode of the part
;; D,S,H: mode of the containing operand
;; 0,F: value of the other parts (F - all bits set)
;; --
-;; xx[DS]q satisfies s390_contiguous_bitmask_p for DImode or SImode
+;; xxDq satisfies s390_contiguous_bitmask_p for DImode
+;; (with possible wraparound of the one-bit range)
+;; xxSw satisfies s390_contiguous_bitmask_p for SImode
+;; (with possible wraparound of the one-bit range)
+;; xxSq satisfies s390_contiguous_bitmask_nowrap_p for SImode
+;; (without wraparound of the one-bit range)
;;
;; The constraint matches if the specified part of a constant
;; has a value different from its other parts. If the letter x
;; B -- Multiple letter constraint followed by Q, R, S, or T:
;; Memory reference of the type specified by second letter that
;; does *not* refer to a literal pool entry.
-;; U -- Pointer with short displacement. (deprecated - use ZQZR)
-;; W -- Pointer with long displacement. (deprecated - use ZSZT)
-;; Y -- Shift count operand.
+;; U -- Pointer with short displacement. (deprecated - use ZR)
+;; W -- Pointer with long displacement. (deprecated - use ZT)
+;; Y -- Address style operand without index.
;; ZQ -- Pointer without index register and with short displacement.
;; ZR -- Pointer with index register and short displacement.
;; ZS -- Pointer without index register but with long displacement.
;; ZT -- Pointer with index register and long displacement.
+;; ZL -- LARL operand when in 64-bit mode, otherwise nothing.
;;
;;
Access registers 36 and 37")
+(define_register_constraint "v"
+ "VEC_REGS"
+ "Vector registers v0-v31")
+
+
;;
;; General constraints for constants.
;;
(define_address_constraint "Y"
- "Shift count operand"
+ "Address style operand without index register"
+
+;; Simply check for base + offset style operands. Reload will take
+;; care of making sure we have a proper base register.
+
+ (match_test "s390_decompose_addrstyle_without_index (op, NULL, NULL)" ))
-;; Simply check for the basic form of a shift count. Reload will
-;; take care of making sure we have a proper base register.
- (match_test "s390_decompose_shift_count (op, NULL, NULL)" ))
+;; Shift count operands are not necessarily legitimate addresses
+;; but the predicate shift_count_operand will only allow
+;; proper operands. If reload/lra need to change e.g. a spilled register
+;; they can still do so via the special handling of address constraints.
+;; To avoid further reloading (caused by a non-matching constraint) we
+;; always return true here as the predicate's checks are already sufficient.
+
+(define_address_constraint "jsc"
+ "Address style operand used as shift count."
+ (match_test "true" ))
;; N -- Multiple letter constraint followed by 4 parameter letters.
;; 0..9,x: number of the part counting from most to least significant
-;; H,Q: mode of the part
+;; S,H,Q: mode of the part
;; D,S,H: mode of the containing operand
;; 0,F: value of the other parts (F = all bits set)
;;
(match_test "s390_N_constraint_str (\"xQS0\", ival)")))
+(define_constraint "NxHD0"
+ "@internal"
+ (and (match_code "const_int")
+ (match_test "s390_N_constraint_str (\"xHD0\", ival)")))
+
+
+(define_constraint "NxSD0"
+ "@internal"
+ (and (match_code "const_int")
+ (match_test "s390_N_constraint_str (\"xSD0\", ival)")))
+
+
(define_constraint "NxQD0"
"@internal"
(and (match_code "const_int")
(and (match_code "const_int")
(match_test "s390_N_constraint_str (\"xQH0\", ival)")))
-(define_constraint "NxxDq"
+(define_constraint "NxxDw"
"@internal"
(and (match_code "const_int")
- (match_test "s390_contiguous_bitmask_p (ival, 64, NULL, NULL)")))
+ (match_test "s390_contiguous_bitmask_p (ival, true, 64, NULL, NULL)")))
(define_constraint "NxxSq"
"@internal"
(and (match_code "const_int")
- (match_test "s390_contiguous_bitmask_p (ival, 32, NULL, NULL)")))
+ (match_test "s390_contiguous_bitmask_p (ival, false, 32, NULL, NULL)")))
+
+(define_constraint "NxxSw"
+ "@internal"
+ (and (match_code "const_int")
+ (match_test "s390_contiguous_bitmask_p (ival, true, 32, NULL, NULL)")))
;;
;; Double-letter constraints starting with O follow.
(match_test "s390_O_constraint_str ('n', ival)")))
+;;
+;; Vector constraints follow.
+;;
+
+(define_constraint "j00"
+ "Zero scalar or vector constant"
+ (match_test "op == CONST0_RTX (GET_MODE (op))"))
+
+(define_constraint "jm1"
+ "All one bit scalar or vector constant"
+ (match_test "op == CONSTM1_RTX (GET_MODE (op))"))
+
+; vector generate mask operand - support for up to 64 bit elements
+(define_constraint "jxx"
+ "@internal"
+ (and (match_code "const_vector")
+ (match_test "s390_contiguous_bitmask_vector_p (op, NULL, NULL)")))
+; vector generate byte mask operand - this is only supposed to deal
+; with real vectors 128 bit values of being either 0 or -1 are handled
+; with j00 and jm1
+(define_constraint "jyy"
+ "@internal"
+ (and (match_code "const_vector")
+ (match_test "s390_bytemask_vector_p (op, NULL)")))
+
+; vector replicate immediate operand - support for up to 64 bit elements
+(define_constraint "jKK"
+ "@internal"
+ (and (and (and (match_code "const_vector")
+ (match_test "const_vec_duplicate_p (op)"))
+ (match_test "GET_MODE_UNIT_SIZE (GET_MODE (op)) <= 8"))
+ (match_test "satisfies_constraint_K (XVECEXP (op, 0, 0))")))
+
+(define_constraint "jm6"
+ "@internal An integer operand with the lowest order 6 bits all ones."
+ (match_operand 0 "const_int_6bitset_operand"))
;;
;; Memory constraints follow.
; the TARGET_MEM_CONSTRAINT macro.
(define_memory_constraint "m"
"Matches the most general memory address for pre-z10 machines."
- (match_test "s390_mem_constraint (\"R\", op)
- || s390_mem_constraint (\"T\", op)"))
+ (match_test "s390_mem_constraint (\"T\", op)"))
(define_memory_constraint "AQ"
"@internal
(define_address_constraint "U"
- "Pointer with short displacement. (deprecated - use ZQZR)"
- (match_test "s390_mem_constraint (\"U\", op)"))
+ "Pointer with short displacement. (deprecated - use ZR)"
+ (match_test "s390_mem_constraint (\"ZR\", op)"))
(define_address_constraint "W"
- "Pointer with long displacement. (deprecated - use ZSZT)"
- (match_test "s390_mem_constraint (\"W\", op)"))
+ "Pointer with long displacement. (deprecated - use ZT)"
+ (match_test "s390_mem_constraint (\"ZT\", op)"))
(define_address_constraint "ZQ"
(define_address_constraint "ZT"
"Pointer with index register and long displacement."
(match_test "s390_mem_constraint (\"ZT\", op)"))
+
+(define_constraint "ZL"
+ "LARL operand when in 64-bit mode, otherwise nothing."
+ (match_test "TARGET_64BIT && larl_operand (op, VOIDmode)"))
+
+;; This constraint must behave like "i", in particular, the matching values
+;; must never be placed into registers or memory by
+;; cfgexpand.c:expand_asm_stmt. It could be straightforward to start its name
+;; with a letter from genpreds.c:const_int_constraints, however it would
+;; require using (match_code "const_int"), which is infeasible. To achieve the
+;; same effect, that is, setting maybe_allows_reg and maybe_allows_mem to false
+;; in genpreds.c:add_constraint, we explicitly exclude reg, subreg and mem
+;; codes.
+(define_constraint "jdd"
+ "A constant operand that fits into the data section.
+ Usage of this constraint might produce a relocation."
+ (and (not (match_code "reg"))
+ (not (match_code "subreg"))
+ (not (match_code "mem"))
+ (match_test "CONSTANT_P (op)")))
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