/* Definitions of target machine for GNU compiler, for IBM S/390
- Copyright (C) 2002-2013 Free Software Foundation, Inc.
+ Copyright (C) 2002-2024 Free Software Foundation, Inc.
Contributed by Hartmut Penner (hpenner@de.ibm.com) and
Ulrich Weigand (uweigand@de.ibm.com).
/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE. */
INT_MODE (OI, 32);
-/* Define TFmode to work around reload problem PR 20927. */
+/* 128-bit float stored in a VR on z14+ or a FPR pair on older machines. */
FLOAT_MODE (TF, 16, ieee_quad_format);
+/* 128-bit float stored in a FPR pair. */
+FLOAT_MODE (FPRX2, 16, ieee_quad_format);
+
/* Add any extra modes needed to represent the condition code. */
/*
Condition Codes
+ CC0 CC1 CC2 CC3
+
Check for zero
CCZ: EQ NE NE NE
ADB/R, AEB/R, SDB/R, SEB/R,
SRAG, SRA, SRDA)
CCSR: EQ GT LT UNORDERED (CGF/R, CH/Y)
+CCSFPS: EQ LT GT UNORDERED (KEB/R, KDB/R, KXBR, KDTR,
+ KXTR, WFK)
Condition codes resulting from add with overflow
CCAP: EQ LT GT LT (AGHI, AHI)
CCAN: EQ LT GT GT (AGHI, AHI)
+Condition codes for overflow checking resulting from signed adds/subs/mults
+
+CCO: EQ EQ EQ NE (AGR, AGHI, SGR, MSC, ...)
+
Condition codes of unsigned adds and subs
CCL: EQ NE EQ NE (ALGF/R, ALG/R, AL/R/Y,
CCA -> CCAP, CCAN
+
*** Comments ***
CCAP, CCAN
the sign of the result even in case of an overflow.
+CCO
+
+This mode is used to check whether there was an overflow condition in
+a signed add, sub, or mul operation. See (addv<mode>4, subv<mode>4,
+mulv<mode>4 patterns).
+
+
CCT, CCT1, CCT2, CCT3
If bits of an integer masked with an AND instruction are checked, the test under
exchanged operands.
+CCSFPS
+
+This mode is used for signaling rtxes: LT, LE, GT, GE and LTGT.
+
+
CCL1, CCL2
These modes represent the result of overflow checks.
operands were equal/unequal. The CCZ1 mode ensures the result can be
effectively placed into a register.
+CCVIH, CCVIHU, CCVFH, CCVFHE
+
+These are condition code modes used in instructions setting the
+condition code. The mode determines which comparison to perform (H -
+high, HU - high unsigned, HE - high or equal) and whether it is a
+floating point comparison or not (I - int, F - float).
+
+The comparison operation to be performed needs to be encoded into the
+condition code mode since the comparison operator is not available in
+compare style patterns (set cc (compare (op0) (op1))). So the
+condition code mode is the only information to determine the
+instruction to be used.
+
+CCVIALL, CCVIANY, CCVFALL, CCVFANY
+
+These modes are used in instructions reading the condition code.
+Opposed to the CC producer patterns the comparison operator is
+available. Hence the comparison operation does not need to be part of
+the CC mode. However, we still need to know whether CC has been
+generated by a float or an integer comparison in order to be able to
+invert the condition correctly (int: GT -> LE, float: GT -> UNLE).
+
+The ALL and ANY variants differ only in the usage of CC1 which
+indicates a mixed result across the vector elements. Be aware that
+depending on the comparison code the ALL and ANY variants might
+actually refer to their opposite meaning. I.e. while inverting the
+comparison in (EQ (reg:CCVIALL 33) (const_int 0)) results in (NE
+(reg:CCVIALL 33) (const_int 0)) it in fact describes an ANY comparison
+(inverting "all equal" should be "any not equal") However, the
+middle-end does invert only the comparison operator without touching
+the mode.
+Hence, the ALL/ANY in the mode names refer to the meaning in the
+context of EQ, GT, GE while for the inverted codes it actually means
+ANY/ALL.
+
+CCRAW
+
+The cc mode generated by a non-compare instruction. The condition
+code mask for the CC consumer is determined by the comparison operator
+(only EQ and NE allowed) and the immediate value given as second
+operand to the operator. For the other CC modes this value used to be
+0.
+
*/
CC_MODE (CCA);
CC_MODE (CCAP);
CC_MODE (CCAN);
+CC_MODE (CCO);
CC_MODE (CCL);
CC_MODE (CCL1);
CC_MODE (CCL2);
CC_MODE (CCUR);
CC_MODE (CCS);
CC_MODE (CCSR);
+CC_MODE (CCSFPS);
CC_MODE (CCT);
CC_MODE (CCT1);
CC_MODE (CCT2);
CC_MODE (CCT3);
+CC_MODE (CCRAW);
+
+CC_MODE (CCVEQ);
+
+CC_MODE (CCVIH);
+CC_MODE (CCVIHU);
+
+CC_MODE (CCVFH);
+CC_MODE (CCVFHE);
+
+CC_MODE (CCVIALL);
+CC_MODE (CCVIANY);
+
+CC_MODE (CCVFALL);
+CC_MODE (CCVFANY);
+
+/* Vector modes. */
+
+VECTOR_MODES (INT, 2); /* V2QI */
+VECTOR_MODES (INT, 4); /* V4QI V2HI */
+VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
+VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
+VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI V2TI */
+
+VECTOR_MODE (FLOAT, SF, 2); /* V2SF */
+VECTOR_MODE (FLOAT, SF, 4); /* V4SF */
+VECTOR_MODE (FLOAT, SF, 8); /* V8SF */
+VECTOR_MODE (FLOAT, DF, 2); /* V2DF */
+VECTOR_MODE (FLOAT, DF, 4); /* V4DF */
+
+VECTOR_MODE (INT, QI, 1); /* V1QI */
+VECTOR_MODE (INT, HI, 1); /* V1HI */
+VECTOR_MODE (INT, SI, 1); /* V1SI */
+VECTOR_MODE (INT, DI, 1); /* V1DI */
+VECTOR_MODE (INT, TI, 1); /* V1TI */
+
+VECTOR_MODE (FLOAT, SF, 1); /* V1SF */
+VECTOR_MODE (FLOAT, DF, 1); /* V1DF */
+VECTOR_MODE (FLOAT, TF, 1); /* V1TF */
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