Teach sparc backend about %gsr register and add intrinsics to access it.

[thirdparty/gcc.git] / gcc / config / sparc / niagara.md

diff --git a/gcc/config/sparc/niagara.md b/gcc/config/sparc/niagara.md
index a618b195a435576b03edffccfb7e0b4a5a341cde..3e5a3e5b19275720494091e3ccd5273c48cc95b3 100644 (file)
--- a/gcc/config/sparc/niagara.md
+++ b/gcc/config/sparc/niagara.md
@@ -114,5 +114,5 @@
  */
 (define_insn_reservation "niag_vis" 8
   (and (eq_attr "cpu" "niagara")
-    (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge"))
+    (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,gsr"))
   "niag_pipe*8")