/* Subroutines for insn-output.c for SPARC.
- Copyright (C) 1987-2018 Free Software Foundation, Inc.
+ Copyright (C) 1987-2020 Free Software Foundation, Inc.
Contributed by Michael Tiemann (tiemann@cygnus.com)
64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
at Cygnus Support.
#include "gimplify.h"
#include "langhooks.h"
#include "reload.h"
-#include "params.h"
#include "tree-pass.h"
#include "context.h"
#include "builtins.h"
#include "tree-vector-builder.h"
+#include "opts.h"
/* This file should be included last. */
#include "target-def.h"
static int sparc_register_move_cost (machine_mode,
reg_class_t, reg_class_t);
static bool sparc_rtx_costs (rtx, machine_mode, int, int, int *, bool);
-static rtx sparc_function_value (const_tree, const_tree, bool);
-static rtx sparc_libcall_value (machine_mode, const_rtx);
-static bool sparc_function_value_regno_p (const unsigned int);
-static rtx sparc_struct_value_rtx (tree, int);
static machine_mode sparc_promote_function_mode (const_tree, machine_mode,
int *, const_tree, int);
-static bool sparc_return_in_memory (const_tree, const_tree);
static bool sparc_strict_argument_naming (cumulative_args_t);
static void sparc_va_start (tree, rtx);
static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
static rtx sparc_delegitimize_address (rtx);
static bool sparc_mode_dependent_address_p (const_rtx, addr_space_t);
static bool sparc_pass_by_reference (cumulative_args_t,
- machine_mode, const_tree, bool);
+ const function_arg_info &);
static void sparc_function_arg_advance (cumulative_args_t,
- machine_mode, const_tree, bool);
-static rtx sparc_function_arg_1 (cumulative_args_t,
- machine_mode, const_tree, bool, bool);
-static rtx sparc_function_arg (cumulative_args_t,
- machine_mode, const_tree, bool);
+ const function_arg_info &);
+static rtx sparc_function_arg (cumulative_args_t, const function_arg_info &);
static rtx sparc_function_incoming_arg (cumulative_args_t,
- machine_mode, const_tree, bool);
+ const function_arg_info &);
static pad_direction sparc_function_arg_padding (machine_mode, const_tree);
static unsigned int sparc_function_arg_boundary (machine_mode,
const_tree);
static int sparc_arg_partial_bytes (cumulative_args_t,
- machine_mode, tree, bool);
+ const function_arg_info &);
+static bool sparc_return_in_memory (const_tree, const_tree);
+static rtx sparc_struct_value_rtx (tree, int);
+static rtx sparc_function_value (const_tree, const_tree, bool);
+static rtx sparc_libcall_value (machine_mode, const_rtx);
+static bool sparc_function_value_regno_p (const unsigned int);
+static unsigned HOST_WIDE_INT sparc_asan_shadow_offset (void);
static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
static void sparc_file_end (void);
static bool sparc_frame_pointer_required (void);
static bool sparc_can_eliminate (const int, const int);
-static rtx sparc_builtin_setjmp_frame_value (void);
static void sparc_conditional_register_usage (void);
static bool sparc_use_pseudo_pic_reg (void);
static void sparc_init_pic_reg (void);
};
#endif
\f
-/* Option handling. */
-
-/* Parsed value. */
-enum cmodel sparc_cmodel;
-
char sparc_hard_reg_printed[8];
/* Initialize the GCC target structure. */
#undef TARGET_PROMOTE_FUNCTION_MODE
#define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
+#undef TARGET_STRICT_ARGUMENT_NAMING
+#define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
-#undef TARGET_FUNCTION_VALUE
-#define TARGET_FUNCTION_VALUE sparc_function_value
-#undef TARGET_LIBCALL_VALUE
-#define TARGET_LIBCALL_VALUE sparc_libcall_value
-#undef TARGET_FUNCTION_VALUE_REGNO_P
-#define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
-
-#undef TARGET_STRUCT_VALUE_RTX
-#define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
-#undef TARGET_RETURN_IN_MEMORY
-#define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
#undef TARGET_MUST_PASS_IN_STACK
#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
#undef TARGET_PASS_BY_REFERENCE
#undef TARGET_FUNCTION_ARG_BOUNDARY
#define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
+#undef TARGET_RETURN_IN_MEMORY
+#define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
+#undef TARGET_STRUCT_VALUE_RTX
+#define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
+#undef TARGET_FUNCTION_VALUE
+#define TARGET_FUNCTION_VALUE sparc_function_value
+#undef TARGET_LIBCALL_VALUE
+#define TARGET_LIBCALL_VALUE sparc_libcall_value
+#undef TARGET_FUNCTION_VALUE_REGNO_P
+#define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
+
#undef TARGET_EXPAND_BUILTIN_SAVEREGS
#define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
-#undef TARGET_STRICT_ARGUMENT_NAMING
-#define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
+
+#undef TARGET_ASAN_SHADOW_OFFSET
+#define TARGET_ASAN_SHADOW_OFFSET sparc_asan_shadow_offset
#undef TARGET_EXPAND_BUILTIN_VA_START
#define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
#undef TARGET_FRAME_POINTER_REQUIRED
#define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
-#undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
-#define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
-
#undef TARGET_CAN_ELIMINATE
#define TARGET_CAN_ELIMINATE sparc_can_eliminate
static void
sparc_option_override (void)
{
- static struct code_model {
- const char *const name;
- const enum cmodel value;
- } const cmodels[] = {
- { "32", CM_32 },
- { "medlow", CM_MEDLOW },
- { "medmid", CM_MEDMID },
- { "medany", CM_MEDANY },
- { "embmedany", CM_EMBMEDANY },
- { NULL, (enum cmodel) 0 }
- };
- const struct code_model *cmodel;
/* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
static struct cpu_default {
const int cpu;
- const enum processor_type processor;
+ const enum sparc_processor_type processor;
} const cpu_default[] = {
/* There must be one entry here for each TARGET_CPU value. */
{ TARGET_CPU_sparc, PROCESSOR_CYPRESS },
else if (! strcmp (q, "options"))
mask = MASK_DEBUG_OPTIONS;
else
- error ("unknown -mdebug-%s switch", q);
+ error ("unknown %<-mdebug-%s%> switch", q);
if (invert)
sparc_debug &= ~mask;
/* We force all 64bit archs to use 128 bit long double */
if (TARGET_ARCH64 && !TARGET_LONG_DOUBLE_128)
{
- error ("-mlong-double-64 not allowed with -m64");
+ error ("%<-mlong-double-64%> not allowed with %<-m64%>");
target_flags |= MASK_LONG_DOUBLE_128;
}
- /* Code model selection. */
- sparc_cmodel = SPARC_DEFAULT_CMODEL;
-
-#ifdef SPARC_BI_ARCH
- if (TARGET_ARCH32)
- sparc_cmodel = CM_32;
-#endif
-
- if (sparc_cmodel_string != NULL)
- {
- if (TARGET_ARCH64)
- {
- for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
- if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
- break;
- if (cmodel->name == NULL)
- error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
- else
- sparc_cmodel = cmodel->value;
- }
- else
- error ("-mcmodel= is not supported on 32-bit systems");
- }
-
/* Check that -fcall-saved-REG wasn't specified for out registers. */
for (i = 8; i < 16; i++)
if (!call_used_regs [i])
{
- error ("-fcall-saved-REG is not supported for out registers");
+ error ("%<-fcall-saved-REG%> is not supported for out registers");
call_used_regs [i] = 1;
}
if (sparc_fix_ut699)
target_flags &= ~MASK_FSMULD;
+#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
+ if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
+ target_flags |= MASK_LONG_DOUBLE_128;
+#endif
+
+ if (TARGET_DEBUG_OPTIONS)
+ dump_target_flags ("Final target_flags", target_flags);
+
+ /* Set the code model if no -mcmodel option was specified. */
+ if (global_options_set.x_sparc_code_model)
+ {
+ if (TARGET_ARCH32)
+ error ("%<-mcmodel=%> is not supported in 32-bit mode");
+ }
+ else
+ {
+ if (TARGET_ARCH32)
+ sparc_code_model = CM_32;
+ else
+ sparc_code_model = SPARC_DEFAULT_CMODEL;
+ }
+
+ /* Set the memory model if no -mmemory-model option was specified. */
+ if (!global_options_set.x_sparc_memory_model)
+ {
+ /* Choose the memory model for the operating system. */
+ enum sparc_memory_model_type os_default = SUBTARGET_DEFAULT_MEMORY_MODEL;
+ if (os_default != SMM_DEFAULT)
+ sparc_memory_model = os_default;
+ /* Choose the most relaxed model for the processor. */
+ else if (TARGET_V9)
+ sparc_memory_model = SMM_RMO;
+ else if (TARGET_LEON3)
+ sparc_memory_model = SMM_TSO;
+ else if (TARGET_LEON)
+ sparc_memory_model = SMM_SC;
+ else if (TARGET_V8)
+ sparc_memory_model = SMM_PSO;
+ else
+ sparc_memory_model = SMM_SC;
+ }
+
/* Supply a default value for align_functions. */
if (flag_align_functions && !str_align_functions)
{
if (!TARGET_ARCH64)
targetm.asm_out.unaligned_op.di = NULL;
- /* Do various machine dependent initializations. */
- sparc_init_modes ();
-
- /* Set up function hooks. */
- init_machine_status = sparc_init_machine_status;
-
+ /* Set the processor costs. */
switch (sparc_cpu)
{
case PROCESSOR_V7:
gcc_unreachable ();
};
- if (sparc_memory_model == SMM_DEFAULT)
- {
- /* Choose the memory model for the operating system. */
- enum sparc_memory_model_type os_default = SUBTARGET_DEFAULT_MEMORY_MODEL;
- if (os_default != SMM_DEFAULT)
- sparc_memory_model = os_default;
- /* Choose the most relaxed model for the processor. */
- else if (TARGET_V9)
- sparc_memory_model = SMM_RMO;
- else if (TARGET_LEON3)
- sparc_memory_model = SMM_TSO;
- else if (TARGET_LEON)
- sparc_memory_model = SMM_SC;
- else if (TARGET_V8)
- sparc_memory_model = SMM_PSO;
- else
- sparc_memory_model = SMM_SC;
- }
-
-#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
- if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
- target_flags |= MASK_LONG_DOUBLE_128;
-#endif
-
- if (TARGET_DEBUG_OPTIONS)
- dump_target_flags ("Final target_flags", target_flags);
-
- /* PARAM_SIMULTANEOUS_PREFETCHES is the number of prefetches that
+ /* param_simultaneous_prefetches is the number of prefetches that
can run at the same time. More important, it is the threshold
defining when additional prefetches will be dropped by the
hardware.
single-threaded program. Experimental results show that setting
this parameter to 32 works well when the number of threads is not
high. */
- maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
- ((sparc_cpu == PROCESSOR_ULTRASPARC
- || sparc_cpu == PROCESSOR_NIAGARA
- || sparc_cpu == PROCESSOR_NIAGARA2
- || sparc_cpu == PROCESSOR_NIAGARA3
- || sparc_cpu == PROCESSOR_NIAGARA4)
- ? 2
- : (sparc_cpu == PROCESSOR_ULTRASPARC3
- ? 8 : ((sparc_cpu == PROCESSOR_NIAGARA7
- || sparc_cpu == PROCESSOR_M8)
- ? 32 : 3))),
- global_options.x_param_values,
- global_options_set.x_param_values);
-
- /* PARAM_L1_CACHE_LINE_SIZE is the size of the L1 cache line, in
+ SET_OPTION_IF_UNSET (&global_options, &global_options_set,
+ param_simultaneous_prefetches,
+ ((sparc_cpu == PROCESSOR_ULTRASPARC
+ || sparc_cpu == PROCESSOR_NIAGARA
+ || sparc_cpu == PROCESSOR_NIAGARA2
+ || sparc_cpu == PROCESSOR_NIAGARA3
+ || sparc_cpu == PROCESSOR_NIAGARA4)
+ ? 2
+ : (sparc_cpu == PROCESSOR_ULTRASPARC3
+ ? 8 : ((sparc_cpu == PROCESSOR_NIAGARA7
+ || sparc_cpu == PROCESSOR_M8)
+ ? 32 : 3))));
+
+ /* param_l1_cache_line_size is the size of the L1 cache line, in
bytes.
The Oracle SPARC Architecture (previously the UltraSPARC
L2 and L3, but only 32B are brought into the L1D$. (Assuming it
is a read_n prefetch, which is the only type which allocates to
the L1.) */
- maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
- (sparc_cpu == PROCESSOR_M8
- ? 64 : 32),
- global_options.x_param_values,
- global_options_set.x_param_values);
+ SET_OPTION_IF_UNSET (&global_options, &global_options_set,
+ param_l1_cache_line_size,
+ (sparc_cpu == PROCESSOR_M8 ? 64 : 32));
- /* PARAM_L1_CACHE_SIZE is the size of the L1D$ (most SPARC chips use
+ /* param_l1_cache_size is the size of the L1D$ (most SPARC chips use
Hardvard level-1 caches) in kilobytes. Both UltraSPARC and
Niagara processors feature a L1D$ of 16KB. */
- maybe_set_param_value (PARAM_L1_CACHE_SIZE,
- ((sparc_cpu == PROCESSOR_ULTRASPARC
- || sparc_cpu == PROCESSOR_ULTRASPARC3
- || sparc_cpu == PROCESSOR_NIAGARA
- || sparc_cpu == PROCESSOR_NIAGARA2
- || sparc_cpu == PROCESSOR_NIAGARA3
- || sparc_cpu == PROCESSOR_NIAGARA4
- || sparc_cpu == PROCESSOR_NIAGARA7
- || sparc_cpu == PROCESSOR_M8)
- ? 16 : 64),
- global_options.x_param_values,
- global_options_set.x_param_values);
-
-
- /* PARAM_L2_CACHE_SIZE is the size fo the L2 in kilobytes. Note
+ SET_OPTION_IF_UNSET (&global_options, &global_options_set,
+ param_l1_cache_size,
+ ((sparc_cpu == PROCESSOR_ULTRASPARC
+ || sparc_cpu == PROCESSOR_ULTRASPARC3
+ || sparc_cpu == PROCESSOR_NIAGARA
+ || sparc_cpu == PROCESSOR_NIAGARA2
+ || sparc_cpu == PROCESSOR_NIAGARA3
+ || sparc_cpu == PROCESSOR_NIAGARA4
+ || sparc_cpu == PROCESSOR_NIAGARA7
+ || sparc_cpu == PROCESSOR_M8)
+ ? 16 : 64));
+
+ /* param_l2_cache_size is the size fo the L2 in kilobytes. Note
that 512 is the default in params.def. */
- maybe_set_param_value (PARAM_L2_CACHE_SIZE,
- ((sparc_cpu == PROCESSOR_NIAGARA4
- || sparc_cpu == PROCESSOR_M8)
- ? 128 : (sparc_cpu == PROCESSOR_NIAGARA7
- ? 256 : 512)),
- global_options.x_param_values,
- global_options_set.x_param_values);
+ SET_OPTION_IF_UNSET (&global_options, &global_options_set,
+ param_l2_cache_size,
+ ((sparc_cpu == PROCESSOR_NIAGARA4
+ || sparc_cpu == PROCESSOR_M8)
+ ? 128 : (sparc_cpu == PROCESSOR_NIAGARA7
+ ? 256 : 512)));
/* Disable save slot sharing for call-clobbered registers by default.
redundant 32-to-64-bit extensions. */
if (!global_options_set.x_flag_ree && TARGET_ARCH32)
flag_ree = 0;
+
+ /* Do various machine dependent initializations. */
+ sparc_init_modes ();
+
+ /* Set up function hooks. */
+ init_machine_status = sparc_init_machine_status;
}
\f
/* Miscellaneous utilities. */
temp = gen_rtx_REG (DImode, REGNO (temp));
}
- /* SPARC-V9 code-model support. */
- switch (sparc_cmodel)
+ /* SPARC-V9 code model support. */
+ switch (sparc_code_model)
{
case CM_MEDLOW:
/* The range spanned by all instructions in the object is less
case UNGT:
case UNGE:
case UNEQ:
- case LTGT:
return CCFPmode;
case LT:
case LE:
case GT:
case GE:
+ case LTGT:
return CCFPEmode;
default:
}
\f
/* Global Offset Table support. */
+static GTY(()) rtx got_symbol_rtx = NULL_RTX;
+static GTY(()) rtx got_register_rtx = NULL_RTX;
static GTY(()) rtx got_helper_rtx = NULL_RTX;
-static GTY(()) rtx global_offset_table_rtx = NULL_RTX;
-/* Return the SYMBOL_REF for the Global Offset Table. */
+static GTY(()) bool got_helper_needed = false;
-static GTY(()) rtx sparc_got_symbol = NULL_RTX;
+/* Return the SYMBOL_REF for the Global Offset Table. */
static rtx
sparc_got (void)
{
- if (!sparc_got_symbol)
- sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
+ if (!got_symbol_rtx)
+ got_symbol_rtx = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
- return sparc_got_symbol;
+ return got_symbol_rtx;
+}
+
+/* Wrapper around the load_pcrel_sym{si,di} patterns. */
+
+static rtx
+gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2)
+{
+ int orig_flag_pic = flag_pic;
+ rtx insn;
+
+ /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
+ flag_pic = 0;
+ if (TARGET_ARCH64)
+ insn = gen_load_pcrel_symdi (op0, op1, op2, GEN_INT (REGNO (op0)));
+ else
+ insn = gen_load_pcrel_symsi (op0, op1, op2, GEN_INT (REGNO (op0)));
+ flag_pic = orig_flag_pic;
+
+ return insn;
+}
+
+/* Output the load_pcrel_sym{si,di} patterns. */
+
+const char *
+output_load_pcrel_sym (rtx *operands)
+{
+ if (flag_delayed_branch)
+ {
+ output_asm_insn ("sethi\t%%hi(%a1-4), %0", operands);
+ output_asm_insn ("call\t%a2", operands);
+ output_asm_insn (" add\t%0, %%lo(%a1+4), %0", operands);
+ }
+ else
+ {
+ output_asm_insn ("sethi\t%%hi(%a1-8), %0", operands);
+ output_asm_insn ("add\t%0, %%lo(%a1-4), %0", operands);
+ output_asm_insn ("call\t%a2", operands);
+ output_asm_insn (" nop", NULL);
+ }
+
+ if (operands[2] == got_helper_rtx)
+ got_helper_needed = true;
+
+ return "";
+}
+
+#ifdef HAVE_GAS_HIDDEN
+# define USE_HIDDEN_LINKONCE 1
+#else
+# define USE_HIDDEN_LINKONCE 0
+#endif
+
+/* Emit code to load the GOT register. */
+
+void
+load_got_register (void)
+{
+ rtx insn;
+
+ if (TARGET_VXWORKS_RTP)
+ {
+ if (!got_register_rtx)
+ got_register_rtx = pic_offset_table_rtx;
+
+ insn = gen_vxworks_load_got ();
+ }
+ else
+ {
+ if (!got_register_rtx)
+ got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
+
+ /* The GOT symbol is subject to a PC-relative relocation so we need a
+ helper function to add the PC value and thus get the final value. */
+ if (!got_helper_rtx)
+ {
+ char name[32];
+
+ /* Skip the leading '%' as that cannot be used in a symbol name. */
+ if (USE_HIDDEN_LINKONCE)
+ sprintf (name, "__sparc_get_pc_thunk.%s",
+ reg_names[REGNO (got_register_rtx)] + 1);
+ else
+ ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC",
+ REGNO (got_register_rtx));
+
+ got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
+ }
+
+ insn
+ = gen_load_pcrel_sym (got_register_rtx, sparc_got (), got_helper_rtx);
+ }
+
+ emit_insn (insn);
}
/* Ensure that we are not using patterns that are not OK with PIC. */
return true;
if (!HARD_REGISTER_P (pic_offset_table_rtx)
- && (HARD_REGISTER_P (x) || lra_in_progress)
+ && (HARD_REGISTER_P (x) || lra_in_progress || reload_in_progress)
&& ORIGINAL_REGNO (x) == REGNO (pic_offset_table_rtx))
return true;
if (TARGET_SUN_TLS && TARGET_ARCH32)
{
load_got_register ();
- return global_offset_table_rtx;
+ return got_register_rtx;
}
/* In all other cases, we load a new pseudo with the GOT symbol. */
gcc_assert (can_create_pseudo_p ());
if (GET_CODE (addr) == SYMBOL_REF)
+ /* Although the various sethi/or sequences generate SImode values, many of
+ them can be transformed by the linker when relaxing and, if relaxing to
+ local-exec, will become a sethi/xor pair, which is signed and therefore
+ a full DImode value in 64-bit mode. Thus we must use Pmode, lest these
+ values be spilled onto the stack in 64-bit mode. */
switch (SYMBOL_REF_TLS_MODEL (addr))
{
case TLS_MODEL_GLOBAL_DYNAMIC:
start_sequence ();
- temp1 = gen_reg_rtx (SImode);
- temp2 = gen_reg_rtx (SImode);
+ temp1 = gen_reg_rtx (Pmode);
+ temp2 = gen_reg_rtx (Pmode);
ret = gen_reg_rtx (Pmode);
o0 = gen_rtx_REG (Pmode, 8);
got = sparc_tls_got ();
- emit_insn (gen_tgd_hi22 (temp1, addr));
- emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
if (TARGET_ARCH32)
{
- emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
- insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
+ emit_insn (gen_tgd_hi22si (temp1, addr));
+ emit_insn (gen_tgd_lo10si (temp2, temp1, addr));
+ emit_insn (gen_tgd_addsi (o0, got, temp2, addr));
+ insn = emit_call_insn (gen_tgd_callsi (o0, sparc_tls_get_addr (),
addr, const1_rtx));
}
else
{
- emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
- insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
+ emit_insn (gen_tgd_hi22di (temp1, addr));
+ emit_insn (gen_tgd_lo10di (temp2, temp1, addr));
+ emit_insn (gen_tgd_adddi (o0, got, temp2, addr));
+ insn = emit_call_insn (gen_tgd_calldi (o0, sparc_tls_get_addr (),
addr, const1_rtx));
}
use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
+ RTL_CONST_CALL_P (insn) = 1;
insn = get_insns ();
end_sequence ();
emit_libcall_block (insn, ret, o0, addr);
case TLS_MODEL_LOCAL_DYNAMIC:
start_sequence ();
- temp1 = gen_reg_rtx (SImode);
- temp2 = gen_reg_rtx (SImode);
+ temp1 = gen_reg_rtx (Pmode);
+ temp2 = gen_reg_rtx (Pmode);
temp3 = gen_reg_rtx (Pmode);
ret = gen_reg_rtx (Pmode);
o0 = gen_rtx_REG (Pmode, 8);
got = sparc_tls_got ();
- emit_insn (gen_tldm_hi22 (temp1));
- emit_insn (gen_tldm_lo10 (temp2, temp1));
if (TARGET_ARCH32)
{
- emit_insn (gen_tldm_add32 (o0, got, temp2));
- insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
+ emit_insn (gen_tldm_hi22si (temp1));
+ emit_insn (gen_tldm_lo10si (temp2, temp1));
+ emit_insn (gen_tldm_addsi (o0, got, temp2));
+ insn = emit_call_insn (gen_tldm_callsi (o0, sparc_tls_get_addr (),
const1_rtx));
}
else
{
- emit_insn (gen_tldm_add64 (o0, got, temp2));
- insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
+ emit_insn (gen_tldm_hi22di (temp1));
+ emit_insn (gen_tldm_lo10di (temp2, temp1));
+ emit_insn (gen_tldm_adddi (o0, got, temp2));
+ insn = emit_call_insn (gen_tldm_calldi (o0, sparc_tls_get_addr (),
const1_rtx));
}
use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
+ RTL_CONST_CALL_P (insn) = 1;
insn = get_insns ();
end_sequence ();
+ /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
+ share the LD_BASE result with other LD model accesses. */
emit_libcall_block (insn, temp3, o0,
gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
UNSPEC_TLSLD_BASE));
- temp1 = gen_reg_rtx (SImode);
- temp2 = gen_reg_rtx (SImode);
- emit_insn (gen_tldo_hix22 (temp1, addr));
- emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
+ temp1 = gen_reg_rtx (Pmode);
+ temp2 = gen_reg_rtx (Pmode);
if (TARGET_ARCH32)
- emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
+ {
+ emit_insn (gen_tldo_hix22si (temp1, addr));
+ emit_insn (gen_tldo_lox10si (temp2, temp1, addr));
+ emit_insn (gen_tldo_addsi (ret, temp3, temp2, addr));
+ }
else
- emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
+ {
+ emit_insn (gen_tldo_hix22di (temp1, addr));
+ emit_insn (gen_tldo_lox10di (temp2, temp1, addr));
+ emit_insn (gen_tldo_adddi (ret, temp3, temp2, addr));
+ }
break;
case TLS_MODEL_INITIAL_EXEC:
- temp1 = gen_reg_rtx (SImode);
- temp2 = gen_reg_rtx (SImode);
+ temp1 = gen_reg_rtx (Pmode);
+ temp2 = gen_reg_rtx (Pmode);
temp3 = gen_reg_rtx (Pmode);
got = sparc_tls_got ();
- emit_insn (gen_tie_hi22 (temp1, addr));
- emit_insn (gen_tie_lo10 (temp2, temp1, addr));
if (TARGET_ARCH32)
- emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
+ {
+ emit_insn (gen_tie_hi22si (temp1, addr));
+ emit_insn (gen_tie_lo10si (temp2, temp1, addr));
+ emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
+ }
else
- emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
+ {
+ emit_insn (gen_tie_hi22di (temp1, addr));
+ emit_insn (gen_tie_lo10di (temp2, temp1, addr));
+ emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
+ }
if (TARGET_SUN_TLS)
{
ret = gen_reg_rtx (Pmode);
if (TARGET_ARCH32)
- emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
+ emit_insn (gen_tie_addsi (ret, gen_rtx_REG (Pmode, 7),
temp3, addr));
else
- emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
+ emit_insn (gen_tie_adddi (ret, gen_rtx_REG (Pmode, 7),
temp3, addr));
}
else
temp2 = gen_reg_rtx (Pmode);
if (TARGET_ARCH32)
{
- emit_insn (gen_tle_hix22_sp32 (temp1, addr));
- emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
+ emit_insn (gen_tle_hix22si (temp1, addr));
+ emit_insn (gen_tle_lox10si (temp2, temp1, addr));
}
else
{
- emit_insn (gen_tle_hix22_sp64 (temp1, addr));
- emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
+ emit_insn (gen_tle_hix22di (temp1, addr));
+ emit_insn (gen_tle_lox10di (temp2, temp1, addr));
}
ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
break;
{
x = delegitimize_mem_from_attrs (x);
- if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 1)) == UNSPEC)
- switch (XINT (XEXP (x, 1), 1))
+ if (GET_CODE (x) == LO_SUM)
+ x = XEXP (x, 1);
+
+ if (GET_CODE (x) == UNSPEC)
+ switch (XINT (x, 1))
{
case UNSPEC_MOVE_PIC:
case UNSPEC_TLSLE:
- x = XVECEXP (XEXP (x, 1), 0, 0);
+ x = XVECEXP (x, 0, 0);
+ gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ break;
+ case UNSPEC_MOVE_GOTDATA:
+ x = XVECEXP (x, 0, 2);
gcc_assert (GET_CODE (x) == SYMBOL_REF);
break;
default:
/* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
if (GET_CODE (x) == MINUS
- && sparc_pic_register_p (XEXP (x, 0))
- && GET_CODE (XEXP (x, 1)) == LO_SUM
- && GET_CODE (XEXP (XEXP (x, 1), 1)) == UNSPEC
- && XINT (XEXP (XEXP (x, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL)
+ && (XEXP (x, 0) == got_register_rtx
+ || sparc_pic_register_p (XEXP (x, 0))))
{
- x = XVECEXP (XEXP (XEXP (x, 1), 1), 0, 0);
- gcc_assert (GET_CODE (x) == LABEL_REF
- || (GET_CODE (x) == CONST
- && GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT));
+ rtx y = XEXP (x, 1);
+
+ if (GET_CODE (y) == LO_SUM)
+ y = XEXP (y, 1);
+
+ if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_MOVE_PIC_LABEL)
+ {
+ x = XVECEXP (y, 0, 0);
+ gcc_assert (GET_CODE (x) == LABEL_REF
+ || (GET_CODE (x) == CONST
+ && GET_CODE (XEXP (x, 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
+ && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT));
+ }
}
return x;
&& GET_MODE (x) == SImode
&& GET_CODE (x) != LO_SUM
&& GET_CODE (x) != HIGH
- && sparc_cmodel <= CM_MEDLOW
+ && sparc_code_model <= CM_MEDLOW
&& !(flag_pic
&& (symbolic_operand (x, Pmode) || pic_address_needs_scratch (x))))
{
return false;
}
-#ifdef HAVE_GAS_HIDDEN
-# define USE_HIDDEN_LINKONCE 1
-#else
-# define USE_HIDDEN_LINKONCE 0
-#endif
-
-static void
-get_pc_thunk_name (char name[32], unsigned int regno)
-{
- const char *reg_name = reg_names[regno];
-
- /* Skip the leading '%' as that cannot be used in a
- symbol name. */
- reg_name += 1;
-
- if (USE_HIDDEN_LINKONCE)
- sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
- else
- ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
-}
-
-/* Wrapper around the load_pcrel_sym{si,di} patterns. */
-
-static rtx
-gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2)
-{
- int orig_flag_pic = flag_pic;
- rtx insn;
-
- /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
- flag_pic = 0;
- if (TARGET_ARCH64)
- insn = gen_load_pcrel_symdi (op0, op1, op2, GEN_INT (REGNO (op0)));
- else
- insn = gen_load_pcrel_symsi (op0, op1, op2, GEN_INT (REGNO (op0)));
- flag_pic = orig_flag_pic;
-
- return insn;
-}
-
-/* Emit code to load the GOT register. */
-
-void
-load_got_register (void)
-{
- if (!global_offset_table_rtx)
- global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
-
- if (TARGET_VXWORKS_RTP)
- emit_insn (gen_vxworks_load_got ());
- else
- {
- /* The GOT symbol is subject to a PC-relative relocation so we need a
- helper function to add the PC value and thus get the final value. */
- if (!got_helper_rtx)
- {
- char name[32];
- get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
- got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
- }
-
- emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (),
- got_helper_rtx));
- }
-}
-
/* Emit a call instruction with the pattern given by PAT. ADDR is the
address of the call target. */
save_global_or_fp_reg_p (unsigned int regno,
int leaf_function ATTRIBUTE_UNUSED)
{
- return !call_used_regs[regno] && df_regs_ever_live_p (regno);
+ return !call_used_or_fixed_reg_p (regno) && df_regs_ever_live_p (regno);
}
/* Return whether the return address register (%i7) is needed. */
save_local_or_in_reg_p (unsigned int regno, int leaf_function)
{
/* General case: call-saved registers live at some point. */
- if (!call_used_regs[regno] && df_regs_ever_live_p (regno))
+ if (!call_used_or_fixed_reg_p (regno) && df_regs_ever_live_p (regno))
return true;
/* Frame pointer register (%fp) if needed. */
return true;
/* GOT register (%l7) if needed. */
- if (regno == PIC_OFFSET_TABLE_REGNUM && crtl->uses_pic_offset_table)
+ if (got_register_rtx && regno == REGNO (got_register_rtx))
return true;
/* If the function accesses prior frames, the frame pointer and the return
void
sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
{
-#ifdef HAVE_AS_REGISTER_PSEUDO_OP
int i;
if (TARGET_ARCH32)
}
if (i == 3) i = 5;
}
-#endif
}
#define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
Note #1: complex floating-point types follow the extended SPARC ABIs as
implemented by the Sun compiler.
-Note #2: integral vector types follow the scalar floating-point types
+Note #2: integer vector types follow the scalar floating-point types
conventions to match what is implemented by the Sun VIS SDK.
Note #3: floating-point vector types follow the aggregate types
return TARGET_ARCH64 ? true : false;
}
+/* Handle the TARGET_PASS_BY_REFERENCE target hook.
+ Specify whether to pass the argument by reference. */
+
+static bool
+sparc_pass_by_reference (cumulative_args_t, const function_arg_info &arg)
+{
+ tree type = arg.type;
+ machine_mode mode = arg.mode;
+ if (TARGET_ARCH32)
+ /* Original SPARC 32-bit ABI says that structures and unions,
+ and quad-precision floats are passed by reference.
+ All other base types are passed in registers.
+
+ Extended ABI (as implemented by the Sun compiler) says that all
+ complex floats are passed by reference. Pass complex integers
+ in registers up to 8 bytes. More generally, enforce the 2-word
+ cap for passing arguments in registers.
+
+ Vector ABI (as implemented by the Sun VIS SDK) says that integer
+ vectors are passed like floats of the same size, that is in
+ registers up to 8 bytes. Pass all vector floats by reference
+ like structure and unions. */
+ return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
+ || mode == SCmode
+ /* Catch CDImode, TFmode, DCmode and TCmode. */
+ || GET_MODE_SIZE (mode) > 8
+ || (type
+ && VECTOR_TYPE_P (type)
+ && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
+ else
+ /* Original SPARC 64-bit ABI says that structures and unions
+ smaller than 16 bytes are passed in registers, as well as
+ all other base types.
+
+ Extended ABI (as implemented by the Sun compiler) says that
+ complex floats are passed in registers up to 16 bytes. Pass
+ all complex integers in registers up to 16 bytes. More generally,
+ enforce the 2-word cap for passing arguments in registers.
+
+ Vector ABI (as implemented by the Sun VIS SDK) says that integer
+ vectors are passed like floats of the same size, that is in
+ registers (up to 16 bytes). Pass all vector floats like structure
+ and unions. */
+ return ((type
+ && (AGGREGATE_TYPE_P (type) || VECTOR_TYPE_P (type))
+ && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
+ /* Catch CTImode and TCmode. */
+ || GET_MODE_SIZE (mode) > 16);
+}
+
/* Traverse the record TYPE recursively and call FUNC on its fields.
NAMED is true if this is for a named parameter. DATA is passed
to FUNC for each field. OFFSET is the starting position and
PACKED is true if we are inside a packed record. */
-template <typename T, void Func (const_tree, HOST_WIDE_INT, bool, T*)>
+template <typename T, void Func (const_tree, int, bool, T*)>
static void
traverse_record_type (const_tree type, bool named, T *data,
- HOST_WIDE_INT offset = 0, bool packed = false)
+ int offset = 0, bool packed = false)
{
/* The ABI obviously doesn't specify how packed structures are passed.
These are passed in integer regs if possible, otherwise memory. */
if (!DECL_SIZE (field) || integer_zerop (DECL_SIZE (field)))
continue;
- HOST_WIDE_INT bitpos = offset;
+ int bitpos = offset;
if (TREE_CODE (DECL_FIELD_OFFSET (field)) == INTEGER_CST)
bitpos += int_bit_position (field);
/* A subroutine of function_arg_slotno. Classify the field. */
inline void
-classify_registers (const_tree, HOST_WIDE_INT bitpos, bool fp,
- classify_data_t *data)
+classify_registers (const_tree, int bitpos, bool fp, classify_data_t *data)
{
if (fp)
{
const_tree type, bool named, bool incoming,
int *pregno, int *ppadding)
{
- int regbase = (incoming
- ? SPARC_INCOMING_INT_ARG_FIRST
- : SPARC_OUTGOING_INT_ARG_FIRST);
- int slotno = cum->words;
- enum mode_class mclass;
- int regno;
+ const int regbase
+ = incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST;
+ int slotno = cum->words, regno;
+ enum mode_class mclass = GET_MODE_CLASS (mode);
- *ppadding = 0;
+ /* Silence warnings in the callers. */
+ *pregno = -1;
+ *ppadding = -1;
if (type && TREE_ADDRESSABLE (type))
return -1;
- if (TARGET_ARCH32
- && mode == BLKmode
- && type
- && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
- return -1;
-
- /* For SPARC64, objects requiring 16-byte alignment get it. */
+ /* In 64-bit mode, objects requiring 16-byte alignment get it. */
if (TARGET_ARCH64
&& (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128
&& (slotno & 1) != 0)
- slotno++, *ppadding = 1;
+ {
+ slotno++;
+ *ppadding = 1;
+ }
+ else
+ *ppadding = 0;
- mclass = GET_MODE_CLASS (mode);
- if (type && TREE_CODE (type) == VECTOR_TYPE)
+ /* Vector types deserve special treatment because they are polymorphic wrt
+ their mode, depending upon whether VIS instructions are enabled. */
+ if (type && VECTOR_TYPE_P (type))
{
- /* Vector types deserve special treatment because they are
- polymorphic wrt their mode, depending upon whether VIS
- instructions are enabled. */
if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
{
/* The SPARC port defines no floating-point vector modes. */
}
else
{
- /* Integral vector types should either have a vector
+ /* Integer vector types should either have a vector
mode or an integral mode, because we are guaranteed
by pass_by_reference that their size is not greater
than 16 bytes and TImode is 16-byte wide. */
gcc_assert (mode != BLKmode);
- /* Vector integers are handled like floats according to
+ /* Integer vectors are handled like floats as per
the Sun VIS SDK. */
mclass = MODE_FLOAT;
}
break;
case MODE_RANDOM:
+ /* MODE is VOIDmode when generating the actual call. */
if (mode == VOIDmode)
- /* MODE is VOIDmode when generating the actual call. */
return -1;
- gcc_assert (mode == BLKmode);
-
- if (TARGET_ARCH32
- || !type
- || (TREE_CODE (type) != RECORD_TYPE
- && TREE_CODE (type) != VECTOR_TYPE))
- {
- /* If all arg slots are filled, then must pass on stack. */
- if (slotno >= SPARC_INT_ARG_MAX)
- return -1;
-
- regno = regbase + slotno;
- }
- else /* TARGET_ARCH64 && type */
+ if (TARGET_64BIT && TARGET_FPU && named
+ && type
+ && (TREE_CODE (type) == RECORD_TYPE || VECTOR_TYPE_P (type)))
{
/* If all arg slots are filled, then must pass on stack. */
if (slotno >= SPARC_FP_ARG_MAX)
if (slotno >= SPARC_INT_ARG_MAX)
return -1;
}
+
+ /* PREGNO isn't set since both int and FP regs can be used. */
+ return slotno;
}
- /* PREGNO isn't set since both int and FP regs can be used. */
- return slotno;
+ regno = SPARC_FP_ARG_FIRST + slotno * 2;
+ }
+ else
+ {
+ /* If all arg slots are filled, then must pass on stack. */
+ if (slotno >= SPARC_INT_ARG_MAX)
+ return -1;
+
+ regno = regbase + slotno;
}
break;
true if at least one integer register is assigned or false otherwise. */
static bool
-compute_int_layout (HOST_WIDE_INT bitpos, assign_data_t *data, int *pnregs)
+compute_int_layout (int bitpos, assign_data_t *data, int *pnregs)
{
if (data->intoffset < 0)
return false;
FP register is assigned or false otherwise. */
static bool
-compute_fp_layout (const_tree field, HOST_WIDE_INT bitpos,
- assign_data_t *data,
+compute_fp_layout (const_tree field, int bitpos, assign_data_t *data,
int *pnregs, machine_mode *pmode)
{
const int this_slotno = data->slotno + bitpos / BITS_PER_WORD;
/* Slots are counted as words while regs are counted as having the size of
the (inner) mode. */
- if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE && mode == BLKmode)
+ if (VECTOR_TYPE_P (TREE_TYPE (field)) && mode == BLKmode)
{
mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
to be assigned for FIELD and between PARMS->intoffset and BITPOS. */
inline void
-count_registers (const_tree field, HOST_WIDE_INT bitpos, bool fp,
- assign_data_t *data)
+count_registers (const_tree field, int bitpos, bool fp, assign_data_t *data)
{
if (fp)
{
structure between PARMS->intoffset and BITPOS to integer registers. */
static void
-assign_int_registers (HOST_WIDE_INT bitpos, assign_data_t *data)
+assign_int_registers (int bitpos, assign_data_t *data)
{
int intoffset = data->intoffset;
machine_mode mode;
BITPOS to FP registers. */
static void
-assign_fp_registers (const_tree field, HOST_WIDE_INT bitpos,
- assign_data_t *data)
+assign_fp_registers (const_tree field, int bitpos, assign_data_t *data)
{
int nregs;
machine_mode mode;
the structure between PARMS->intoffset and BITPOS to registers. */
inline void
-assign_registers (const_tree field, HOST_WIDE_INT bitpos, bool fp,
- assign_data_t *data)
+assign_registers (const_tree field, int bitpos, bool fp, assign_data_t *data)
{
if (fp)
{
}
}
-/* Used by function_arg and sparc_function_value_1 to implement the complex
+/* Used by function_arg and function_value to implement the complex
conventions of the 64-bit ABI for passing and returning structures.
Return an expression valid as a return value for the FUNCTION_ARG
and TARGET_FUNCTION_VALUE.
function_arg_record_value (const_tree type, machine_mode mode,
int slotno, bool named, int regbase)
{
- HOST_WIDE_INT typesize = int_size_in_bytes (type);
+ const int size = int_size_in_bytes (type);
assign_data_t data;
int nregs;
traverse_record_type<assign_data_t, count_registers> (type, named, &data);
/* Take into account pending integer fields. */
- if (compute_int_layout (typesize * BITS_PER_UNIT, &data, &nregs))
+ if (compute_int_layout (size * BITS_PER_UNIT, &data, &nregs))
data.nregs += nregs;
/* Allocate the vector and handle some annoying special cases. */
if (nregs == 0)
{
/* ??? Empty structure has no value? Duh? */
- if (typesize <= 0)
+ if (size <= 0)
{
/* Though there's nothing really to store, return a word register
anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
/* ??? C++ has structures with no fields, and yet a size. Give up
for now and pass everything back in integer registers. */
- nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+ nregs = CEIL_NWORDS (size);
if (nregs + slotno > SPARC_INT_ARG_MAX)
nregs = SPARC_INT_ARG_MAX - slotno;
}
traverse_record_type<assign_data_t, assign_registers> (type, named, &data);
/* Assign pending integer fields. */
- assign_int_registers (typesize * BITS_PER_UNIT, &data);
+ assign_int_registers (size * BITS_PER_UNIT, &data);
gcc_assert (data.nregs == nregs);
return data.ret;
}
-/* Used by function_arg and sparc_function_value_1 to implement the conventions
+/* Used by function_arg and function_value to implement the conventions
of the 64-bit ABI for passing and returning unions.
Return an expression valid as a return value for the FUNCTION_ARG
and TARGET_FUNCTION_VALUE.
SIZE is the size in bytes of the union.
MODE is the argument's machine mode.
+ SLOTNO is the index number of the argument's slot in the parameter array.
REGNO is the hard register the union will be passed in. */
static rtx
-function_arg_union_value (int size, machine_mode mode, int slotno,
- int regno)
+function_arg_union_value (int size, machine_mode mode, int slotno, int regno)
{
- int nwords = CEIL_NWORDS (size), i;
- rtx regs;
+ unsigned int nwords;
- /* See comment in previous function for empty structures. */
- if (nwords == 0)
+ /* See comment in function_arg_record_value for empty structures. */
+ if (size <= 0)
return gen_rtx_REG (mode, regno);
if (slotno == SPARC_INT_ARG_MAX - 1)
nwords = 1;
+ else
+ nwords = CEIL_NWORDS (size);
- regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
+ rtx regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
- for (i = 0; i < nwords; i++)
- {
- /* Unions are passed left-justified. */
- XVECEXP (regs, 0, i)
- = gen_rtx_EXPR_LIST (VOIDmode,
- gen_rtx_REG (word_mode, regno),
- GEN_INT (UNITS_PER_WORD * i));
- regno++;
- }
+ /* Unions are passed left-justified. */
+ for (unsigned int i = 0; i < nwords; i++)
+ XVECEXP (regs, 0, i)
+ = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (word_mode, regno + i),
+ GEN_INT (UNITS_PER_WORD * i));
return regs;
}
-/* Used by function_arg and sparc_function_value_1 to implement the conventions
- for passing and returning BLKmode vectors.
+/* Used by function_arg and function_value to implement the conventions
+ of the 64-bit ABI for passing and returning BLKmode vectors.
Return an expression valid as a return value for the FUNCTION_ARG
and TARGET_FUNCTION_VALUE.
SIZE is the size in bytes of the vector.
- REGNO is the FP hard register the vector will be passed in. */
+ SLOTNO is the index number of the argument's slot in the parameter array.
+ NAMED is true if this argument is a named parameter
+ (otherwise it is an extra parameter matching an ellipsis).
+ REGNO is the hard register the vector will be passed in. */
static rtx
-function_arg_vector_value (int size, int regno)
+function_arg_vector_value (int size, int slotno, bool named, int regno)
{
- const int nregs = MAX (1, size / 8);
- rtx regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
+ const int mult = (named ? 2 : 1);
+ unsigned int nwords;
+
+ if (slotno == (named ? SPARC_FP_ARG_MAX : SPARC_INT_ARG_MAX) - 1)
+ nwords = 1;
+ else
+ nwords = CEIL_NWORDS (size);
- if (size < 8)
+ rtx regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nwords));
+
+ if (size < UNITS_PER_WORD)
XVECEXP (regs, 0, 0)
= gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_REG (SImode, regno),
const0_rtx);
else
- for (int i = 0; i < nregs; i++)
+ for (unsigned int i = 0; i < nwords; i++)
XVECEXP (regs, 0, i)
= gen_rtx_EXPR_LIST (VOIDmode,
- gen_rtx_REG (DImode, regno + 2*i),
- GEN_INT (i*8));
+ gen_rtx_REG (word_mode, regno + i * mult),
+ GEN_INT (i * UNITS_PER_WORD));
return regs;
}
CUM is a variable of type CUMULATIVE_ARGS which gives info about
the preceding args and about the function being called.
- MODE is the argument's machine mode.
- TYPE is the data type of the argument (as a tree).
- This is null for libcalls where that information may
- not be available.
- NAMED is true if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis).
+ ARG is a description of the argument.
INCOMING_P is false for TARGET_FUNCTION_ARG, true for
TARGET_FUNCTION_INCOMING_ARG. */
static rtx
-sparc_function_arg_1 (cumulative_args_t cum_v, machine_mode mode,
- const_tree type, bool named, bool incoming)
+sparc_function_arg_1 (cumulative_args_t cum_v, const function_arg_info &arg,
+ bool incoming)
{
const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
-
- int regbase = (incoming
- ? SPARC_INCOMING_INT_ARG_FIRST
- : SPARC_OUTGOING_INT_ARG_FIRST);
+ const int regbase
+ = incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST;
int slotno, regno, padding;
+ tree type = arg.type;
+ machine_mode mode = arg.mode;
enum mode_class mclass = GET_MODE_CLASS (mode);
+ bool named = arg.named;
- slotno = function_arg_slotno (cum, mode, type, named, incoming,
- ®no, &padding);
+ slotno
+ = function_arg_slotno (cum, mode, type, named, incoming, ®no, &padding);
if (slotno == -1)
return 0;
- /* Vector types deserve special treatment because they are polymorphic wrt
- their mode, depending upon whether VIS instructions are enabled. */
- if (type && TREE_CODE (type) == VECTOR_TYPE)
- {
- HOST_WIDE_INT size = int_size_in_bytes (type);
- gcc_assert ((TARGET_ARCH32 && size <= 8)
- || (TARGET_ARCH64 && size <= 16));
-
- if (mode == BLKmode)
- return function_arg_vector_value (size, SPARC_FP_ARG_FIRST + 2*slotno);
-
- mclass = MODE_FLOAT;
- }
+ /* Integer vectors are handled like floats as per the Sun VIS SDK. */
+ if (type && VECTOR_INTEGER_TYPE_P (type))
+ mclass = MODE_FLOAT;
if (TARGET_ARCH32)
return gen_rtx_REG (mode, regno);
and are promoted to registers if possible. */
if (type && TREE_CODE (type) == RECORD_TYPE)
{
- HOST_WIDE_INT size = int_size_in_bytes (type);
+ const int size = int_size_in_bytes (type);
gcc_assert (size <= 16);
return function_arg_record_value (type, mode, slotno, named, regbase);
/* Unions up to 16 bytes in size are passed in integer registers. */
else if (type && TREE_CODE (type) == UNION_TYPE)
{
- HOST_WIDE_INT size = int_size_in_bytes (type);
+ const int size = int_size_in_bytes (type);
gcc_assert (size <= 16);
return function_arg_union_value (size, mode, slotno, regno);
}
+ /* Floating-point vectors up to 16 bytes are passed in registers. */
+ else if (type && VECTOR_TYPE_P (type) && mode == BLKmode)
+ {
+ const int size = int_size_in_bytes (type);
+ gcc_assert (size <= 16);
+
+ return function_arg_vector_value (size, slotno, named, regno);
+ }
+
/* v9 fp args in reg slots beyond the int reg slots get passed in regs
but also have the slot allocated for them.
If no prototype is in scope fp values in register slots get passed
corresponding to the size of the type. */
else if (type && AGGREGATE_TYPE_P (type))
{
- HOST_WIDE_INT size = int_size_in_bytes (type);
+ const int size = int_size_in_bytes (type);
gcc_assert (size <= 16);
mode = int_mode_for_size (size * BITS_PER_UNIT, 0).else_blk ();
/* Handle the TARGET_FUNCTION_ARG target hook. */
static rtx
-sparc_function_arg (cumulative_args_t cum, machine_mode mode,
- const_tree type, bool named)
+sparc_function_arg (cumulative_args_t cum, const function_arg_info &arg)
{
- return sparc_function_arg_1 (cum, mode, type, named, false);
+ return sparc_function_arg_1 (cum, arg, false);
}
/* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
static rtx
-sparc_function_incoming_arg (cumulative_args_t cum, machine_mode mode,
- const_tree type, bool named)
+sparc_function_incoming_arg (cumulative_args_t cum,
+ const function_arg_info &arg)
{
- return sparc_function_arg_1 (cum, mode, type, named, true);
+ return sparc_function_arg_1 (cum, arg, true);
}
/* For sparc64, objects requiring 16 byte alignment are passed that way. */
mode] will be split between that reg and memory. */
static int
-sparc_arg_partial_bytes (cumulative_args_t cum, machine_mode mode,
- tree type, bool named)
+sparc_arg_partial_bytes (cumulative_args_t cum, const function_arg_info &arg)
{
int slotno, regno, padding;
/* We pass false for incoming here, it doesn't matter. */
- slotno = function_arg_slotno (get_cumulative_args (cum), mode, type, named,
- false, ®no, &padding);
+ slotno = function_arg_slotno (get_cumulative_args (cum), arg.mode, arg.type,
+ arg.named, false, ®no, &padding);
if (slotno == -1)
return 0;
if (TARGET_ARCH32)
{
- if ((slotno + (mode == BLKmode
- ? CEIL_NWORDS (int_size_in_bytes (type))
- : CEIL_NWORDS (GET_MODE_SIZE (mode))))
- > SPARC_INT_ARG_MAX)
- return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD;
+ /* We are guaranteed by pass_by_reference that the size of the
+ argument is not greater than 8 bytes, so we only need to return
+ one word if the argument is partially passed in registers. */
+ const int size = GET_MODE_SIZE (arg.mode);
+
+ if (size > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1)
+ return UNITS_PER_WORD;
}
else
{
/* We are guaranteed by pass_by_reference that the size of the
argument is not greater than 16 bytes, so we only need to return
one word if the argument is partially passed in registers. */
-
- if (type && AGGREGATE_TYPE_P (type))
+ if (arg.aggregate_type_p ())
{
- int size = int_size_in_bytes (type);
+ const int size = int_size_in_bytes (arg.type);
if (size > UNITS_PER_WORD
&& (slotno == SPARC_INT_ARG_MAX - 1
|| slotno == SPARC_FP_ARG_MAX - 1))
return UNITS_PER_WORD;
}
- else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
- || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
- && ! (TARGET_FPU && named)))
+ else if (GET_MODE_CLASS (arg.mode) == MODE_COMPLEX_INT
+ || ((GET_MODE_CLASS (arg.mode) == MODE_COMPLEX_FLOAT
+ || (arg.type && VECTOR_TYPE_P (arg.type)))
+ && !(TARGET_FPU && arg.named)))
{
- /* The complex types are passed as packed types. */
- if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
- && slotno == SPARC_INT_ARG_MAX - 1)
+ const int size = (arg.type && VECTOR_FLOAT_TYPE_P (arg.type))
+ ? int_size_in_bytes (arg.type)
+ : GET_MODE_SIZE (arg.mode);
+
+ if (size > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1)
return UNITS_PER_WORD;
}
- else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
+ else if (GET_MODE_CLASS (arg.mode) == MODE_COMPLEX_FLOAT
+ || (arg.type && VECTOR_TYPE_P (arg.type)))
{
- if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
- > SPARC_FP_ARG_MAX)
+ const int size = (arg.type && VECTOR_FLOAT_TYPE_P (arg.type))
+ ? int_size_in_bytes (arg.type)
+ : GET_MODE_SIZE (arg.mode);
+
+ if (size > UNITS_PER_WORD && slotno == SPARC_FP_ARG_MAX - 1)
return UNITS_PER_WORD;
}
}
return 0;
}
-/* Handle the TARGET_PASS_BY_REFERENCE target hook.
- Specify whether to pass the argument by reference. */
-
-static bool
-sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
- machine_mode mode, const_tree type,
- bool named ATTRIBUTE_UNUSED)
-{
- if (TARGET_ARCH32)
- /* Original SPARC 32-bit ABI says that structures and unions,
- and quad-precision floats are passed by reference.
- All base types are passed in registers.
-
- Extended ABI (as implemented by the Sun compiler) says that all
- complex floats are passed by reference. Pass complex integers
- in registers up to 8 bytes. More generally, enforce the 2-word
- cap for passing arguments in registers.
-
- Vector ABI (as implemented by the Sun VIS SDK) says that vector
- integers are passed like floats of the same size, that is in
- registers up to 8 bytes. Pass all vector floats by reference
- like structure and unions. */
- return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
- || mode == SCmode
- /* Catch CDImode, TFmode, DCmode and TCmode. */
- || GET_MODE_SIZE (mode) > 8
- || (type
- && TREE_CODE (type) == VECTOR_TYPE
- && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
- else
- /* Original SPARC 64-bit ABI says that structures and unions
- smaller than 16 bytes are passed in registers, as well as
- all other base types.
-
- Extended ABI (as implemented by the Sun compiler) says that
- complex floats are passed in registers up to 16 bytes. Pass
- all complex integers in registers up to 16 bytes. More generally,
- enforce the 2-word cap for passing arguments in registers.
-
- Vector ABI (as implemented by the Sun VIS SDK) says that vector
- integers are passed like floats of the same size, that is in
- registers (up to 16 bytes). Pass all vector floats like structure
- and unions. */
- return ((type
- && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
- && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
- /* Catch CTImode and TCmode. */
- || GET_MODE_SIZE (mode) > 16);
-}
-
/* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
- Update the data in CUM to advance over an argument
- of mode MODE and data type TYPE.
- TYPE is null for libcalls where that information may not be available. */
+ Update the data in CUM to advance over argument ARG. */
static void
-sparc_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
- const_tree type, bool named)
+sparc_function_arg_advance (cumulative_args_t cum_v,
+ const function_arg_info &arg)
{
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
+ tree type = arg.type;
+ machine_mode mode = arg.mode;
int regno, padding;
/* We pass false for incoming here, it doesn't matter. */
- function_arg_slotno (cum, mode, type, named, false, ®no, &padding);
+ function_arg_slotno (cum, mode, type, arg.named, false, ®no, &padding);
/* If argument requires leading padding, add it. */
cum->words += padding;
if (TARGET_ARCH32)
- cum->words += (mode == BLKmode
- ? CEIL_NWORDS (int_size_in_bytes (type))
- : CEIL_NWORDS (GET_MODE_SIZE (mode)));
+ cum->words += CEIL_NWORDS (GET_MODE_SIZE (mode));
else
{
- if (type && AGGREGATE_TYPE_P (type))
+ /* For types that can have BLKmode, get the size from the type. */
+ if (type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
{
- int size = int_size_in_bytes (type);
+ const int size = int_size_in_bytes (type);
- if (size <= 8)
- ++cum->words;
- else if (size <= 16)
- cum->words += 2;
- else /* passed by reference */
- ++cum->words;
+ /* See comment in function_arg_record_value for empty structures. */
+ if (size <= 0)
+ cum->words++;
+ else
+ cum->words += CEIL_NWORDS (size);
}
else
- cum->words += (mode == BLKmode
- ? CEIL_NWORDS (int_size_in_bytes (type))
- : CEIL_NWORDS (GET_MODE_SIZE (mode)));
+ cum->words += CEIL_NWORDS (GET_MODE_SIZE (mode));
}
}
sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
{
if (TARGET_ARCH32)
- /* Original SPARC 32-bit ABI says that structures and unions,
- and quad-precision floats are returned in memory. All other
- base types are returned in registers.
+ /* Original SPARC 32-bit ABI says that structures and unions, and
+ quad-precision floats are returned in memory. But note that the
+ first part is implemented through -fpcc-struct-return being the
+ default, so here we only implement -freg-struct-return instead.
+ All other base types are returned in registers.
Extended ABI (as implemented by the Sun compiler) says that
all complex floats are returned in registers (8 FP registers
sparc_struct_value_rtx (tree fndecl, int incoming)
{
if (TARGET_ARCH64)
- return 0;
+ return NULL_RTX;
else
{
rtx mem;
except that up to 32 bytes may be returned in registers. */
static rtx
-sparc_function_value_1 (const_tree type, machine_mode mode,
- bool outgoing)
+sparc_function_value_1 (const_tree type, machine_mode mode, bool outgoing)
{
/* Beware that the two values are swapped here wrt function_arg. */
- int regbase = (outgoing
- ? SPARC_INCOMING_INT_ARG_FIRST
- : SPARC_OUTGOING_INT_ARG_FIRST);
+ const int regbase
+ = outgoing ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST;
enum mode_class mclass = GET_MODE_CLASS (mode);
int regno;
- /* Vector types deserve special treatment because they are polymorphic wrt
- their mode, depending upon whether VIS instructions are enabled. */
- if (type && TREE_CODE (type) == VECTOR_TYPE)
- {
- HOST_WIDE_INT size = int_size_in_bytes (type);
- gcc_assert ((TARGET_ARCH32 && size <= 8)
- || (TARGET_ARCH64 && size <= 32));
-
- if (mode == BLKmode)
- return function_arg_vector_value (size, SPARC_FP_ARG_FIRST);
-
- mclass = MODE_FLOAT;
- }
+ /* Integer vectors are handled like floats as per the Sun VIS SDK.
+ Note that integer vectors larger than 16 bytes have BLKmode so
+ they need to be handled like floating-point vectors below. */
+ if (type && VECTOR_INTEGER_TYPE_P (type) && mode != BLKmode)
+ mclass = MODE_FLOAT;
if (TARGET_ARCH64 && type)
{
/* Structures up to 32 bytes in size are returned in registers. */
if (TREE_CODE (type) == RECORD_TYPE)
{
- HOST_WIDE_INT size = int_size_in_bytes (type);
+ const int size = int_size_in_bytes (type);
gcc_assert (size <= 32);
- return function_arg_record_value (type, mode, 0, 1, regbase);
+ return function_arg_record_value (type, mode, 0, true, regbase);
}
/* Unions up to 32 bytes in size are returned in integer registers. */
else if (TREE_CODE (type) == UNION_TYPE)
{
- HOST_WIDE_INT size = int_size_in_bytes (type);
+ const int size = int_size_in_bytes (type);
gcc_assert (size <= 32);
return function_arg_union_value (size, mode, 0, regbase);
}
+ /* Vectors up to 32 bytes are returned in FP registers. */
+ else if (VECTOR_TYPE_P (type) && mode == BLKmode)
+ {
+ const int size = int_size_in_bytes (type);
+ gcc_assert (size <= 32);
+
+ return function_arg_vector_value (size, 0, true, SPARC_FP_ARG_FIRST);
+ }
+
/* Objects that require it are returned in FP registers. */
else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
;
{
/* All other aggregate types are passed in an integer register
in a mode corresponding to the size of the type. */
- HOST_WIDE_INT size = int_size_in_bytes (type);
+ const int size = int_size_in_bytes (type);
gcc_assert (size <= 32);
mode = int_mode_for_size (size * BITS_PER_UNIT, 0).else_blk ();
bool indirect;
tree ptrtype = build_pointer_type (type);
- if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
+ if (pass_va_arg_by_reference (type))
{
indirect = true;
size = rsize = UNITS_PER_WORD;
int ignore ATTRIBUTE_UNUSED)
{
tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
- enum sparc_builtins code = (enum sparc_builtins) DECL_FUNCTION_CODE (fndecl);
+ enum sparc_builtins code
+ = (enum sparc_builtins) DECL_MD_FUNCTION_CODE (fndecl);
enum insn_code icode = sparc_builtins_icode[code];
bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
call_expr_arg_iterator iter;
sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
tree *args, bool ignore)
{
- enum sparc_builtins code = (enum sparc_builtins) DECL_FUNCTION_CODE (fndecl);
+ enum sparc_builtins code
+ = (enum sparc_builtins) DECL_MD_FUNCTION_CODE (fndecl);
tree rtype = TREE_TYPE (TREE_TYPE (fndecl));
tree arg0, arg1, arg2;
HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
tree function)
{
+ const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
rtx this_rtx, funexp;
rtx_insn *insn;
unsigned int int_arg_first;
start_sequence ();
load_got_register (); /* clobbers %o7 */
if (!TARGET_VXWORKS_RTP)
- pic_offset_table_rtx = global_offset_table_rtx;
+ pic_offset_table_rtx = got_register_rtx;
scratch = sparc_legitimize_pic_address (funexp, scratch);
seq = get_insns ();
end_sequence ();
}
else /* TARGET_ARCH64 */
{
- switch (sparc_cmodel)
+ switch (sparc_code_model)
{
case CM_MEDLOW:
case CM_MEDMID:
/* Run just enough of rest_of_compilation to get the insns emitted.
There's not really enough bulk here to make other passes such as
- instruction scheduling worth while. Note that use_thunk calls
- assemble_start_function and assemble_end_function. */
+ instruction scheduling worth while. */
insn = get_insns ();
shorten_branches (insn);
+ assemble_start_function (thunk_fndecl, fnname);
final_start_function (insn, file, 1);
final (insn, file, 1);
final_end_function ();
+ assemble_end_function (thunk_fndecl, fnname);
reload_completed = 0;
epilogue_completed = 0;
{
return ggc_cleared_alloc<machine_function> ();
}
+\f
+/* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
+static unsigned HOST_WIDE_INT
+sparc_asan_shadow_offset (void)
+{
+ return TARGET_ARCH64 ? (HOST_WIDE_INT_1 << 43) : (HOST_WIDE_INT_1 << 29);
+}
+\f
/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
We need to emit DTP-relative relocations. */
sparc_file_end (void)
{
/* If we need to emit the special GOT helper function, do so now. */
- if (got_helper_rtx)
+ if (got_helper_needed)
{
const char *name = XSTR (got_helper_rtx, 0);
- const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
#ifdef DWARF2_UNWIND_INFO
bool do_cfi;
#endif
#ifdef DWARF2_UNWIND_INFO
do_cfi = dwarf2out_do_cfi_asm ();
if (do_cfi)
- fprintf (asm_out_file, "\t.cfi_startproc\n");
+ output_asm_insn (".cfi_startproc", NULL);
#endif
if (flag_delayed_branch)
- fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
- reg_name, reg_name);
+ {
+ output_asm_insn ("jmp\t%%o7+8", NULL);
+ output_asm_insn (" add\t%%o7, %0, %0", &got_register_rtx);
+ }
else
- fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
- reg_name, reg_name);
+ {
+ output_asm_insn ("add\t%%o7, %0, %0", &got_register_rtx);
+ output_asm_insn ("jmp\t%%o7+8", NULL);
+ output_asm_insn (" nop", NULL);
+ }
#ifdef DWARF2_UNWIND_INFO
if (do_cfi)
- fprintf (asm_out_file, "\t.cfi_endproc\n");
+ output_asm_insn (".cfi_endproc", NULL);
#endif
}
return to == HARD_FRAME_POINTER_REGNUM || !sparc_frame_pointer_required ();
}
-/* Return the hard frame pointer directly to bypass the stack bias. */
-
-static rtx
-sparc_builtin_setjmp_frame_value (void)
-{
- return hard_frame_pointer_rtx;
-}
-
/* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
they won't be allocated. */
sparc_conditional_register_usage (void)
{
if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
- {
- fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
- call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
- }
+ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
/* If the user has passed -f{fixed,call-{used,saved}}-g5 */
/* then honor it. */
if (TARGET_ARCH32 && fixed_regs[5])
edge entry_edge;
rtx_insn *seq;
- if (!crtl->uses_pic_offset_table)
+ /* In PIC mode, we need to always initialize the PIC register if optimization
+ is enabled, because we are called from IRA and LRA may later force things
+ to the constant pool for optimization purposes. */
+ if (!flag_pic || (!crtl->uses_pic_offset_table && !optimize))
return;
start_sequence ();
load_got_register ();
if (!TARGET_VXWORKS_RTP)
- emit_move_insn (pic_offset_table_rtx, global_offset_table_rtx);
+ emit_move_insn (pic_offset_table_rtx, got_register_rtx);
seq = get_insns ();
end_sequence ();
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