Update copyright years.

[thirdparty/gcc.git] / gcc / config / sparc / ultra1_2.md

diff --git a/gcc/config/sparc/ultra1_2.md b/gcc/config/sparc/ultra1_2.md
index 49b4b96a4738289d549f9fc294df47824d37ab9a..e2feeed499b70b1c2ac659eac7be0223f39b6983 100644 (file)
--- a/gcc/config/sparc/ultra1_2.md
+++ b/gcc/config/sparc/ultra1_2.md
@@ -1,11 +1,11 @@
 ;; Scheduling description for UltraSPARC-I/II.
-;;   Copyright (C) 2002, 2004 Free Software Foundation, Inc.
+;;   Copyright (C) 2002-2024 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
 ;; GCC is free software; you can redistribute it and/or modify
 ;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
+;; the Free Software Foundation; either version 3, or (at your option)
 ;; any later version.
 ;;
 ;; GCC is distributed in the hope that it will be useful,
@@ -14,9 +14,8 @@
 ;; GNU General Public License for more details.
 ;;
 ;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
 
 ;; UltraSPARC-I and II are quad-issue processors.  Interesting features
 ;; to note:
@@ -80,7 +79,7 @@
 
 (define_insn_reservation "us1_single" 1
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "multi,savew,flushw,iflush,trap"))
+    (eq_attr "type" "multi,savew,flushw,iflush,trap,gsr"))
   "us1_single_issue")
 
 (define_insn_reservation "us1_simple_ieuN" 1
@@ -95,7 +94,7 @@
 
 (define_insn_reservation "us1_simple_ieu1" 1
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "compare"))
+    (eq_attr "type" "compare,edge,edgen,array"))
   "us1_ieu1 + us1_slot012")
 
 (define_insn_reservation "us1_ialuX" 1
@@ -256,7 +255,7 @@
   2
   (and (and
          (eq_attr "cpu" "ultrasparc")
-         (eq_attr "type" "fga"))
+         (eq_attr "type" "fga,visl,vismv"))
        (eq_attr "fptype" "single"))
   "us1_fpa + us1_fp_single + us1_slotany, nothing")
 
@@ -264,10 +263,10 @@
 
 (define_insn_reservation "us1_fga_double"
   2
-  (and (and
-         (eq_attr "cpu" "ultrasparc")
-         (eq_attr "type" "fga"))
-       (eq_attr "fptype" "double"))
+  (and (eq_attr "cpu" "ultrasparc")
+       (ior (and (eq_attr "type" "fga,visl,vismv")
+                 (eq_attr "fptype" "double"))
+            (eq_attr "type" "viscmp")))
   "us1_fpa + us1_fp_double + us1_slotany, nothing")
 
 (define_bypass 1 "us1_fga_double" "us1_fga_double")
@@ -276,7 +275,7 @@
   4
   (and (and
          (eq_attr "cpu" "ultrasparc")
-         (eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp"))
+         (eq_attr "type" "fgm_pack,fgm_mul"))
        (eq_attr "fptype" "single"))
   "us1_fpm + us1_fp_single + us1_slotany, nothing*3")
 
@@ -286,7 +285,7 @@
   4
   (and (and
          (eq_attr "cpu" "ultrasparc")
-         (eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp"))
+         (eq_attr "type" "fgm_pack,fgm_mul"))
        (eq_attr "fptype" "double"))
   "us1_fpm + us1_fp_double + us1_slotany, nothing*3")
 
@@ -295,7 +294,7 @@
 (define_insn_reservation "us1_pdist"
   4
   (and (eq_attr "cpu" "ultrasparc")
-       (eq_attr "type" "fgm_pdist"))
+       (eq_attr "type" "pdist"))
   "us1_fpm + us1_fp_double + us1_slotany, nothing*3")
 
 (define_bypass 3 "us1_pdist" "us1_fga_double,us1_fga_single")