;; GCC machine description for NEC V850
-;; Copyright (C) 1996, 1997, 1998, 1999, 2002, 2004, 2005, 2007, 2008, 2010
-;; Free Software Foundation, Inc.
+;; Copyright (C) 1996-2020 Free Software Foundation, Inc.
;; Contributed by Jeff Law (law@cygnus.com).
;; This file is part of GCC.
;;
;; One day we'll probably need to handle calls to targets more than 4M
;; away.
+;;
+
+;; Condition codes
+;;
+;; Data movement (load, store, register copy) does not modify condition
+;; codes. But there is no way to add two registers together without
+;; modifying the condition codes.
+;;
+;; So we do not expose the condition codes until after reload. The
+;; general approach is to have a define_insn_and_split for the basic
+;; operation with no condition codes in the pattern (to give the
+;; optimizers maximal freedom). The splitter adds a clobber of the
+;; condition codes after reload. There is a distinct pattern which
+;; sets the condition codes.
+;;
+;; As noted, data movement does not affect condition codes.
+;;
+;; Arithmetic generally set the codes in the expected ways, with mul
+;; instructions being a notable outlier. div instructions generally
+;; do the right thing, except when the output registers are the same
+;; when the flags do not get set. We just assume they're clobbered
+;; for div instructions to avoid MD bloat with marginal benefit
+;;
+;; The bit manipulation instructions (clr1, not1, set1) set condition
+;; codes, but not in a useful way (they're set to the prior status of
+;; the bit). So we just model those as clobbers. tst1 does set the
+;; condition codes in a useful way. We could perhaps do better with
+;; these by noting they only modify the Z flag, it doesn't seem worth
+;; the effort.
+;;
+;; Byte swaps seem to change the condition codes, but I haven't tried
+;; to describe how.
+;;
+;; I have no documentation on the rotate instructions. They likely
+;; set the condition codes, but I've left them as clobbers for now.
+
;; The size of instructions in bytes.
[(ZERO_REGNUM 0) ; constant zero
(SP_REGNUM 3) ; Stack Pointer
(GP_REGNUM 4) ; GP Pointer
+ (RV_REGNUM 10) ; Return value register
(EP_REGNUM 30) ; EP pointer
(LP_REGNUM 31) ; Return address register
(CC_REGNUM 32) ; Condition code pseudo register
]
)
+(define_c_enum "unspec" [
+ UNSPEC_LOOP
+ UNSPEC_RCP
+ UNSPEC_RSQRT
+])
+
(define_attr "length" ""
(const_int 4))
(define_attr "type" "load,store,bit1,mult,macc,div,fpu,single,other"
(const_string "other"))
-(define_attr "cpu" "none,v850,v850e,v850e1,v850e2,v850e2v3"
+(define_attr "cpu" "none,v850,v850e,v850e1,v850e2,v850e2v3,v850e3v5"
(cond [(match_test "TARGET_V850")
(const_string "v850")
(match_test "TARGET_V850E")
(const_string "v850e1")
(match_test "TARGET_V850E2")
(const_string "v850e2")
- (match_test "TARGET_V850E2")
- (const_string "v850e2v3")]
+ (match_test "TARGET_V850E2V3")
+ (const_string "v850e2v3")
+ (match_test "TARGET_V850E3V5")
+ (const_string "v850e3v5")]
(const_string "none")))
-;; Condition code settings.
-;; none - insn does not affect cc
-;; none_0hit - insn does not affect cc but it does modify operand 0
-;; This attribute is used to keep track of when operand 0 changes.
-;; See the description of NOTICE_UPDATE_CC for more info.
-;; set_znv - sets z,n,v to usable values; c is unknown.
-;; set_zn - sets z,n to usable values; v,c is unknown.
-;; compare - compare instruction
-;; clobber - value of cc is unknown
-(define_attr "cc" "none,none_0hit,set_z,set_zn,set_znv,compare,clobber"
- (const_string "clobber"))
\f
;; Function units for the V850. As best as I can tell, there's
;; a traditional memory load/use stall as well as a stall if
;; ----------------------------------------------------------------------
;; MOVE INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "sign23byte_load"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI
- (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand 2 "disp23_operand" "W")))))]
- "TARGET_V850E2V3"
- "ld.b %2[%1],%0"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
-
-(define_insn "unsign23byte_load"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI
- (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand 2 "disp23_operand" "W")))))]
- "TARGET_V850E2V3"
- "ld.bu %2[%1],%0"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
-
-(define_insn "sign23hword_load"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI
- (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand 2 "disp23_operand" "W")))))]
- "TARGET_V850E2V3"
- "ld.h %2[%1],%0"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
+;; movdi
-(define_insn "unsign23hword_load"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI
- (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand 2 "disp23_operand" "W")))))]
- "TARGET_V850E2V3"
- "ld.hu %2[%1],%0"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
-
-(define_insn "23word_load"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand 2 "disp23_operand" "W"))))]
- "TARGET_V850E2V3"
- "ld.w %2[%1],%0"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
+(define_expand "movdi"
+ [(set (match_operand:DI 0 "general_operand")
+ (match_operand:DI 1 "general_operand"))]
+ "TARGET_V850E3V5_UP"
+ {
+ /* One of the ops has to be in a register or 0. */
+ if (!register_operand (operand0, DImode)
+ && !register_operand (operand1, DImode))
+ operands[1] = copy_to_mode_reg (DImode, operand1);
-(define_insn "23byte_store"
- [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand 1 "disp23_operand" "W")))
- (match_operand:QI 2 "register_operand" "r"))]
- "TARGET_V850E2V3"
- "st.b %2,%1[%0]"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
+ if (register_operand (operand0, DImode)
+ && (CONST_INT_P (operands[1]) || CONST_DOUBLE_P (operands[1])))
+ {
+ int i;
-(define_insn "23hword_store"
- [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand 1 "disp23_operand" "W")))
- (match_operand:HI 2 "register_operand" "r"))]
- "TARGET_V850E2V3"
- "st.h %2,%1[%0]"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
+ for (i = 0; i < UNITS_PER_WORD * 2; i += UNITS_PER_WORD)
+ emit_move_insn (simplify_gen_subreg (SImode, operands[0], DImode, i),
+ simplify_gen_subreg (SImode, operands[1], DImode, i));
+ DONE;
+ }
+ }
+)
-(define_insn "23word_store"
- [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand 1 "disp23_operand" "W")))
- (match_operand:SI 2 "register_operand" "r"))]
- "TARGET_V850E2V3"
- "st.w %2,%1[%0]"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
+(define_insn "*movdi_internal"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,e!r,m")
+ (match_operand:DI 1 "nonimmediate_operand" "r,m,e!r"))]
+ "TARGET_V850E3V5_UP
+ || (register_operand (operands[0], DImode) && register_operand (operands[1], DImode))"
+ { return v850_gen_movdi (operands); }
+ [(set_attr "length" "4,12,12")
+ (set_attr "type" "other,load,store")])
;; movqi
})
(define_insn "*movqi_internal"
- [(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,Q,r,m,m")
(match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
"register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode)"
return output_move_single (operands);
}
[(set_attr "length" "2,4,2,2,4,4,4")
- (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,load,other,load,store,store")])
;; movhi
})
(define_insn "*movhi_internal"
- [(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m")
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,Q,r,m,m")
(match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
"register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode)"
return output_move_single (operands);
}
[(set_attr "length" "2,4,2,2,4,4,4")
- (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,load,other,load,store,store")])
;; movsi and helpers
""
"movhi hi(%1),%.,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "other")])
(define_insn "*movsi_lo"
""
"movea lo(%2),%1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "other")])
(define_expand "movsi"
must be done with HIGH & LO_SUM patterns. */
if (CONSTANT_P (operands[1])
&& GET_CODE (operands[1]) != HIGH
- && ! (TARGET_V850E || TARGET_V850E2_ALL)
+ && ! (TARGET_V850E_UP)
&& !special_symbolref_operand (operands[1], VOIDmode)
&& !(GET_CODE (operands[1]) == CONST_INT
&& (CONST_OK_FOR_J (INTVAL (operands[1]))
else
temp = gen_reg_rtx (SImode);
- emit_insn (gen_rtx_SET (SImode, temp,
- gen_rtx_HIGH (SImode, operand1)));
- emit_insn (gen_rtx_SET (SImode, operand0,
+ emit_insn (gen_rtx_SET (temp, gen_rtx_HIGH (SImode, operand1)));
+ emit_insn (gen_rtx_SET (operand0,
gen_rtx_LO_SUM (SImode, temp, operand1)));
DONE;
}
;; upper part with hi, and then put the lower part in the load/store insn.
(define_insn "*movsi_internal_v850e"
- [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m,r")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,Q,r,r,m,m,r")
(match_operand:SI 1 "general_operand" "Jr,K,L,Q,Ir,m,R,r,I,i"))]
- "(TARGET_V850E || TARGET_V850E2_ALL)
+ "(TARGET_V850E_UP)
&& (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))"
{
return output_move_single (operands);
}
[(set_attr "length" "2,4,4,2,2,4,4,4,4,6")
- (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,other,load,other,load,other,store,store,other")])
(define_insn "*movsi_internal"
- [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,Q,r,r,m,m")
(match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))]
"register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode)"
return output_move_single (operands);
}
[(set_attr "length" "2,4,4,2,2,4,4,4,4")
- (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,other,load,other,load,store,store,other")])
(define_insn "*movsf_internal"
- [(set (match_operand:SF 0 "general_operand" "=r,r,r,r,r,Q,r,m,m,r")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,r,Q,r,m,m,r")
(match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))]
"register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode)"
return output_move_single (operands);
}
[(set_attr "length" "2,4,4,8,2,2,4,4,4,8")
- (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,other,other,load,other,load,store,store,other")])
;; ----------------------------------------------------------------------
;; ----------------------------------------------------------------------
(define_insn "*v850_tst1"
- [(set (cc0)
+ [(set (reg:CCZ CC_REGNUM)
(compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
(const_int 1)
(match_operand:QI 1 "const_int_operand" "n"))
(const_int 0)))]
- ""
+ "reload_completed"
"tst1 %1,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
;; This replaces ld.b;sar;andi with tst1;setf nz.
+;; Should there be variants for HI or SI modes?
-(define_split
+(define_insn_and_split ""
[(set (match_operand:SI 0 "register_operand" "")
(compare (zero_extract:SI (match_operand:QI 1 "memory_operand" "")
(const_int 1)
(match_operand 2 "const_int_operand" ""))
(const_int 0)))]
""
- [(set (cc0) (compare (zero_extract:SI (match_dup 1)
- (const_int 1)
- (match_dup 2))
- (const_int 0)))
- (set (match_dup 0) (ne:SI (cc0) (const_int 0)))])
+ "#"
+ "reload_completed"
+ [(set (reg:CCZ CC_REGNUM) (compare (zero_extract:SI (match_dup 1)
+ (const_int 1)
+ (match_dup 2))
+ (const_int 0)))
+ (set (match_dup 0) (ne:SI (reg:CCZ CC_REGNUM) (const_int 0)))])
(define_expand "cbranchsi4"
- [(set (cc0)
- (compare (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "reg_or_int5_operand" "")))
- (set (pc)
+ [(set (pc)
(if_then_else
- (match_operator 0 "ordered_comparison_operator" [(cc0)
- (const_int 0)])
+ (match_operator 0 "comparison_operator"
+ [(match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "reg_or_int5_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
"")
-(define_expand "cstoresi4"
- [(set (cc0)
- (compare (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 3 "reg_or_int5_operand" "")))
- (set (match_operand:SI 0 "register_operand")
- (match_operator:SI 1 "ordered_comparison_operator" [(cc0)
- (const_int 0)]))]
- "")
-
-(define_expand "cmpsi"
- [(set (cc0)
- (compare (match_operand:SI 0 "register_operand" "r,r")
- (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
- ""
- {
- v850_compare_op0 = operands[0];
- v850_compare_op1 = operands[1];
- DONE;
- })
-
(define_insn "cmpsi_insn"
- [(set (cc0)
+ [(set (reg:CC CC_REGNUM)
(compare (match_operand:SI 0 "register_operand" "r,r")
(match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
- ""
- "@
- cmp %1,%0
- cmp %1,%0"
- [(set_attr "length" "2,2")
- (set_attr "cc" "compare")])
+ "reload_completed"
+ "cmp %1,%0"
+ [(set_attr "length" "2,2")])
-(define_expand "cmpsf"
- [(set (reg:CC CC_REGNUM)
- (compare (match_operand:SF 0 "register_operand" "r")
- (match_operand:SF 1 "register_operand" "r")))]
- "TARGET_V850E2V3"
- {
- v850_compare_op0 = operands[0];
- v850_compare_op1 = operands[1];
- DONE;
- })
+(define_insn_and_split "cbranchsf4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(match_operand:SF 1 "register_operand" "r")
+ (match_operand:SF 2 "register_operand" "r")])
+ (label_ref (match_operand 3 ""))
+ (pc)))]
+ "TARGET_USE_FPU"
+ "#"
+ "reload_completed"
+ [(set (match_dup 4) (match_dup 5))
+ (set (pc)
+ (if_then_else (match_dup 6)
+ (label_ref (match_dup 3))
+ (pc)))]
+ "{
+ /* This will generate the comparison insn at the start of
+ the sequence and get us the right mode to use for our
+ condition code registers. */
+ enum machine_mode mode
+ = v850_gen_float_compare (GET_CODE (operands[0]),
+ GET_MODE (operands[1]),
+ operands[1], operands[2]);
+ /* We want operands referring to CC_REGNUM and FCC_REGNUM
+ in mode MODE. */
+ operands[4] = gen_rtx_REG (mode, CC_REGNUM);
+ operands[5] = gen_rtx_REG (mode, FCC_REGNUM);
+ if (mode == CC_FPU_NEmode)
+ operands[6] = gen_rtx_NE (mode, operands[4], const0_rtx);
+ else
+ operands[6] = gen_rtx_EQ (mode, operands[4], const0_rtx);
+}")
+
+(define_insn "cstoresf4"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operator:SI 1 "ordered_comparison_operator"
+ [(match_operand:SF 2 "register_operand" "r")
+ (match_operand:SF 3 "register_operand" "r")]))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_USE_FPU"
+{
+ if (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
+ return "cmpf.s %c1, %z2, %z3 ; trfsr ; setf nz, %0";
+ if (GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE)
+ return "cmpf.s %c1, %z2, %z3 ; trfsr ; setf z, %0";
+ if (GET_CODE (operands[1]) == EQ)
+ return "cmpf.s eq, %z2, %z3 ; trfsr ; setf z, %0";
+ if (GET_CODE (operands[1]) == NE)
+ return "cmpf.s neq, %z2, %z3 ; trfsr ; setf nz, %0";
+ gcc_unreachable ();
+}
+ [(set_attr "length" "12")
+ (set_attr "type" "fpu")])
-(define_expand "cmpdf"
- [(set (reg:CC CC_REGNUM)
- (compare (match_operand:DF 0 "even_reg_operand" "r")
- (match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
- {
- v850_compare_op0 = operands[0];
- v850_compare_op1 = operands[1];
- DONE;
- })
+(define_insn_and_split "cbranchdf4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(match_operand:DF 1 "even_reg_operand" "r")
+ (match_operand:DF 2 "even_reg_operand" "r")])
+ (label_ref (match_operand 3 ""))
+ (pc)))]
+ "TARGET_USE_FPU"
+ "#"
+ "reload_completed"
+;; How to get the mode here?
+ [(set (match_dup 4) (match_dup 5))
+ (set (pc)
+ (if_then_else (match_dup 6)
+ (label_ref (match_dup 3))
+ (pc)))]
+ "{
+ /* This will generate the comparison insn at the start of
+ the sequence and get us the right mode to use for our
+ condition code registers. */
+ enum machine_mode mode
+ = v850_gen_float_compare (GET_CODE (operands[0]),
+ GET_MODE (operands[1]),
+ operands[1], operands[2]);
+ PUT_MODE (operands[0], mode);
+ /* We want operands referring to CC_REGNUM and FCC_REGNUM
+ in mode MODE. */
+ operands[4] = gen_rtx_REG (mode, CC_REGNUM);
+ operands[5] = gen_rtx_REG (mode, FCC_REGNUM);
+ if (mode == CC_FPU_NEmode)
+ operands[6] = gen_rtx_NE (mode, operands[4], const0_rtx);
+ else
+ operands[6] = gen_rtx_EQ (mode, operands[4], const0_rtx);
+}")
+
+(define_insn "cstoredf4"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operator:SI 1 "ordered_comparison_operator"
+ [(match_operand:DF 2 "even_reg_operand" "r")
+ (match_operand:DF 3 "even_reg_operand" "r")]))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_USE_FPU"
+{
+ if (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
+ return "cmpf.d %c1, %z2, %z3 ; trfsr ; setf nz, %0";
+ if (GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE)
+ return "cmpf.d %c1, %z2, %z3 ; trfsr ; setf z, %0";
+ if (GET_CODE (operands[1]) == EQ)
+ return "cmpf.d eq, %z2, %z3 ; trfsr ; setf z ,%0";
+ if (GET_CODE (operands[1]) == NE)
+ return "cmpf.d neq, %z2, %z3 ; trfsr ; setf nz, %0";
+ gcc_unreachable ();
+}
+ [(set_attr "length" "12")
+ (set_attr "type" "fpu")])
;; ----------------------------------------------------------------------
;; ADD INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "addsi3"
+(define_insn_and_split "addsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r")
+ (match_operand:SI 2 "nonmemory_operand" "rJ,K,U")))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])])
+
+(define_insn "addsi3_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(plus:SI (match_operand:SI 1 "register_operand" "%0,r,r")
(match_operand:SI 2 "nonmemory_operand" "rJ,K,U")))
(clobber (reg:CC CC_REGNUM))]
-
""
"@
add %2,%0
addi %2,%1,%0
addi %O2(%P2),%1,%0"
- [(set_attr "length" "2,4,4")
- (set_attr "cc" "set_zn,set_zn,set_zn")])
+ [(set_attr "length" "2,4,4")])
+
+(define_insn "addsi3_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r")
+ (match_operand:SI 2 "nonmemory_operand" "rJ,K,U"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (plus:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ add %2,%0
+ addi %2,%1,%0
+ addi %O2(%P2),%1,%0"
+ [(set_attr "length" "2,4,4")])
;; ----------------------------------------------------------------------
;; SUBTRACT INSTRUCTIONS
;; ----------------------------------------------------------------------
+(define_insn_and_split "subsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,r")
+ (match_operand:SI 2 "register_operand" "r,0")))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])])
-(define_insn "subsi3"
+(define_insn "subsi3_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(minus:SI (match_operand:SI 1 "register_operand" "0,r")
(match_operand:SI 2 "register_operand" "r,0")))
"@
sub %2,%0
subr %1,%0"
- [(set_attr "length" "2,2")
- (set_attr "cc" "set_zn,set_zn")])
+ [(set_attr "length" "2,2")])
+
+(define_insn "*subsi3_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (minus:SI (match_operand:SI 1 "register_operand" "0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r")
+ (minus:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ sub %2,%0
+ subr %1,%0"
+ [(set_attr "length" "2,2")])
+
+(define_insn_and_split "negsi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (neg:SI (match_operand:SI 1 "register_operand" "0")))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (neg:SI (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])])
-(define_insn "negsi2"
+(define_insn "negsi2_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "register_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
""
"subr %.,%0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "2")])
+
+(define_insn "*negsi2_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (neg:SI (match_operand:SI 1 "register_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (neg:SI (match_dup 1)))]
+ "reload_completed"
+ "subr %.,%0"
+ [(set_attr "length" "2")])
;; ----------------------------------------------------------------------
;; MULTIPLY INSTRUCTIONS
""
"mulh %2,%0"
[(set_attr "length" "2")
- (set_attr "cc" "none_0hit")
(set_attr "type" "mult")])
(define_insn "mulhisi3_internal2"
mulh %2,%0
mulhi %2,%1,%0"
[(set_attr "length" "2,4")
- (set_attr "cc" "none_0hit,none_0hit")
(set_attr "type" "mult")])
;; ??? The scheduling info is probably wrong.
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "reg_or_int9_operand" "rO")))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ "(TARGET_V850E_UP)"
"mul %2,%1,%."
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "mult")])
;; ----------------------------------------------------------------------
(mod:SI (match_dup 1)
(match_dup 2)))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_V850E || TARGET_V850E2_ALL"
+ "TARGET_V850E_UP"
{
- if (TARGET_V850E2_ALL)
+ if (TARGET_V850E2_UP)
return "divq %2,%0,%3";
else
return "div %2,%0,%3";
}
[(set_attr "length" "4")
- (set_attr "cc" "clobber")
(set_attr "type" "div")])
(define_insn "udivmodsi4"
(umod:SI (match_dup 1)
(match_dup 2)))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_V850E || TARGET_V850E2_ALL"
+ "TARGET_V850E_UP"
{
- if (TARGET_V850E2_ALL)
+ if (TARGET_V850E2_UP)
return "divqu %2,%0,%3";
else
return "divu %2,%0,%3";
}
[(set_attr "length" "4")
- (set_attr "cc" "clobber")
(set_attr "type" "div")])
;; ??? There is a 2 byte instruction for generating only the quotient.
(mod:HI (match_dup 1)
(match_dup 2)))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_V850E || TARGET_V850E2_ALL"
- "divh %2,%0,%3"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")
+ "TARGET_V850E_UP"
+ "sxh %0\\n\\tdivh %2,%0,%3"
+ [(set_attr "length" "6")
(set_attr "type" "div")])
-;; Half-words are sign-extended by default, so we must zero extend to a word
-;; here before doing the divide.
+;; The half word needs to be zero/sign extended to 32 bits before doing
+;; the division/modulo operation.
(define_insn "udivmodhi4"
[(set (match_operand:HI 0 "register_operand" "=r")
(umod:HI (match_dup 1)
(match_dup 2)))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_V850E || TARGET_V850E2_ALL"
- "zxh %0 ; divhu %2,%0,%3"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")
+ "TARGET_V850E_UP"
+ "zxh %0\\n\\ndivhu %2,%0,%3"
+ [(set_attr "length" "6")
(set_attr "type" "div")])
\f
;; ----------------------------------------------------------------------
return "";
}
[(set_attr "length" "4")
- (set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(define_insn "*v850_clr1_2"
return "";
}
[(set_attr "length" "4")
- (set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(define_insn "*v850_clr1_3"
return "";
}
[(set_attr "length" "4")
- (set_attr "cc" "clobber")
(set_attr "type" "bit1")])
-(define_insn "andsi3"
+(define_insn_and_split "andsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])])
+
+(define_insn "andsi3_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
(match_operand:SI 2 "nonmemory_operand" "r,I,M")))
(clobber (reg:CC CC_REGNUM))]
- ""
+ "reload_completed"
+ "@
+ and %2,%0
+ and %.,%0
+ andi %2,%1,%0"
+ [(set_attr "length" "2,2,4")])
+
+(define_insn "andsi3_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,I,M"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (and:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
"@
and %2,%0
and %.,%0
andi %2,%1,%0"
- [(set_attr "length" "2,2,4")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "2,2,4")])
;; ----------------------------------------------------------------------
;; OR INSTRUCTIONS
""
"set1 %M1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(define_insn "*v850_set1_2"
return "";
}
[(set_attr "length" "4")
- (set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(define_insn "*v850_set1_3"
return "";
}
[(set_attr "length" "4")
- (set_attr "cc" "clobber")
(set_attr "type" "bit1")])
-(define_insn "iorsi3"
+(define_insn_and_split "iorsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])])
+
+(define_insn "iorsi3_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
(match_operand:SI 2 "nonmemory_operand" "r,I,M")))
or %2,%0
or %.,%0
ori %2,%1,%0"
- [(set_attr "length" "2,2,4")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "2,2,4")])
+
+(define_insn "*iorsi3_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,I,M"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (ior:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ or %2,%0
+ or %.,%0
+ ori %2,%1,%0"
+ [(set_attr "length" "2,2,4")])
;; ----------------------------------------------------------------------
;; XOR INSTRUCTIONS
""
"not1 %M1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(define_insn "*v850_not1_2"
return "";
}
[(set_attr "length" "4")
- (set_attr "cc" "clobber")
(set_attr "type" "bit1")])
(define_insn "*v850_not1_3"
return "";
}
[(set_attr "length" "4")
- (set_attr "cc" "clobber")
(set_attr "type" "bit1")])
-(define_insn "xorsi3"
+(define_insn_and_split "xorsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])])
+
+(define_insn "xorsi3_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
(match_operand:SI 2 "nonmemory_operand" "r,I,M")))
xor %2,%0
xor %.,%0
xori %2,%1,%0"
- [(set_attr "length" "2,2,4")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "2,2,4")])
+
+(define_insn "*xorsi3_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+ (match_operand:SI 2 "nonmemory_operand" "r,I,M"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (xor:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ xor %2,%0
+ xor %.,%0
+ xori %2,%1,%0"
+ [(set_attr "length" "2,2,4")])
+
\f
;; ----------------------------------------------------------------------
;; NOT INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "one_cmplsi2"
+(define_insn_and_split "one_cmplsi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (not:SI (match_operand:SI 1 "register_operand" "r")))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (not:SI (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])])
+
+
+(define_insn "one_cmplsi2_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operand:SI 1 "register_operand" "r")))
(clobber (reg:CC CC_REGNUM))]
""
"not %1,%0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "2")])
+
+(define_insn "*one_cmplsi2_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (not:SI (match_operand:SI 1 "register_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (not:SI (match_dup 1)))]
+ "reload_completed"
+ "not %1,%0"
+ [(set_attr "length" "2")])
;; -----------------------------------------------------------------
;; BIT FIELDS
;; optimize_bitfield_compare in fold-const usually converts single
;; bit extracts into an AND with a mask.
+(define_insn "insv"
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
+ (match_operand:SI 1 "immediate_operand" "n")
+ (match_operand:SI 2 "immediate_operand" "n"))
+ (match_operand:SI 3 "register_operand" "r"))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_V850E3V5_UP"
+ "bins %3, %2, %1, %0"
+ [(set_attr "length" "4")])
+
;; -----------------------------------------------------------------
;; Scc INSTRUCTIONS
;; -----------------------------------------------------------------
-(define_insn "*setcc"
+(define_insn_and_split "*cbranchsi4_insn"
+ [(set (pc)
+ (if_then_else (match_operator 0 "comparison_operator"
+ [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "reg_or_int5_operand" "rJ")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+ "#"
+ "reload_completed"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_dup 1) (match_dup 2)))
+ (set (pc)
+ (if_then_else (match_op_dup 0
+ [(reg:CC CC_REGNUM) (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))]
+ "")
+
+
+(define_insn_and_split "cstoresi4"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operator:SI 1 "comparison_operator"
- [(cc0) (const_int 0)]))]
+ [(match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "reg_or_int5_operand" "rJ")]))]
""
-{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
- && (GET_CODE (operands[1]) == GT
- || GET_CODE (operands[1]) == GE
- || GET_CODE (operands[1]) == LE
- || GET_CODE (operands[1]) == LT))
- return 0;
-
- return "setf %c1,%0";
-}
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
+ "#"
+ "reload_completed"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_dup 2) (match_dup 3)))
+ (set (match_dup 0) (match_op_dup 1
+ [(reg:CC CC_REGNUM) (const_int 0)]))]
+ "")
-(define_insn "setf_insn"
+(define_insn "*setcc_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
- (match_operator:SI 1 "comparison_operator"
- [(reg:CC CC_REGNUM) (const_int 0)]))]
- ""
- "setf %b1,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
+ (match_operator:SI 1 "comparison_operator"
+ [(reg:CC CC_REGNUM) (const_int 0)]))]
+ "reload_completed"
+ "setf %c1,%0"
+ [(set_attr "length" "4")])
(define_insn "set_z_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand 1 "v850_float_z_comparison_operator" ""))]
- "TARGET_V850E2V3"
+ "TARGET_V850E2V3_UP"
"setf z,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
+ [(set_attr "length" "4")])
(define_insn "set_nz_insn"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand 1 "v850_float_nz_comparison_operator" ""))]
- "TARGET_V850E2V3"
+ "TARGET_V850E2V3_UP"
"setf nz,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
+ [(set_attr "length" "4")])
;; ----------------------------------------------------------------------
;; CONDITIONAL MOVE INSTRUCTIONS
(match_operand 1 "comparison_operator")
(match_operand:SI 2 "reg_or_const_operand" "rJ")
(match_operand:SI 3 "reg_or_const_operand" "rI")))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ "(TARGET_V850E_UP)"
{
+ /* Make sure that we have an integer comparison... */
+ if (GET_MODE (XEXP (operands[1], 0)) != CCmode
+ && GET_MODE (XEXP (operands[1], 0)) != SImode)
+ FAIL;
+
if ((GET_CODE (operands[2]) == CONST_INT
&& GET_CODE (operands[3]) == CONST_INT))
{
}
})
-;; ??? Clobbering the condition codes is overkill.
-
-;; ??? We sometimes emit an unnecessary compare instruction because the
-;; condition codes may have already been set by an earlier instruction,
-;; but we have no code here to avoid the compare if it is unnecessary.
-
(define_insn "movsicc_normal_cc"
[(set (match_operand:SI 0 "register_operand" "=r")
(if_then_else:SI
[(reg:CC CC_REGNUM) (const_int 0)])
(match_operand:SI 2 "reg_or_int5_operand" "rJ")
(match_operand:SI 3 "reg_or_0_operand" "rI")))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ "reload_completed && (TARGET_V850E_UP)"
"cmov %c1,%2,%z3,%0";
- [(set_attr "length" "6")
- (set_attr "cc" "compare")])
+ [(set_attr "length" "6")])
(define_insn "movsicc_reversed_cc"
[(set (match_operand:SI 0 "register_operand" "=r")
[(reg:CC CC_REGNUM) (const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "rI")
(match_operand:SI 3 "reg_or_int5_operand" "rJ")))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ "reload_completed && (TARGET_V850E_UP)"
"cmov %C1,%3,%z2,%0"
- [(set_attr "length" "6")
- (set_attr "cc" "compare")])
+ [(set_attr "length" "6")])
-(define_insn "*movsicc_normal"
+(define_insn_and_split "*movsicc_normal"
[(set (match_operand:SI 0 "register_operand" "=r")
(if_then_else:SI
(match_operator 1 "comparison_operator"
(match_operand:SI 5 "reg_or_int5_operand" "rJ")])
(match_operand:SI 2 "reg_or_int5_operand" "rJ")
(match_operand:SI 3 "reg_or_0_operand" "rI")))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
- "cmp %5,%4 ; cmov %c1,%2,%z3,%0"
- [(set_attr "length" "6")
- (set_attr "cc" "clobber")])
+ "(TARGET_V850E_UP)"
+ "#"
+ "reload_completed"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_dup 4) (match_dup 5)))
+ (set (match_dup 0)
+ (if_then_else:SI (match_op_dup 1
+ [(reg:CC CC_REGNUM) (const_int 0)])
+ (match_dup 2) (match_dup 3)))])
+
-(define_insn "*movsicc_reversed"
+(define_insn_and_split "*movsicc_reversed"
[(set (match_operand:SI 0 "register_operand" "=r")
(if_then_else:SI
(match_operator 1 "comparison_operator"
[(match_operand:SI 4 "register_operand" "r")
(match_operand:SI 5 "reg_or_int5_operand" "rJ")])
- (match_operand:SI 2 "reg_or_0_operand" "rI")
- (match_operand:SI 3 "reg_or_int5_operand" "rJ")))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
- "cmp %5,%4 ; cmov %C1,%3,%z2,%0"
- [(set_attr "length" "6")
- (set_attr "cc" "clobber")])
+ (match_operand:SI 2 "reg_or_int5_operand" "rI")
+ (match_operand:SI 3 "reg_or_0_operand" "rJ")))]
+ "(TARGET_V850E_UP)"
+ "#"
+ "reload_completed"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_dup 4) (match_dup 5)))
+ (set (match_dup 0)
+ (if_then_else:SI (match_op_dup 1
+ [(reg:CC CC_REGNUM) (const_int 0)])
+ (match_dup 2) (match_dup 3)))])
+;; We could expose the setting of the condition codes here.
(define_insn "*movsicc_tst1"
[(set (match_operand:SI 0 "register_operand" "=r")
(if_then_else:SI
(match_operand 3 "const_int_operand" "n"))
(const_int 0)])
(match_operand:SI 4 "reg_or_int5_operand" "rJ")
- (match_operand:SI 5 "reg_or_0_operand" "rI")))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ (match_operand:SI 5 "reg_or_0_operand" "rI")))
+ (clobber (reg:CC CC_REGNUM))]
+ "(TARGET_V850E_UP)"
"tst1 %3,%2 ; cmov %c1,%4,%z5,%0"
- [(set_attr "length" "8")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "8")])
+;; We could expose the setting of the condition codes here.
(define_insn "*movsicc_tst1_reversed"
[(set (match_operand:SI 0 "register_operand" "=r")
(if_then_else:SI
(match_operand 3 "const_int_operand" "n"))
(const_int 0)])
(match_operand:SI 4 "reg_or_0_operand" "rI")
- (match_operand:SI 5 "reg_or_int5_operand" "rJ")))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ (match_operand:SI 5 "reg_or_int5_operand" "rJ")))
+ (clobber (reg:CC CC_REGNUM))]
+ "(TARGET_V850E_UP)"
"tst1 %3,%2 ; cmov %C1,%5,%z4,%0"
- [(set_attr "length" "8")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "8")])
;; Matching for sasf requires combining 4 instructions, so we provide a
;; dummy pattern to match the first 3, which will always be turned into the
;; second pattern by subsequent combining. As above, we must include the
;; comparison to avoid input reloads in an insn using cc0.
+;; We could expose the setting of the condition codes here.
+;; However, I haven't seen this pattern used, so I'm not going
+;; to bother.
(define_insn "*sasf"
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI
(ashift:SI (match_operand:SI 2 "register_operand" "0")
(const_int 1))))
(clobber (reg:CC CC_REGNUM))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ "(TARGET_V850E_UP)"
"cmp %4,%3 ; sasf %c1,%0"
- [(set_attr "length" "6")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "6")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")
(match_operand:SI 3 "const_int_operand" "")))
(clobber (reg:CC CC_REGNUM))]
- "(TARGET_V850E || TARGET_V850E2_ALL)
+ "(TARGET_V850E_UP)
&& ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1)
&& ((INTVAL (operands[2]) + INTVAL (operands[3])) != 1)
&& (GET_CODE (operands[5]) == CONST_INT
(rotate:HI (match_operand:HI 1 "register_operand" "")
(match_operand:HI 2 "const_int_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ "(TARGET_V850E_UP)"
{
if (INTVAL (operands[2]) != 8)
FAIL;
(rotate:HI (match_operand:HI 1 "register_operand" "r")
(const_int 8)))
(clobber (reg:CC CC_REGNUM))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ "(TARGET_V850E_UP)"
"bsh %1,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
(define_expand "rotlsi3"
[(parallel [(set (match_operand:SI 0 "register_operand" "")
(rotate:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ "(TARGET_V850E_UP)"
{
if (INTVAL (operands[2]) != 16)
FAIL;
})
+(define_insn "rotlsi3_a"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operator:SI 4 "ior_operator"
+ [(ashift:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "const_int_operand" "n"))
+ (lshiftrt:SI (match_dup 1)
+ (match_operand:SI 3 "const_int_operand" "n"))]))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_V850E3V5_UP && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32)"
+ "rotl %2, %1, %0"
+ [(set_attr "length" "4")])
+
+(define_insn "rotlsi3_b"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operator:SI 4 "ior_operator"
+ [(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 3 "const_int_operand" "n"))
+ (ashift:SI (match_dup 1)
+ (match_operand:SI 2 "const_int_operand" "n"))]))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_V850E3V5_UP && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32)"
+ "rotl %2, %1, %0"
+ [(set_attr "length" "4")])
+
+(define_insn "rotlsi3_v850e3v5"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (rotate:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "e3v5_shift_operand" "rn")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_V850E3V5_UP"
+ "rotl %2, %1, %0"
+ [(set_attr "length" "4")])
+
(define_insn "*rotlsi3_16"
[(set (match_operand:SI 0 "register_operand" "=r")
(rotate:SI (match_operand:SI 1 "register_operand" "r")
(const_int 16)))
(clobber (reg:CC CC_REGNUM))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ "(TARGET_V850E_UP)"
"hsw %1,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
;; ----------------------------------------------------------------------
;; JUMP INSTRUCTIONS
;; ----------------------------------------------------------------------
+;; Doloop
+
+(define_expand "doloop_begin"
+ [(use (match_operand 0 "" "")) ; loop pseudo
+ (use (match_operand 1 "" ""))] ; doloop_end pattern
+ "TARGET_V850E3V5_UP && TARGET_LOOP"
+ {
+ rtx loop_cnt = operands[0];
+ gcc_assert (GET_MODE (loop_cnt) == SImode);
+ emit_insn (gen_fix_loop_counter (loop_cnt));
+ DONE;
+ }
+)
+
+;; Note the embedded arithmetic. That affects the condition codes!
+(define_insn "fix_loop_counter"
+ [(unspec:SI [(match_operand:SI 0 "register_operand" "+r,!m")
+ (clobber (match_scratch:SI 1 "=X,r"))] UNSPEC_LOOP)
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_V850E3V5_UP && TARGET_LOOP"
+ {
+ switch (which_alternative)
+ {
+ case 0: return "add 1, %0 # LOOP_BEGIN";
+ case 1: return "ld.w %0, %1; add 1, %1; st.w %1, %0 # LOOP_BEGIN";
+ default: gcc_unreachable ();
+ }
+ }
+ [(set_attr "length" "2,6")])
+
+(define_expand "doloop_end"
+ [(use (match_operand 0 "" "")) ; loop pseudo
+ (use (match_operand 1 "" ""))] ; label
+ "TARGET_V850E3V5_UP && TARGET_LOOP"
+ {
+ rtx loop_cnt = operands[0];
+ rtx label = operands[1];
+
+ if (GET_MODE (loop_cnt) != SImode)
+ FAIL;
+
+ emit_jump_insn (gen_doloop_end_internal_loop (label, loop_cnt));
+ DONE;
+ }
+)
+
+(define_insn "doloop_end_internal_loop"
+ [(set (pc)
+ (if_then_else (ne (match_operand:SI 1 "register_operand" "+r,!m")
+ (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))
+ (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))
+ (clobber (match_scratch:SI 2 "=X,r"))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_V850E3V5_UP && TARGET_LOOP"
+ {
+ switch (which_alternative)
+ {
+ case 0:
+ if (get_attr_length (insn) == 4)
+ return "loop %1, %0 # LOOP.1.0";
+
+ return "add -1, %1; bne %l0 # LOOP.1.1";
+ case 1:
+ return "ld.w %1, %2; add -1, %2; st.w %2, %1; bne %l0 # LOOP.2.1";
+ default:
+ gcc_unreachable ();
+ }
+ }
+ [(set (attr "length")
+ (if_then_else (lt (abs (minus (match_dup 0) (pc)))
+ (const_int 65534))
+ (const_int 4)
+ (const_int 14)))])
+
;; Conditional jump instructions
+(define_insn_and_split "*cbranchsi4_insn"
+ [(set (pc)
+ (if_then_else (match_operator 0 "comparison_operator"
+ [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "reg_or_int5_operand" "rJ")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+ "#"
+ "reload_completed"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_dup 1) (match_dup 2)))
+ (set (pc)
+ (if_then_else (match_op_dup 0
+ [(reg:CC CC_REGNUM) (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))]
+ "")
+
(define_insn "*branch_normal"
[(set (pc)
(if_then_else (match_operator 1 "comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg CC_REGNUM) (const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))]
- ""
+ "reload_completed"
{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
- && (GET_CODE (operands[1]) == GT
- || GET_CODE (operands[1]) == GE
- || GET_CODE (operands[1]) == LE
- || GET_CODE (operands[1]) == LT))
- return 0;
-
+ bool nzmode = GET_MODE (XEXP (operands[1], 0)) == CCNZmode;
if (get_attr_length (insn) == 2)
- return "b%b1 %l0";
+ {
+ if (nzmode)
+ return "b%d1 %l0";
+ else
+ return "b%b1 %l0";
+ }
+ if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4)
+ {
+ if (nzmode)
+ return "b%d1 %l0";
+ else
+ return "b%b1 %l0";
+ }
+ if (nzmode)
+ return "b%D1 .+6 ; jr %l0";
else
return "b%B1 .+6 ; jr %l0";
}
(if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256))
(const_int 2)
- (const_int 6)))
- (set_attr "cc" "none")])
+ (if_then_else (lt (abs (minus (match_dup 0) (pc)))
+ (const_int 65536))
+ (const_int 4)
+ (const_int 6))))])
(define_insn "*branch_invert"
[(set (pc)
(if_then_else (match_operator 1 "comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg CC_REGNUM) (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
- ""
+ "reload_completed"
{
- if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
- && (GET_CODE (operands[1]) == GT
- || GET_CODE (operands[1]) == GE
- || GET_CODE (operands[1]) == LE
- || GET_CODE (operands[1]) == LT))
- return 0;
- if (get_attr_length (insn) == 2)
- return "b%B1 %l0";
- else
- return "b%b1 .+6 ; jr %l0";
-}
- [(set (attr "length")
- (if_then_else (lt (abs (minus (match_dup 0) (pc)))
- (const_int 256))
- (const_int 2)
- (const_int 6)))
- (set_attr "cc" "none")])
+ bool nzmode = GET_MODE (XEXP (operands[1], 0)) == CCNZmode;
-(define_insn "branch_z_normal"
- [(set (pc)
- (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "")
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_V850E2V3"
-{
if (get_attr_length (insn) == 2)
- return "bz %l0";
- else
- return "bnz 1f ; jr %l0 ; 1:";
-}
- [(set (attr "length")
- (if_then_else (lt (abs (minus (match_dup 0) (pc)))
- (const_int 256))
- (const_int 2)
- (const_int 6)))
- (set_attr "cc" "none")])
-
-(define_insn "*branch_z_invert"
- [(set (pc)
- (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "")
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "TARGET_V850E2V3"
-{
- if (get_attr_length (insn) == 2)
- return "bnz %l0";
- else
- return "bz 1f ; jr %l0 ; 1:";
-}
- [(set (attr "length")
- (if_then_else (lt (abs (minus (match_dup 0) (pc)))
- (const_int 256))
- (const_int 2)
- (const_int 6)))
- (set_attr "cc" "none")])
+ {
+ if (nzmode)
+ return "b%D1 %l0";
+ else
+ return "b%B1 %l0";
+ }
-(define_insn "branch_nz_normal"
- [(set (pc)
- (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "")
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_V850E2V3"
-{
- if (get_attr_length (insn) == 2)
- return "bnz %l0";
- else
- return "bz 1f ; jr %l0 ; 1:";
-}
-[(set (attr "length")
- (if_then_else (lt (abs (minus (match_dup 0) (pc)))
- (const_int 256))
- (const_int 2)
- (const_int 6)))
- (set_attr "cc" "none")])
+ if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4)
+ {
+ if (nzmode)
+ return "b%D1 %l0";
+ else
+ return "b%B1 %l0";
+ }
-(define_insn "*branch_nz_invert"
- [(set (pc)
- (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "")
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "TARGET_V850E2V3"
-{
- if (get_attr_length (insn) == 2)
- return "bz %l0";
+ if (nzmode)
+ return "b%d1 .+6 ; jr %l0";
else
- return "bnz 1f ; jr %l0 ; 1:";
+ return "b%b1 .+6 ; jr %l0";
}
[(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256))
(const_int 2)
- (const_int 6)))
- (set_attr "cc" "none")])
+ (if_then_else (lt (abs (minus (match_dup 0) (pc)))
+ (const_int 65536))
+ (const_int 4)
+ (const_int 6))))])
;; Unconditional and other jump instructions.
(if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256))
(const_int 2)
- (const_int 4)))
- (set_attr "cc" "none")])
+ (const_int 4)))])
(define_insn "indirect_jump"
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
""
"jmp %0"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
(define_insn "tablejump"
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
(use (label_ref (match_operand 1 "" "")))]
""
"jmp %0"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
(define_insn "switch"
[(set (pc)
(const_int 1))
(label_ref (match_operand 1 "" "")))))
(label_ref (match_dup 1))))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ "(TARGET_V850E_UP)"
"switch %0"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
(define_expand "casesi"
[(match_operand:SI 0 "register_operand" "")
(define_insn "call_internal_short"
[(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
(match_operand:SI 1 "general_operand" "g,g"))
+ (clobber (reg:CC CC_REGNUM))
(clobber (reg:SI 31))]
"! TARGET_LONG_CALLS"
- "@
- jarl %0,r31
- jarl .+4,r31 ; add 4,r31 ; jmp %0"
- [(set_attr "length" "4,8")
- (set_attr "cc" "clobber,clobber")]
-)
+ {
+ if (which_alternative == 1)
+ {
+ if (TARGET_V850E3V5_UP)
+ return "jarl [%0], r31";
+
+ return "jarl .+4, r31 ; add 4, r31 ; jmp %0";
+ }
+
+ return "jarl %0, r31";
+ }
+ [(set_attr "length" "4,8")])
(define_insn "call_internal_long"
[(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
(match_operand:SI 1 "general_operand" "g,g"))
+ (clobber (reg:CC CC_REGNUM))
(clobber (reg:SI 31))]
"TARGET_LONG_CALLS"
{
{
if (GET_CODE (operands[0]) == REG)
return "jarl %0,r31";
- else
- return "movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11";
+
+ if (TARGET_V850E3V5_UP)
+ return "mov hilo(%0), r11 ; jarl [r11], r31";
+
+ return "movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11";
}
- else
- return "jarl .+4,r31 ; add 4,r31 ; jmp %0";
+
+ if (TARGET_V850E3V5_UP)
+ return "jarl [%0], r31";
+
+ return "jarl .+4,r31 ; add 4,r31 ; jmp %0";
}
- [(set_attr "length" "16,8")
- (set_attr "cc" "clobber,clobber")]
-)
+ [(set_attr "length" "16,8")])
;; Call subroutine, returning value in operand 0
;; (which must be a hard register).
[(set (match_operand 0 "" "=r,r")
(call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
(match_operand:SI 2 "general_operand" "g,g")))
+ (clobber (reg:CC CC_REGNUM))
(clobber (reg:SI 31))]
"! TARGET_LONG_CALLS"
- "@
- jarl %1,r31
- jarl .+4,r31 ; add 4,r31 ; jmp %1"
- [(set_attr "length" "4,8")
- (set_attr "cc" "clobber,clobber")]
-)
+ {
+ if (which_alternative == 1)
+ {
+ if (TARGET_V850E3V5_UP)
+ return "jarl [%1], r31";
+
+ return "jarl .+4, r31 ; add 4, r31 ; jmp %1";
+ }
+
+ return "jarl %1, r31";
+ }
+ [(set_attr "length" "4,8")])
(define_insn "call_value_internal_long"
[(set (match_operand 0 "" "=r,r")
(call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
(match_operand:SI 2 "general_operand" "g,g")))
+ (clobber (reg:CC CC_REGNUM))
(clobber (reg:SI 31))]
"TARGET_LONG_CALLS"
{
{
if (GET_CODE (operands[1]) == REG)
return "jarl %1, r31";
- else
+
/* Reload can generate this pattern.... */
- return "movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11";
+ if (TARGET_V850E3V5_UP)
+ return "mov hilo(%1), r11 ; jarl [r11], r31";
+
+ return "movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11";
}
- else
- return "jarl .+4, r31 ; add 4, r31 ; jmp %1";
+
+ if (TARGET_V850E3V5_UP)
+ return "jarl [%1], r31";
+
+ return "jarl .+4, r31 ; add 4, r31 ; jmp %1";
}
- [(set_attr "length" "16,8")
- (set_attr "cc" "clobber,clobber")]
-)
+ [(set_attr "length" "16,8")])
(define_insn "nop"
[(const_int 0)]
""
"nop"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
\f
;; ----------------------------------------------------------------------
;; EXTEND INSTRUCTIONS
;; ----------------------------------------------------------------------
+;; We only need the CC clobber because of the andi alternative
(define_insn "*zero_extendhisi2_v850e"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
(zero_extend:SI
(match_operand:HI 1 "nonimmediate_operand" "0,r,T,m")))
(clobber (reg:CC CC_REGNUM))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ "(TARGET_V850E_UP)"
"@
zxh %0
andi 65535,%1,%0
sld.hu %1,%0
ld.hu %1,%0"
- [(set_attr "length" "2,4,2,4")
- (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")])
+ [(set_attr "length" "2,4,2,4")])
(define_insn "*zero_extendhisi2_v850"
[(set (match_operand:SI 0 "register_operand" "=r")
(clobber (reg:CC CC_REGNUM))] ;; A lie, but we have to match the expander
""
"andi 65535,%1,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "4")])
+
+(define_insn "*zero_extendhisi2_v850_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extend:SI (match_dup 1)))]
+ "reload_completed"
+ "andi 65535,%1,%0"
+ [(set_attr "length" "4")])
(define_expand "zero_extendhisi2"
[(parallel [(set (match_operand:SI 0 "register_operand")
(clobber (reg:CC CC_REGNUM))])]
""
{
- if (! (TARGET_V850E || TARGET_V850E2_ALL))
+ if (! (TARGET_V850E_UP))
operands[1] = force_reg (HImode, operands[1]);
})
(zero_extend:SI
(match_operand:QI 1 "nonimmediate_operand" "0,r,T,m")))
(clobber (reg:CC CC_REGNUM))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ "(TARGET_V850E_UP)"
"@
zxb %0
andi 255,%1,%0
sld.bu %1,%0
ld.bu %1,%0"
- [(set_attr "length" "2,4,2,4")
- (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")])
+ [(set_attr "length" "2,4,2,4")])
(define_insn "*zero_extendqisi2_v850"
[(set (match_operand:SI 0 "register_operand" "=r")
(clobber (reg:CC CC_REGNUM))] ;; A lie, but we have to match the expander
""
"andi 255,%1,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "4")])
+
+(define_insn "*zero_extendqisi2_v850_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extend:SI (match_dup 1)))]
+ "reload_completed"
+ "andi 255,%1,%0"
+ [(set_attr "length" "4")])
(define_expand "zero_extendqisi2"
[(parallel [(set (match_operand:SI 0 "register_operand")
(clobber (reg:CC CC_REGNUM))])]
""
{
- if (! (TARGET_V850E || TARGET_V850E2_ALL))
+ if (! (TARGET_V850E_UP))
operands[1] = force_reg (QImode, operands[1]);
})
(define_insn "*extendhisi_insn"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,Q,m")))
- (clobber (reg:CC CC_REGNUM))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,Q,m")))]
+ "(TARGET_V850E_UP)"
"@
sxh %0
sld.h %1,%0
ld.h %1,%0"
- [(set_attr "length" "2,2,4")
- (set_attr "cc" "none_0hit,none_0hit,none_0hit")])
+ [(set_attr "length" "2,2,4")])
;; ??? This is missing a sign extend from memory pattern to match the ld.h
;; instruction.
(define_insn "*extendqisi_insn"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,Q,m")))
- (clobber (reg:CC CC_REGNUM))]
- "(TARGET_V850E || TARGET_V850E2_ALL)"
+ (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,Q,m")))]
+ "(TARGET_V850E_UP)"
"@
sxb %0
sld.b %1,%0
ld.b %1,%0"
- [(set_attr "length" "2,2,4")
- (set_attr "cc" "none_0hit,none_0hit,none_0hit")])
+ [(set_attr "length" "2,2,4")])
;; ??? This is missing a sign extend from memory pattern to match the ld.b
;; instruction.
;; SHIFTS
;; ----------------------------------------------------------------------
-(define_insn "ashlsi3"
+(define_insn_and_split "ashlsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (ashift:SI
+ (match_operand:SI 1 "register_operand" "0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,N")))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])])
+
+(define_insn "ashlsi3_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ashift:SI
(match_operand:SI 1 "register_operand" "0,0")
"@
shl %2,%0
shl %2,%0"
- [(set_attr "length" "4,2")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "4,2")])
+
+(define_insn "ashlsi3_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,N"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r")
+ (ashift:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ shl %2,%0
+ shl %2,%0"
+ [(set_attr "length" "4,2")])
-(define_insn "ashlsi3_v850e2"
+(define_insn "ashlsi3_v850e2_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashift:SI
(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "nonmemory_operand" "r")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_V850E2_ALL"
+ "TARGET_V850E2_UP"
"shl %2,%1,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "set_znv")])
+ [(set_attr "length" "4")])
+
+(define_insn "ashlsi3_v850e2_set_flags"
+ [(set (reg:CCNZ CC_REGNUM)
+ (compare:CCNZ (ashift:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "nonmemory_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (ashift:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed && TARGET_V850E2_UP"
+ "shl %2,%1,%0"
+ [(set_attr "length" "4")])
+
+(define_insn_and_split "lshrsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (lshiftrt:SI
+ (match_operand:SI 1 "register_operand" "0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,N")))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])])
-(define_insn "lshrsi3"
+(define_insn "lshrsi3_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(lshiftrt:SI
(match_operand:SI 1 "register_operand" "0,0")
"@
shr %2,%0
shr %2,%0"
- [(set_attr "length" "4,2")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "4,2")])
+
+(define_insn "lshrsi3_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,N"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r")
+ (lshiftrt:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ shr %2,%0
+ shr %2,%0"
+ [(set_attr "length" "4,2")])
-(define_insn "lshrsi3_v850e2"
+(define_insn "lshrsi3_v850e2_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI
(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "nonmemory_operand" "r")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_V850E2_ALL"
+ "TARGET_V850E2_UP"
"shr %2,%1,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "4")])
+
+(define_insn "lshrsi3_v850e2_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "nonmemory_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (lshiftrt:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed && TARGET_V850E2_UP"
+ "shr %2,%1,%0"
+ [(set_attr "length" "4")])
+
+(define_insn_and_split "ashrsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (ashiftrt:SI
+ (match_operand:SI 1 "register_operand" "0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,N")))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])])
-(define_insn "ashrsi3"
+(define_insn "ashrsi3_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ashiftrt:SI
(match_operand:SI 1 "register_operand" "0,0")
"@
sar %2,%0
sar %2,%0"
- [(set_attr "length" "4,2")
- (set_attr "cc" "set_zn, set_zn")])
+ [(set_attr "length" "4,2")])
+
+(define_insn "ashrsi3_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,N"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r,r")
+ (ashiftrt:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed"
+ "@
+ sar %2,%0
+ sar %2,%0"
+ [(set_attr "length" "4,2")])
-(define_insn "ashrsi3_v850e2"
+(define_insn "ashrsi3_v850e2_clobber_flags"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI
(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "nonmemory_operand" "r")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_V850E2_ALL"
+ "TARGET_V850E2_UP"
"sar %2,%1,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "4")])
+
+(define_insn "ashrsi3_v850e2_set_flags"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "nonmemory_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=r")
+ (ashiftrt:SI (match_dup 1) (match_dup 2)))]
+ "reload_completed && TARGET_V850E2_UP"
+ "sar %2,%1,%0"
+ [(set_attr "length" "4")])
;; ----------------------------------------------------------------------
;; FIND FIRST BIT INSTRUCTION
[(set (match_operand:SI 0 "register_operand" "=r")
(ffs:SI (match_operand:SI 1 "register_operand" "r")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_V850E2_ALL"
+ "TARGET_V850E2_UP"
"sch1r %1,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
;; ----------------------------------------------------------------------
;; PROLOGUE/EPILOGUE
[(return)]
"reload_completed"
"jmp [r31]"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
(define_insn "return_internal"
[(return)
(use (reg:SI 31))]
""
"jmp [r31]"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
;; ----------------------------------------------------------------------
;; v850e2V3 floating-point hardware support
[(set (match_operand:SF 0 "register_operand" "=r")
(plus:SF (match_operand:SF 1 "register_operand" "r")
(match_operand:SF 2 "register_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"addf.s %1,%2,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "adddf3"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(plus:DF (match_operand:DF 1 "even_reg_operand" "r")
(match_operand:DF 2 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"addf.d %1,%2,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "subsf3"
[(set (match_operand:SF 0 "register_operand" "=r")
(minus:SF (match_operand:SF 1 "register_operand" "r")
(match_operand:SF 2 "register_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"subf.s %2,%1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "subdf3"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(minus:DF (match_operand:DF 1 "even_reg_operand" "r")
(match_operand:DF 2 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"subf.d %2,%1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "mulsf3"
[(set (match_operand:SF 0 "register_operand" "=r")
(mult:SF (match_operand:SF 1 "register_operand" "r")
(match_operand:SF 2 "register_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"mulf.s %1,%2,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "muldf3"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(mult:DF (match_operand:DF 1 "even_reg_operand" "r")
(match_operand:DF 2 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"mulf.d %1,%2,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "divsf3"
[(set (match_operand:SF 0 "register_operand" "=r")
(div:SF (match_operand:SF 1 "register_operand" "r")
(match_operand:SF 2 "register_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"divf.s %2,%1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "divdf3"
[(set (match_operand:DF 0 "register_operand" "=r")
(div:DF (match_operand:DF 1 "even_reg_operand" "r")
(match_operand:DF 2 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"divf.d %2,%1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "minsf3"
[(set (match_operand:SF 0 "register_operand" "=r")
(smin:SF (match_operand:SF 1 "reg_or_0_operand" "r")
(match_operand:SF 2 "reg_or_0_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"minf.s %z1,%z2,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "mindf3"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(smin:DF (match_operand:DF 1 "even_reg_operand" "r")
(match_operand:DF 2 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"minf.d %1,%2,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "maxsf3"
[(set (match_operand:SF 0 "register_operand" "=r")
(smax:SF (match_operand:SF 1 "reg_or_0_operand" "r")
(match_operand:SF 2 "reg_or_0_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"maxf.s %z1,%z2,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "maxdf3"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(smax:DF (match_operand:DF 1 "even_reg_operand" "r")
(match_operand:DF 2 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"maxf.d %1,%2,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "abssf2"
[(set (match_operand:SF 0 "register_operand" "=r")
(abs:SF (match_operand:SF 1 "register_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"absf.s %1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "absdf2"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(abs:DF (match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"absf.d %1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "negsf2"
[(set (match_operand:SF 0 "register_operand" "=r")
(neg:SF (match_operand:SF 1 "register_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"negf.s %1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "negdf2"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(neg:DF (match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"negf.d %1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
;; square-root
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=r")
(sqrt:SF (match_operand:SF 1 "register_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"sqrtf.s %1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(sqrt:DF (match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"sqrtf.d %1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
;; float -> int
(define_insn "fix_truncsfsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(fix:SI (match_operand:SF 1 "register_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"trncf.sw %1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
+ (set_attr "type" "fpu")])
+
+(define_insn "fixuns_truncsfsi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
+ "TARGET_USE_FPU"
+ "trncf.suw %1, %0"
+ [(set_attr "length" "4")
(set_attr "type" "fpu")])
(define_insn "fix_truncdfsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(fix:SI (match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"trncf.dw %1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
-(define_expand "fixuns_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (fix:SI (match_operand:SF 1 "register_operand" "r")))]
- "TARGET_V850E2V3")
+(define_insn "fixuns_truncdfsi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unsigned_fix:SI (match_operand:DF 1 "even_reg_operand" "r")))]
+ "TARGET_USE_FPU"
+ "trncf.duw %1, %0"
+ [(set_attr "length" "4")
+ (set_attr "type" "fpu")])
-(define_expand "fixuns_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (fix:SI (match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3")
+(define_insn "fix_truncsfdi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (fix:DI (match_operand:SF 1 "register_operand" "r")))]
+ "TARGET_USE_FPU"
+ "trncf.sl %1, %0"
+ [(set_attr "length" "4")
+ (set_attr "type" "fpu")])
+
+(define_insn "fixuns_truncsfdi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unsigned_fix:DI (match_operand:SF 1 "register_operand" "r")))]
+ "TARGET_USE_FPU"
+ "trncf.sul %1, %0"
+ [(set_attr "length" "4")
+ (set_attr "type" "fpu")])
+
+(define_insn "fix_truncdfdi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (fix:DI (match_operand:DF 1 "even_reg_operand" "r")))]
+ "TARGET_USE_FPU"
+ "trncf.dl %1, %0"
+ [(set_attr "length" "4")
+ (set_attr "type" "fpu")])
+
+(define_insn "fixuns_truncdfdi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unsigned_fix:DI (match_operand:DF 1 "even_reg_operand" "r")))]
+ "TARGET_USE_FPU"
+ "trncf.dul %1, %0"
+ [(set_attr "length" "4")
+ (set_attr "type" "fpu")])
;; int -> float
(define_insn "floatsisf2"
[(set (match_operand:SF 0 "register_operand" "=r")
(float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"cvtf.ws %z1, %0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
+ (set_attr "type" "fpu")])
+
+(define_insn "unsfloatsisf2"
+ [(set (match_operand:SF 0 "register_operand" "=r")
+ (unsigned_float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
+ "TARGET_USE_FPU"
+ "cvtf.uws %z1, %0"
+ [(set_attr "length" "4")
(set_attr "type" "fpu")])
(define_insn "floatsidf2"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"cvtf.wd %z1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
+ (set_attr "type" "fpu")])
+
+(define_insn "unsfloatsidf2"
+ [(set (match_operand:DF 0 "even_reg_operand" "=r")
+ (unsigned_float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
+ "TARGET_USE_FPU"
+ "cvtf.uwd %z1, %0"
+ [(set_attr "length" "4")
+ (set_attr "type" "fpu")])
+
+(define_insn "floatdisf2"
+ [(set (match_operand:SF 0 "even_reg_operand" "=r")
+ (float:SF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
+ "TARGET_USE_FPU"
+ "cvtf.ls %z1, %0"
+ [(set_attr "length" "4")
+ (set_attr "type" "fpu")])
+
+(define_insn "unsfloatdisf2"
+ [(set (match_operand:SF 0 "even_reg_operand" "=r")
+ (unsigned_float:SF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
+ "TARGET_USE_FPU"
+ "cvtf.uls %z1, %0"
+ [(set_attr "length" "4")
+ (set_attr "type" "fpu")])
+
+(define_insn "floatdidf2"
+ [(set (match_operand:DF 0 "even_reg_operand" "=r")
+ (float:DF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
+ "TARGET_USE_FPU"
+ "cvtf.ld %z1, %0"
+ [(set_attr "length" "4")
+ (set_attr "type" "fpu")])
+
+(define_insn "unsfloatdidf2"
+ [(set (match_operand:DF 0 "even_reg_operand" "=r")
+ (unsigned_float:DF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
+ "TARGET_USE_FPU"
+ "cvtf.uld %z1, %0"
+ [(set_attr "length" "4")
(set_attr "type" "fpu")])
;; single-float -> double-float
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "rI")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"cvtf.sd %z1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
;; double-float -> single-float
[(set (match_operand:SF 0 "register_operand" "=r")
(float_truncate:SF
(match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"cvtf.ds %1,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
;;
;; ---------------- special insns
;;
-;;; reciprocal
-(define_insn "recipsf2"
+;; reciprocal
+
+;; Generic code demands that the recip and rsqrt named patterns
+;; have precisely one operand. So that's what we expose in the
+;; expander via the strange UNSPEC. However, those expanders
+;; generate normal looking recip and rsqrt patterns.
+
+(define_expand "recipsf2"
+ [(set (match_operand:SF 0 "register_operand" "")
+ (unspec:SF [(match_operand:SF 1 "register_operand" "")]
+ UNSPEC_RCP))]
+ "TARGET_USE_FPU"
+ {
+ emit_insn (gen_recipsf2_insn (operands[0], CONST1_RTX (SFmode), operands[1]));
+ DONE;
+ })
+
+(define_insn "recipsf2_insn"
[(set (match_operand:SF 0 "register_operand" "=r")
(div:SF (match_operand:SF 1 "const_float_1_operand" "")
(match_operand:SF 2 "register_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"recipf.s %2,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
-(define_insn "recipdf2"
+(define_expand "recipdf2"
+ [(set (match_operand:DF 0 "even_reg_operand" "")
+ (unspec:DF [(match_operand:SF 1 "even_reg_operand" "")]
+ UNSPEC_RCP))]
+ "TARGET_USE_FPU"
+ {
+ emit_insn (gen_recipdf2_insn (operands[0], CONST1_RTX (DFmode), operands[1]));
+ DONE;
+ })
+
+(define_insn "recipdf2_insn"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(div:DF (match_operand:DF 1 "const_float_1_operand" "")
(match_operand:DF 2 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"recipf.d %2,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
;;; reciprocal of square-root
-(define_insn "rsqrtsf2"
+(define_expand "rsqrtsf2"
+ [(set (match_operand:SF 0 "register_operand" "=")
+ (unspec:SF [(match_operand:SF 1 "register_operand" "")]
+ UNSPEC_RSQRT))]
+ "TARGET_USE_FPU"
+ {
+ emit_insn (gen_rsqrtsf2_insn (operands[0], CONST1_RTX (SFmode), operands[1]));
+ DONE;
+ })
+
+(define_insn "rsqrtsf2_insn"
[(set (match_operand:SF 0 "register_operand" "=r")
(div:SF (match_operand:SF 1 "const_float_1_operand" "")
(sqrt:SF (match_operand:SF 2 "register_operand" "r"))))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"rsqrtf.s %2,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
-(define_insn "rsqrtdf2"
+(define_expand "rsqrtdf2"
+ [(set (match_operand:DF 0 "even_reg_operand" "=r")
+ (unspec:DF [(match_operand:DF 1 "even_reg_operand" "r")]
+ UNSPEC_RSQRT))]
+ "TARGET_USE_FPU"
+ {
+ emit_insn (gen_rsqrtdf2_insn (operands[0], CONST1_RTX (DFmode), operands[1]));
+ DONE;
+ })
+
+(define_insn "rsqrtdf2_insn"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(div:DF (match_operand:DF 1 "const_float_1_operand" "")
(sqrt:DF (match_operand:DF 2 "even_reg_operand" "r"))))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"rsqrtf.d %2,%0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
+;; Note: The FPU-2.0 (ie pre e3v5) versions of these routines do not actually
+;; need operand 4 to be the same as operand 0. But the FPU-2.0 versions are
+;; also deprecated so the loss of flexibility is unimportant.
+
;;; multiply-add
(define_insn "fmasf4"
[(set (match_operand:SF 0 "register_operand" "=r")
(fma:SF (match_operand:SF 1 "register_operand" "r")
(match_operand:SF 2 "register_operand" "r")
- (match_operand:SF 3 "register_operand" "r")))]
- "TARGET_V850E2V3"
- "maddf.s %2,%1,%3,%0"
+ (match_operand:SF 3 "register_operand" "0")))]
+ "TARGET_USE_FPU"
+ { return TARGET_V850E3V5_UP ? "fmaf.s %1, %2, %0" : "maddf.s %2, %1, %3, %0"; }
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
;;; multiply-subtract
[(set (match_operand:SF 0 "register_operand" "=r")
(fma:SF (match_operand:SF 1 "register_operand" "r")
(match_operand:SF 2 "register_operand" "r")
- (neg:SF (match_operand:SF 3 "register_operand" "r"))))]
- "TARGET_V850E2V3"
- "msubf.s %2,%1,%3,%0"
+ (neg:SF (match_operand:SF 3 "register_operand" "0"))))]
+ "TARGET_USE_FPU"
+ { return TARGET_V850E3V5_UP ? "fmsf.s %1, %2, %0" : "msubf.s %2, %1, %3, %0"; }
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
;;; negative-multiply-add
(define_insn "fnmasf4"
[(set (match_operand:SF 0 "register_operand" "=r")
- (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
- (match_operand:SF 2 "register_operand" "r")
- (match_operand:SF 3 "register_operand" "r")))]
- "TARGET_V850E2V3"
- "nmaddf.s %2,%1,%3,%0"
+ (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r")
+ (match_operand:SF 2 "register_operand" "r")
+ (match_operand:SF 3 "register_operand" "0"))))]
+ "TARGET_USE_FPU"
+ { return TARGET_V850E3V5_UP ? "fnmaf.s %1, %2, %0" : "nmaddf.s %2, %1, %3, %0"; }
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
;; negative-multiply-subtract
(define_insn "fnmssf4"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
- (match_operand:SF 2 "register_operand" "r")
- (neg:SF (match_operand:SF 3 "register_operand" "r"))))]
- "TARGET_V850E2V3"
- "nmsubf.s %2,%1,%3,%0"
+ [(set (match_operand:SF 0 "register_operand" "=r")
+ (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r")
+ (match_operand:SF 2 "register_operand" "r")
+ (neg:SF (match_operand:SF 3 "register_operand" "0")))))]
+ "TARGET_USE_FPU"
+ { return TARGET_V850E3V5_UP ? "fnmsf.s %1, %2, %0" : "nmsubf.s %2, %1, %3, %0"; }
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
;
; ---------------- comparison/conditionals
[(set (reg:CC_FPU_LE FCC_REGNUM)
(compare:CC_FPU_LE (match_operand:SF 0 "register_operand" "r")
(match_operand:SF 1 "register_operand" "r")))]
- "TARGET_V850E2V3"
- "cmpf.s le,%z0,%z1"
+ "reload_completed && TARGET_USE_FPU"
+ "cmpf.s le, %z0, %z1"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "cmpsf_lt_insn"
[(set (reg:CC_FPU_LT FCC_REGNUM)
(compare:CC_FPU_LT (match_operand:SF 0 "register_operand" "r")
(match_operand:SF 1 "register_operand" "r")))]
- "TARGET_V850E2V3"
- "cmpf.s lt,%z0,%z1"
+ "reload_completed && TARGET_USE_FPU"
+ "cmpf.s lt, %z0, %z1"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "cmpsf_ge_insn"
[(set (reg:CC_FPU_GE FCC_REGNUM)
(compare:CC_FPU_GE (match_operand:SF 0 "register_operand" "r")
(match_operand:SF 1 "register_operand" "r")))]
- "TARGET_V850E2V3"
- "cmpf.s ge,%z0,%z1"
+ "reload_completed && TARGET_USE_FPU"
+ "cmpf.s le, %z1, %z0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "cmpsf_gt_insn"
[(set (reg:CC_FPU_GT FCC_REGNUM)
(compare:CC_FPU_GT (match_operand:SF 0 "register_operand" "r")
(match_operand:SF 1 "register_operand" "r")))]
- "TARGET_V850E2V3"
- "cmpf.s gt,%z0,%z1"
+ "reload_completed && TARGET_USE_FPU"
+ "cmpf.s lt, %z1, %z0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "cmpsf_eq_insn"
[(set (reg:CC_FPU_EQ FCC_REGNUM)
(compare:CC_FPU_EQ (match_operand:SF 0 "register_operand" "r")
(match_operand:SF 1 "register_operand" "r")))]
- "TARGET_V850E2V3"
- "cmpf.s eq,%z0,%z1"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
- (set_attr "type" "fpu")])
-
-(define_insn "cmpsf_ne_insn"
- [(set (reg:CC_FPU_NE FCC_REGNUM)
- (compare:CC_FPU_NE (match_operand:SF 0 "register_operand" "r")
- (match_operand:SF 1 "register_operand" "r")))]
- "TARGET_V850E2V3"
- "cmpf.s neq,%z0,%z1"
+ "reload_completed && TARGET_USE_FPU"
+ "cmpf.s eq, %z0, %z1"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
; DF
[(set (reg:CC_FPU_LE FCC_REGNUM)
(compare:CC_FPU_LE (match_operand:DF 0 "even_reg_operand" "r")
(match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
- "cmpf.d le,%z0,%z1"
+ "reload_completed && TARGET_USE_FPU"
+ "cmpf.d le, %z0, %z1"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "cmpdf_lt_insn"
[(set (reg:CC_FPU_LT FCC_REGNUM)
(compare:CC_FPU_LT (match_operand:DF 0 "even_reg_operand" "r")
(match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
- "cmpf.d lt,%z0,%z1"
+ "reload_completed && TARGET_USE_FPU"
+ "cmpf.d lt, %z0, %z1"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "cmpdf_ge_insn"
[(set (reg:CC_FPU_GE FCC_REGNUM)
(compare:CC_FPU_GE (match_operand:DF 0 "even_reg_operand" "r")
(match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
- "cmpf.d ge,%z0,%z1"
+ "reload_completed && TARGET_USE_FPU"
+ "cmpf.d le, %z1, %z0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "cmpdf_gt_insn"
[(set (reg:CC_FPU_GT FCC_REGNUM)
(compare:CC_FPU_GT (match_operand:DF 0 "even_reg_operand" "r")
- (match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
- "cmpf.d gt,%z0,%z1"
+ (match_operand:DF 1 "even_reg_operand" "r")))]
+ "reload_completed && TARGET_USE_FPU"
+ "cmpf.d lt, %z1, %z0"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
(define_insn "cmpdf_eq_insn"
[(set (reg:CC_FPU_EQ FCC_REGNUM)
(compare:CC_FPU_EQ (match_operand:DF 0 "even_reg_operand" "r")
(match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
- "cmpf.d eq,%z0,%z1"
+ "reload_completed && TARGET_USE_FPU"
+ "cmpf.d eq, %z0, %z1"
[(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
-(define_insn "cmpdf_ne_insn"
- [(set (reg:CC_FPU_NE FCC_REGNUM)
- (compare:CC_FPU_NE (match_operand:DF 0 "even_reg_operand" "r")
- (match_operand:DF 1 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
- "cmpf.d neq,%z0,%z1"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")
- (set_attr "type" "fpu")])
-
-
;;
;; Transfer a v850e2v3 fcc to the Z bit of CC0 (this is necessary to do a
;; conditional branch based on a floating-point compare)
(define_insn "trfsr"
[(set (match_operand 0 "" "") (match_operand 1 "" ""))]
- "TARGET_V850E2V3
+ "reload_completed
+ && TARGET_USE_FPU
&& GET_MODE(operands[0]) == GET_MODE(operands[1])
&& GET_CODE(operands[0]) == REG && REGNO (operands[0]) == CC_REGNUM
&& GET_CODE(operands[1]) == REG && REGNO (operands[1]) == FCC_REGNUM
|| GET_MODE(operands[0]) == CC_FPU_NEmode)"
"trfsr"
[(set_attr "length" "4")
- (set_attr "cc" "set_z")
(set_attr "type" "fpu")])
;;
(match_operand 3 "v850_float_z_comparison_operator" "")
(match_operand:SF 1 "reg_or_0_operand" "rIG")
(match_operand:SF 2 "reg_or_0_operand" "rIG")))]
- "TARGET_V850E2V3"
- "cmovf.s 0,%z1,%z2,%0"
- [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
+ "TARGET_USE_FPU"
+ "cmovf.s 0,%z1,%z2,%0")
(define_insn "movsfcc_nz_insn"
[(set (match_operand:SF 0 "register_operand" "=r")
(match_operand 3 "v850_float_nz_comparison_operator" "")
(match_operand:SF 1 "reg_or_0_operand" "rIG")
(match_operand:SF 2 "reg_or_0_operand" "rIG")))]
- "TARGET_V850E2V3"
- "cmovf.s 0,%z2,%z1,%0"
- [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
+ "TARGET_USE_FPU"
+ "cmovf.s 0,%z2,%z1,%0")
(define_insn "movdfcc_z_insn"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(match_operand 3 "v850_float_z_comparison_operator" "")
(match_operand:DF 1 "even_reg_operand" "r")
(match_operand:DF 2 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
- "cmovf.d 0,%z1,%z2,%0"
- [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
+ "TARGET_USE_FPU"
+ "cmovf.d 0,%z1,%z2,%0")
(define_insn "movdfcc_nz_insn"
[(set (match_operand:DF 0 "even_reg_operand" "=r")
(match_operand 3 "v850_float_nz_comparison_operator" "")
(match_operand:DF 1 "even_reg_operand" "r")
(match_operand:DF 2 "even_reg_operand" "r")))]
- "TARGET_V850E2V3"
- "cmovf.d 0,%z2,%z1,%0"
- [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
+ "TARGET_USE_FPU"
+ "cmovf.d 0,%z2,%z1,%0")
(define_insn "movedfcc_z_zero"
[(set (match_operand:DF 0 "register_operand" "=r")
(match_operand 3 "v850_float_z_comparison_operator" "")
(match_operand:DF 1 "reg_or_0_operand" "rIG")
(match_operand:DF 2 "reg_or_0_operand" "rIG")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"cmovf.s 0,%z1,%z2,%0 ; cmovf.s 0,%Z1,%Z2,%R0"
- [(set_attr "length" "8")
- (set_attr "cc" "clobber")]) ;; ??? or none_0hit
+ [(set_attr "length" "8")])
(define_insn "movedfcc_nz_zero"
[(set (match_operand:DF 0 "register_operand" "=r")
(match_operand 3 "v850_float_nz_comparison_operator" "")
(match_operand:DF 1 "reg_or_0_operand" "rIG")
(match_operand:DF 2 "reg_or_0_operand" "rIG")))]
- "TARGET_V850E2V3"
+ "TARGET_USE_FPU"
"cmovf.s 0,%z2,%z1,%0 ; cmovf.s 0,%Z2,%Z1,%R0"
- [(set_attr "length" "8")
- (set_attr "cc" "clobber")]) ;; ??? or none_0hit
+ [(set_attr "length" "8")])
;; ----------------------------------------------------------------------
(set (mem:SI (plus:SI (reg:SI 3)
(match_operand:SI 2 "immediate_operand" "i")))
(match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
- "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)"
+ "TARGET_PROLOG_FUNCTION && (TARGET_V850E_UP)"
{
return construct_prepare_instruction (operands[0]);
}
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
(define_insn ""
[(match_parallel 0 "pattern_is_ok_for_prologue"
}
[(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
(const_string "16")
- (const_string "4")))
- (set_attr "cc" "clobber")])
+ (const_string "4")))])
;;
;; Actually, turn the RTXs into a DISPOSE instruction.
(set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r")
(mem:SI (plus:SI (reg:SI 3)
(match_operand:SI 3 "immediate_operand" "i"))))])]
- "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)"
+ "TARGET_PROLOG_FUNCTION && (TARGET_V850E_UP)"
{
return construct_dispose_instruction (operands[0]);
}
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
;; This pattern will match a return RTX followed by any number of pop RTXs
;; and possible a stack adjustment as well. These RTXs will be turned into
}
[(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
(const_string "12")
- (const_string "4")))
- (set_attr "cc" "clobber")])
+ (const_string "4")))])
;; Initialize an interrupt function. Do not depend on TARGET_PROLOG_FUNCTION.
(define_insn "callt_save_interrupt"
- [(unspec_volatile [(const_int 0)] 2)]
- "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT"
+ [(unspec_volatile [(const_int 0)] 2)
+ (clobber (reg:CC CC_REGNUM))]
+ "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT"
;; The CALLT instruction stores the next address of CALLT to CTPC register
;; without saving its previous value. So if the interrupt handler
;; or its caller could possibly execute the CALLT insn, save_interrupt
output_asm_insn ("callt ctoff(__callt_save_interrupt)", operands);
return "";
}
- [(set_attr "length" "26")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "26")])
(define_insn "callt_return_interrupt"
- [(unspec_volatile [(const_int 0)] 3)]
- "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT"
+ [(unspec_volatile [(const_int 0)] 3)
+ (clobber (reg:CC CC_REGNUM))]
+ "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT"
"callt ctoff(__callt_return_interrupt)"
- [(set_attr "length" "2")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "2")])
(define_insn "save_interrupt"
[(set (reg:SI 3) (plus:SI (reg:SI 3) (const_int -20)))
(set (mem:SI (plus:SI (reg:SI 3) (const_int -16))) (reg:SI 4))
(set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 1))
(set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 10))
- (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 11))]
+ (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 11))
+ (clobber (reg:CC CC_REGNUM))]
""
{
if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
[(set (attr "length")
(if_then_else (match_test "TARGET_LONG_CALLS")
(const_int 10)
- (const_int 34)))
- (set_attr "cc" "clobber")])
+ (const_int 34)))])
;; Restore r1, r4, r10, and return from the interrupt
(define_insn "return_interrupt"
(set (reg:SI 10) (mem:SI (plus:SI (reg:SI 3) (const_int 12))))
(set (reg:SI 1) (mem:SI (plus:SI (reg:SI 3) (const_int 8))))
(set (reg:SI 4) (mem:SI (plus:SI (reg:SI 3) (const_int 4))))
- (set (reg:SI 30) (mem:SI (reg:SI 3)))]
+ (set (reg:SI 30) (mem:SI (reg:SI 3)))
+ (clobber (reg:CC CC_REGNUM))]
""
{
if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
[(set (attr "length")
(if_then_else (match_test "TARGET_LONG_CALLS")
(const_int 4)
- (const_int 24)))
- (set_attr "cc" "clobber")])
+ (const_int 24)))])
;; Save all registers except for the registers saved in save_interrupt when
;; an interrupt function makes a call.
;; insns this complicated.
(define_insn "callt_save_all_interrupt"
- [(unspec_volatile [(const_int 0)] 0)]
- "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT"
+ [(unspec_volatile [(const_int 0)] 0)
+ (clobber (reg:CC CC_REGNUM))]
+ "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT"
"callt ctoff(__callt_save_all_interrupt)"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
(define_insn "save_all_interrupt"
- [(unspec_volatile [(const_int 0)] 0)]
+ [(unspec_volatile [(const_int 0)] 0)
+ (clobber (reg:CC CC_REGNUM))]
""
{
if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
(if_then_else (match_test "TARGET_LONG_CALLS")
(const_int 4)
(const_int 62)
- ))
- (set_attr "cc" "clobber")])
+ ))])
(define_insn "_save_all_interrupt"
- [(unspec_volatile [(const_int 0)] 0)]
+ [(unspec_volatile [(const_int 0)] 0)
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_V850 && ! TARGET_LONG_CALLS"
"jarl __save_all_interrupt,r10"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
;; Restore all registers saved when an interrupt function makes a call.
;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
;; insns this complicated.
(define_insn "callt_restore_all_interrupt"
- [(unspec_volatile [(const_int 0)] 1)]
- "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT"
+ [(unspec_volatile [(const_int 0)] 1)
+ (clobber (reg:CC CC_REGNUM))]
+ "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT"
"callt ctoff(__callt_restore_all_interrupt)"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
(define_insn "restore_all_interrupt"
- [(unspec_volatile [(const_int 0)] 1)]
+ [(unspec_volatile [(const_int 0)] 1)
+ (clobber (reg:CC CC_REGNUM))]
""
{
if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
(if_then_else (match_test "TARGET_LONG_CALLS")
(const_int 4)
(const_int 62)
- ))
- (set_attr "cc" "clobber")])
+ ))])
(define_insn "_restore_all_interrupt"
- [(unspec_volatile [(const_int 0)] 1)]
+ [(unspec_volatile [(const_int 0)] 1)
+ (clobber (reg:CC CC_REGNUM))]
"TARGET_V850 && ! TARGET_LONG_CALLS"
"jarl __restore_all_interrupt,r10"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
-
-
+ [(set_attr "length" "4")])
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