RISC-V: Support load/store in mov<mode> pattern for RVV modes.

[thirdparty/gcc.git] / gcc / config.gcc

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 52f9e988bf6086b4b9c4b18e3edd2b3118be4b0a..e8fe623c6fe0cafb5d97550d28994cbcd14c8fc5 100644 (file)
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -516,7 +516,7 @@ pru-*-*)
        ;;
 riscv*)
        cpu_type=riscv
-       extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o"
+       extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o"
        extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
        d_target_objs="riscv-d.o"
        extra_headers="riscv_vector.h"