@c man end
@c man begin COPYRIGHT
-Copyright @copyright{} 1988-2017 Free Software Foundation, Inc.
+Copyright @copyright{} 1988-2018 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3 or
-Wno-builtin-declaration-mismatch @gol
-Wno-builtin-macro-redefined -Wc90-c99-compat -Wc99-c11-compat @gol
-Wc++-compat -Wc++11-compat -Wc++14-compat @gol
--Wcast-align -Wcast-align=strict -Wcast-qual @gol
+-Wcast-align -Wcast-align=strict -Wcast-function-type -Wcast-qual @gol
-Wchar-subscripts -Wchkp -Wcatch-value -Wcatch-value=@var{n} @gol
-Wclobbered -Wcomment -Wconditionally-supported @gol
-Wconversion -Wcoverage-mismatch -Wno-cpp -Wdangling-else -Wdate-time @gol
-ggdb -grecord-gcc-switches -gno-record-gcc-switches @gol
-gstabs -gstabs+ -gstrict-dwarf -gno-strict-dwarf @gol
-gcolumn-info -gno-column-info @gol
+-gstatement-frontiers -gno-statement-frontiers @gol
-gvms -gxcoff -gxcoff+ -gz@r{[}=@var{type}@r{]} @gol
-fdebug-prefix-map=@var{old}=@var{new} -fdebug-types-section @gol
-fno-eliminate-unused-debug-types @gol
-fdisable-tree-@var{pass-name}=@var{range-list} @gol
-fdump-noaddr -fdump-unnumbered -fdump-unnumbered-links @gol
-fdump-class-hierarchy@r{[}-@var{n}@r{]} @gol
--fdump-final-insns@r{[}=@var{file}@r{]}
+-fdump-final-insns@r{[}=@var{file}@r{]} @gol
-fdump-ipa-all -fdump-ipa-cgraph -fdump-ipa-inline @gol
-fdump-lang-all @gol
-fdump-lang-@var{switch} @gol
-mlow-precision-recip-sqrt -mlow-precision-sqrt -mlow-precision-div @gol
-mpc-relative-literal-loads @gol
-msign-return-address=@var{scope} @gol
--march=@var{name} -mcpu=@var{name} -mtune=@var{name} -moverride=@var{string}}
+-march=@var{name} -mcpu=@var{name} -mtune=@var{name} @gol
+-moverride=@var{string} -mverbose-cost-dump}
@emph{Adapteva Epiphany Options}
@gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol
-mpic-register=@var{reg} @gol
-mnop-fun-dllimport @gol
-mpoke-function-name @gol
--mthumb -marm @gol
+-mthumb -marm -mflip-thumb @gol
-mtpcs-frame -mtpcs-leaf-frame @gol
-mcaller-super-interworking -mcallee-super-interworking @gol
-mtp=@var{name} -mtls-dialect=@var{dialect} @gol
-mslow-flash-data @gol
-masm-syntax-unified @gol
-mrestrict-it @gol
+-mverbose-cost-dump @gol
-mpure-code @gol
-mcmse}
@emph{RISC-V Options}
@gccoptlist{-mbranch-cost=@var{N-instruction} @gol
--mmemcpy -mno-memcpy @gol
-mplt -mno-plt @gol
-mabi=@var{ABI-string} @gol
-mfdiv -mno-fdiv @gol
-mincoming-stack-boundary=@var{num} @gol
-mcld -mcx16 -msahf -mmovbe -mcrc32 @gol
-mrecip -mrecip=@var{opt} @gol
--mvzeroupper -mprefer-avx128 -mprefer-avx256 @gol
+-mvzeroupper -mprefer-avx128 -mprefer-vector-width=@var{opt} @gol
-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
-mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd -mavx512vl @gol
-mavx512bw -mavx512dq -mavx512ifma -mavx512vbmi -msha -maes @gol
-mprefetchwt1 -mclflushopt -mxsavec -mxsaves @gol
-msse4a -m3dnow -m3dnowa -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop @gol
-mlzcnt -mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mmpx @gol
--mmwaitx -mclzero -mpku -mthreads -mgfni @gol
+-mmwaitx -mclzero -mpku -mthreads -mgfni -mvaes @gol
-mcet -mibt -mshstk -mforce-indirect-call -mavx512vbmi2 @gol
+-mvpclmulqdq -mavx512bitalg -mavx512vpopcntdq @gol
-mms-bitfields -mno-align-stringops -minline-all-stringops @gol
-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol
-mmemcpy-strategy=@var{strategy} -mmemset-strategy=@var{strategy} @gol
interfaces) and L (Analyzability). The name @samp{c1x} is deprecated.
@item c17
+@itemx c18
@itemx iso9899:2017
-ISO C17, the 2017 revision of the ISO C standard. This standard is
+@itemx iso9899:2018
+ISO C17, the 2017 revision of the ISO C standard (expected to be
+published in 2018). This standard is
same as C11 except for corrections of defects (all of which are also
applied with @option{-std=c11}) and a new value of
@code{__STDC_VERSION__}, and so is supported to the same extent as C11.
The name @samp{gnu1x} is deprecated.
@item gnu17
+@itemx gnu18
GNU dialect of ISO C17. This is the default for C code.
@item c++98
in C/C++ and @code{!$omp} in Fortran. Other OpenMP directives
are ignored.
-@item -fcilkplus
-@opindex fcilkplus
-@cindex Enable Cilk Plus
-Enable the usage of Cilk Plus language extension features for C/C++.
-When the option @option{-fcilkplus} is specified, enable the usage of
-the Cilk Plus Language extension features for C/C++. The present
-implementation follows ABI version 1.2. This is an experimental
-feature that is only partially complete, and whose interface may
-change in future versions of GCC as the official specification
-changes. Currently, all features but @code{_Cilk_for} have been
-implemented.
-
@item -fgnu-tm
@opindex fgnu-tm
When the option @option{-fgnu-tm} is specified, the compiler
type changes the mangled name of a symbol relative to C++14. Enabled
by @option{-Wabi} and @option{-Wc++17-compat}.
+As an example:
+
@smallexample
template <class T> void f(T t) @{ t(); @};
void g() noexcept;
-void h() @{ f(g); @} // in C++14 calls f<void(*)()>, in C++17 calls f<void(*)()noexcept>
+void h() @{ f(g); @}
@end smallexample
+@noindent
+In C++14, @code{f} calls calls @code{f<void(*)()>}, but in
+C++17 it calls @code{f<void(*)()noexcept>}.
+
@item -Wclass-memaccess @r{(C++ and Objective-C++ only)}
@opindex Wclass-memaccess
Warn when the destination of a call to a raw memory function such as
violate const-correctness or encapsulation, or corrupt the virtual table.
Modifying the representation of such objects may violate invariants maintained
by member functions of the class. For example, the call to @code{memset}
-below is undefined becase it modifies a non-trivial class object and is,
+below is undefined because it modifies a non-trivial class object and is,
therefore, diagnosed. The safe way to either initialize or clear the storage
of objects of such types is by using the appropriate constructor or assignment
operator, if one is available.
-Wparentheses @gol
-Wpointer-sign @gol
-Wreorder @gol
+-Wrestrict @gol
-Wreturn-type @gol
-Wsequence-point @gol
-Wsign-compare @r{(only in C++)} @gol
name is still supported, but the newer name is more descriptive.)
@gccoptlist{-Wclobbered @gol
+-Wcast-function-type @gol
-Wempty-body @gol
-Wignored-qualifiers @gol
-Wimplicit-fallthrough=3 @gol
@item -Wmaybe-uninitialized
@opindex Wmaybe-uninitialized
@opindex Wno-maybe-uninitialized
-For an automatic variable, if there exists a path from the function
-entry to a use of the variable that is initialized, but there exist
+For an automatic (i.e.@ local) variable, if there exists a path from the
+function entry to a use of the variable that is initialized, but there exist
some other paths for which the variable is not initialized, the compiler
emits a warning if it cannot prove the uninitialized paths are not
-executed at run time. These warnings are made optional because GCC is
-not smart enough to see all the reasons why the code might be correct
-in spite of appearing to have an error. Here is one example of how
-this can happen:
+executed at run time.
+
+These warnings are only possible in optimizing compilation, because otherwise
+GCC does not keep track of the state of variables.
+
+These warnings are made optional because GCC may not be able to determine when
+the code is correct in spite of appearing to have an error. Here is one
+example of how this can happen:
@smallexample
@group
@cindex @code{longjmp} warnings
This option also warns when a non-volatile automatic variable might be
-changed by a call to @code{longjmp}. These warnings as well are possible
-only in optimizing compilation.
-
+changed by a call to @code{longjmp}.
The compiler sees only the calls to @code{setjmp}. It cannot know
where @code{longjmp} will be called; in fact, a signal handler could
call it at any point in the code. As a result, you may get a warning
@}
@end smallexample
+In situations where a character array is intended to store a sequence
+of bytes with no terminating @code{NUL} such an array may be annotated
+with attribute @code{nonstring} to avoid this warning. Such arrays,
+however, are not suitable arguments to functions that expect
+@code{NUL}-terminated strings. To help detect accidental misuses of
+such arrays GCC issues warnings unless it can prove that the use is
+safe. @xref{Common Variable Attributes}.
+
@item -Wsuggest-attribute=@r{[}pure@r{|}const@r{|}noreturn@r{|}format@r{|}cold@r{|}malloc@r{]}
@opindex Wsuggest-attribute=
@opindex Wno-suggest-attribute=
target is increased. For example, warn if a @code{char *} is cast to
an @code{int *} regardless of the target machine.
+@item -Wcast-function-type
+@opindex Wcast-function-type
+@opindex Wno-cast-function-type
+Warn when a function pointer is cast to an incompatible function pointer.
+In a cast involving function types with a variable argument list only
+the types of initial arguments that are provided are considered.
+Any parameter of pointer-type matches any other pointer-type. Any benign
+differences in integral types are ignored, like @code{int} vs. @code{long}
+on ILP32 targets. Likewise type qualifiers are ignored. The function
+type @code{void (*) (void)} is special and matches everything, which can
+be used to suppress this warning.
+In a cast involving pointer to member types this warning warns whenever
+the type cast is changing the pointer to member type.
+This warning is enabled by @option{-Wextra}.
+
@item -Wwrite-strings
@opindex Wwrite-strings
@opindex Wno-write-strings
Warn if anything is declared more than once in the same scope, even in
cases where multiple declaration is valid and changes nothing.
-@item -Wrestrict
+@item -Wno-restrict
@opindex Wrestrict
@opindex Wno-restrict
-Warn when an argument passed to a restrict-qualified parameter
-aliases with another argument.
+Warn when an object referenced by a @code{restrict}-qualified parameter
+(or, in C++, a @code{__restrict}-qualified parameter) is aliased by another
+argument, or when copies between such objects overlap. For example,
+the call to the @code{strcpy} function below attempts to truncate the string
+by replacing its initial characters with the last four. However, because
+the call writes the terminating NUL into @code{a[4]}, the copies overlap and
+the call is diagnosed.
+
+@smallexample
+struct foo
+@{
+ char a[] = "abcd1234";
+ strcpy (a, a + 4);
+@};
+@end smallexample
+The @option{-Wrestrict} is included in @option{-Wall}.
@item -Wnested-externs @r{(C and Objective-C only)}
@opindex Wnested-externs
than just file and line.
This option is enabled by default.
+@item -gstatement-frontiers
+@item -gno-statement-frontiers
+@opindex gstatement-frontiers
+@opindex gno-statement-frontiers
+This option causes GCC to create markers in the internal representation
+at the beginning of statements, and to keep them roughly in place
+throughout compilation, using them to guide the output of @code{is_stmt}
+markers in the line number table. This is enabled by default when
+compiling with optimization (@option{-Os}, @option{-O}, @option{-O2},
+@dots{}), and outputting DWARF 2 debug information at the normal level.
+
@item -gz@r{[}=@var{type}@r{]}
@opindex gz
Produce compressed debug sections in DWARF format, if that is supported.
-ftree-loop-vectorize @gol
-ftree-loop-distribution @gol
-ftree-loop-distribute-patterns @gol
+-floop-interchange @gol
-fsplit-paths @gol
-ftree-slp-vectorize @gol
-fvect-cost-model @gol
at @option{-O} and higher.
@item -ftree-loop-linear
-@itemx -floop-interchange
@itemx -floop-strip-mine
@itemx -floop-block
-@itemx -floop-unroll-and-jam
@opindex ftree-loop-linear
-@opindex floop-interchange
@opindex floop-strip-mine
@opindex floop-block
-@opindex floop-unroll-and-jam
Perform loop nest optimizations. Same as
@option{-floop-nest-optimize}. To use this code transformation, GCC has
to be configured with @option{--with-isl} to enable the Graphite loop
@end smallexample
and the initialization loop is transformed into a call to memset zero.
+@item -floop-interchange
+@opindex floop-interchange
+Perform loop interchange outside of graphite. This flag can improve cache
+performance on loop nest and allow further loop optimizations, like
+vectorization, to take place. For example, the loop
+@smallexample
+for (int i = 0; i < N; i++)
+ for (int j = 0; j < N; j++)
+ for (int k = 0; k < N; k++)
+ c[i][j] = c[i][j] + a[i][k]*b[k][j];
+@end smallexample
+is transformed to
+@smallexample
+for (int i = 0; i < N; i++)
+ for (int k = 0; k < N; k++)
+ for (int j = 0; j < N; j++)
+ c[i][j] = c[i][j] + a[i][k]*b[k][j];
+@end smallexample
+
@item -ftree-loop-im
@opindex ftree-loop-im
Perform loop invariant motion on trees. This pass moves only invariants that
Move branches with loop invariant conditions out of the loop, with duplicates
of the loop on both branches (modified according to result of the condition).
+@item -floop-unroll-and-jam
+@opindex floop-unroll-and-jam
+Apply unroll and jam transformations on feasible loops. In a loop
+nest this unrolls the outer loop by some factor and fuses the resulting
+multiple inner loops.
+
@item -ffunction-sections
@itemx -fdata-sections
@opindex ffunction-sections
@item l2-cache-size
The size of L2 cache, in kilobytes.
+@item loop-interchange-max-num-stmts
+The maximum number of stmts in a loop to be interchanged.
+
+@item loop-interchange-stride-ratio
+The minimum ratio between stride of two loops for interchange to be profitable.
+
@item min-insn-to-prefetch-ratio
The minimum ratio between the number of instructions and the
number of prefetches to enable prefetching in a loop.
enable the compiler to find more complex debug expressions, but compile
time and memory use may grow. The default is 12.
+@item max-debug-marker-count
+Sets a threshold on the number of debug markers (e.g. begin stmt
+markers) to avoid complexity explosion at inlining or expanding to RTL.
+If a function has more such gimple stmts than the set limit, such stmts
+will be dropped from the inlined copy of a function, and from its RTL
+expansion. The default is 100000.
+
@item min-nondebug-insn-uid
Use uids starting at this parameter for nondebug insns. The range below
the parameter is reserved exclusively for debug insns created by
Schedule type of omp schedule for loops parallelized by parloops (static,
dynamic, guided, auto, runtime). The default is static.
+@item parloops-min-per-thread
+The minimum number of iterations per thread of an innermost parallelized
+loop for which the parallelized variant is prefered over the single threaded
+one. The default is 100. Note that for a parallelized loop nest the
+minimum number of iterations of the outermost loop per thread is two.
+
@item max-ssa-name-query-depth
Maximum depth of recursion when querying properties of SSA names in things
like fold routines. One level of recursion corresponds to following a
@item max-vrp-switch-assertions
The maximum number of assertions to add along the default edge of a switch
statement during VRP. The default is 10.
+
+@item unroll-jam-min-percent
+The minimum percentage of memory references that must be optimized
+away for the unroll-and-jam transformation to be considered profitable.
+
+@item unroll-jam-max-unroll
+The maximum number of times the outer loop should be unrolled by
+the unroll-and-jam transformation.
@end table
@end table
See @uref{https://github.com/google/kasan/wiki} for more details.
The option cannot be combined with @option{-fcheck-pointer-bounds}.
+@item -fsanitize=pointer-compare
+@opindex fsanitize=pointer-compare
+Instrument comparison operation (<, <=, >, >=) with pointer operands.
+The option must be combined with either @option{-fsanitize=kernel-address} or
+@option{-fsanitize=address}
+The option cannot be combined with @option{-fsanitize=thread}
+and/or @option{-fcheck-pointer-bounds}.
+Note: By default the check is disabled at run time. To enable it,
+add @code{detect_invalid_pointer_pairs=1} to the environment variable
+@env{ASAN_OPTIONS}.
+
+@item -fsanitize=pointer-subtract
+@opindex fsanitize=pointer-subtract
+Instrument subtraction with pointer operands.
+The option must be combined with either @option{-fsanitize=kernel-address} or
+@option{-fsanitize=address}
+The option cannot be combined with @option{-fsanitize=thread}
+and/or @option{-fcheck-pointer-bounds}.
+Note: By default the check is disabled at run time. To enable it,
+add @code{detect_invalid_pointer_pairs=1} to the environment variable
+@env{ASAN_OPTIONS}.
+
@item -fsanitize=thread
@opindex fsanitize=thread
Enable ThreadSanitizer, a fast data race detector.
@item -dp
@opindex dp
Annotate the assembler output with a comment indicating which
-pattern and alternative is used. The length of each instruction is
+pattern and alternative is used. The length and cost of each instruction are
also printed.
@item -dP
This option is only intended to be useful when developing GCC.
+@item -mverbose-cost-dump
+@opindex mverbose-cost-dump
+Enable verbose cost model dumping in the debug dump files. This option is
+provided for use in debugging the compiler.
+
@item -mpc-relative-literal-loads
@itemx -mno-pc-relative-literal-loads
@opindex mpc-relative-literal-loads
optimizers then assume that indexed stores exist, which is not
the case.
+@item -mlra
@opindex mlra
Enable Local Register Allocation. This is still experimental for ARC,
so by default the compiler uses standard reload
@samp{iwmmxt} and @samp{iwmmxt2}.
Additionally, the following architectures, which lack support for the
-Thumb exection state, are recognized but support is deprecated:
+Thumb execution state, are recognized but support is deprecated:
@samp{armv2}, @samp{armv2a}, @samp{armv3}, @samp{armv3m},
@samp{armv4}, @samp{armv5} and @samp{armv5e}.
Most extension names are generically named, but have an effect that is
dependent upon the architecture to which it is applied. For example,
the @samp{+simd} option can be applied to both @samp{armv7-a} and
-@samp{armv8-a} architectures, but will enable the original ARMv7
-Advanced SIMD (Neon) extensions for @samp{armv7-a} and the ARMv8-a
+@samp{armv8-a} architectures, but will enable the original ARMv7-A
+Advanced SIMD (Neon) extensions for @samp{armv7-a} and the ARMv8-A
variant for @samp{armv8-a}.
The table below lists the supported extensions for each architecture.
@item +crc
The Cyclic Redundancy Check (CRC) instructions.
@item +simd
-The ARMv8 Advanced SIMD and floating-point instructions.
+The ARMv8-A Advanced SIMD and floating-point instructions.
@item +crypto
The cryptographic instructions.
@item +nocrypto
-Disable the cryptographic isntructions.
+Disable the cryptographic instructions.
@item +nofp
Disable the floating-point, Advanced SIMD and cryptographic instructions.
@end table
@item armv8.1-a
@table @samp
@item +simd
-The ARMv8.1 Advanced SIMD and floating-point instructions.
+The ARMv8.1-A Advanced SIMD and floating-point instructions.
@item +crypto
The cryptographic instructions. This also enables the Advanced SIMD and
floating-point instructions.
@item +nocrypto
-Disable the cryptographic isntructions.
+Disable the cryptographic instructions.
@item +nofp
Disable the floating-point, Advanced SIMD and cryptographic instructions.
@end table
@item armv8.2-a
+@itemx armv8.3-a
@table @samp
@item +fp16
The half-precision floating-point data processing instructions.
This also enables the Advanced SIMD and floating-point instructions.
@item +simd
-The ARMv8.1 Advanced SIMD and floating-point instructions.
+The ARMv8.1-A Advanced SIMD and floating-point instructions.
@item +crypto
The cryptographic instructions. This also enables the Advanced SIMD and
@item +fp.sp
The single-precision FPv5 floating-point instructions.
@item +simd
-The ARMv8 Advanced SIMD and floating-point instructions.
+The ARMv8-A Advanced SIMD and floating-point instructions.
@item +crypto
The cryptographic instructions.
@item +nocrypto
-Disable the cryptographic isntructions.
+Disable the cryptographic instructions.
@item +nofp
Disable the floating-point, Advanced SIMD and cryptographic instructions.
@end table
by using the @code{target("thumb")} and @code{target("arm")} function attributes
(@pxref{ARM Function Attributes}) or pragmas (@pxref{Function Specific Option Pragmas}).
+@item -mflip-thumb
+@opindex mflip-thumb
+Switch ARM/Thumb modes on alternating functions.
+This option is provided for regression testing of mixed Thumb/ARM code
+generation, and is not intended for ordinary use in compiling code.
+
@item -mtpcs-frame
@opindex mtpcs-frame
Generate a stack frame that is compliant with the Thumb Procedure Call
@item -mrestrict-it
@opindex mrestrict-it
-Restricts generation of IT blocks to conform to the rules of ARMv8.
+Restricts generation of IT blocks to conform to the rules of ARMv8-A.
IT blocks can only contain a single 16-bit instruction from a select
-set of instructions. This option is on by default for ARMv8 Thumb mode.
+set of instructions. This option is on by default for ARMv8-A Thumb mode.
@item -mprint-tune-info
@opindex mprint-tune-info
intended for ordinary use in compiling code. This option is disabled
by default.
+@item -mverbose-cost-dump
+@opindex mverbose-cost-dump
+Enable verbose cost model dumping in the debug dump files. This option is
+provided for use in debugging the compiler.
+
@item -mpure-code
@opindex mpure-code
Do not allow constant data to be placed in code sections.
@opindex mbranch-cost
Set the cost of branches to roughly @var{n} instructions.
-@item -mmemcpy
-@itemx -mno-memcpy
-@opindex mmemcpy
-Don't optimize block moves.
-
@item -mplt
@itemx -mno-plt
@opindex plt
-When generating PIC code, allow the use of PLTs. Ignored for non-PIC.
+When generating PIC code, do or don't allow the use of PLTs. Ignored for
+non-PIC. The default is @option{-mplt}.
-@item -mabi=@var{ABI-string}
-@opindex mabi
@item -mabi=@var{ABI-string}
@opindex mabi
Specify integer and floating-point calling convention. @var{ABI-string}
@item -mfdiv
@itemx -mno-fdiv
@opindex mfdiv
-Use hardware floating-point divide and square root instructions. This requires
-the F or D extensions for floating-point registers.
+Do or don't use hardware floating-point divide and square root instructions.
+This requires the F or D extensions for floating-point registers. The default
+is to use them if the specified architecture has these instructions.
@item -mdiv
@itemx -mno-div
@opindex mdiv
-Use hardware instructions for integer division. This requires the M extension.
+Do or don't use hardware instructions for integer division. This requires the
+M extension. The default is to use them if the specified architecture has
+these instructions.
@item -march=@var{ISA-string}
@opindex march
@item -msave-restore
@itemx -mno-save-restore
@opindex msave-restore
-Use smaller but slower prologue and epilogue code.
+Do or don't use smaller but slower prologue and epilogue code that uses
+library function calls. The default is to use fast inline prologues and
+epilogues.
@item -mstrict-align
@itemx -mno-strict-align
@opindex mstrict-align
-Do not generate unaligned memory accesses.
+Do not or do generate unaligned memory accesses. The default is set depending
+on whether the processor we are optimizing for supports fast unaligned access
+or not.
@item -mcmodel=medlow
@opindex mcmodel=medlow
defined symbols must be within any single 2 GiB address range. Programs can be
statically or dynamically linked.
+@item -mexplicit-relocs
+@itemx -mno-exlicit-relocs
+Use or do not use assembler relocation operators when dealing with symbolic
+addresses. The alternative is to use assembler macros instead, which may
+limit optimization.
+
@end table
@node RL78 Options
BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
+@item cannonlake
+Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
+SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
+AVX512IFMA, SHA, CLWB and UMIP instruction set support.
+
@item k6
AMD K6 CPU with MMX instruction set support.
@need 200
@itemx -mgfni
@opindex mgfni
+@need 200
+@itemx -mvaes
+@opindex mvaes
+@need 200
+@itemx -mvpclmulqdq
+@opindex mvpclmulqdq
+@need 200
+@itemx -mavx512bitalg
+@opindex mavx512bitalg
+@need 200
+@itemx -mavx512vpopcntdq
+@opindex mavx512vpopcntdq
These switches enable the use of instructions in the MMX, SSE,
SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD,
SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM,
-AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, BMI, BMI2,
+AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, BMI, BMI2, VAES,
FXSR, XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU, IBT, SHSTK, AVX512VBMI2,
-GFNI, 3DNow!@: or enhanced 3DNow!@: extended instruction sets. Each has a
-corresponding @option{-mno-} option to disable use of these instructions.
+GFNI, VPCLMULQDQ, AVX512BITALG, AVX512VPOPCNTDQ3DNow!@: or enhanced 3DNow!@:
+extended instruction sets.
+Each has a corresponding @option{-mno-} option to disable use of these
+instructions.
These extensions are also available as built-in functions: see
@ref{x86 Built-in Functions}, for details of the functions enabled and
This option instructs GCC to use 128-bit AVX instructions instead of
256-bit AVX instructions in the auto-vectorizer.
-@item -mprefer-avx256
-@opindex mprefer-avx256
-This option instructs GCC to use 256-bit AVX instructions instead of
-512-bit AVX instructions in the auto-vectorizer.
+@item -mprefer-vector-width=@var{opt}
+@opindex mprefer-vector-width
+This option instructs GCC to use @var{opt}-bit vector width in instructions
+instead of default on the selected platform.
+
+@table @samp
+@item none
+No extra limitations applied to GCC other than defined by the selected platform.
+
+@item 128
+Prefer 128-bit vector width for instructions.
+
+@item 256
+Prefer 256-bit vector width for instructions.
+
+@item 512
+Prefer 512-bit vector width for instructions.
+@end table
@item -mcx16
@opindex mcx16
projects / thirdparty / gcc.git / blobdiff