-@c Copyright (C) 1988-2018 Free Software Foundation, Inc.
+@c Copyright (C) 1988-2019 Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.
@c man end
@c man begin COPYRIGHT
-Copyright @copyright{} 1988-2018 Free Software Foundation, Inc.
+Copyright @copyright{} 1988-2019 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3 or
@xref{Warning Options,,Options to Request or Suppress Warnings}.
@gccoptlist{-fsyntax-only -fmax-errors=@var{n} -Wpedantic @gol
-pedantic-errors @gol
--w -Wextra -Wall -Waddress -Waggregate-return -Waligned-new @gol
+-w -Wextra -Wall -Waddress -Waddress-of-packed-member @gol
+-Waggregate-return -Waligned-new @gol
-Walloc-zero -Walloc-size-larger-than=@var{byte-size} @gol
-Walloca -Walloca-larger-than=@var{byte-size} @gol
-Wno-aggressive-loop-optimizations -Warray-bounds -Warray-bounds=@var{n} @gol
-Wformat-y2k -Wframe-address @gol
-Wframe-larger-than=@var{byte-size} -Wno-free-nonheap-object @gol
-Wjump-misses-init @gol
--Wif-not-aligned @gol
+-Whsa -Wif-not-aligned @gol
-Wignored-qualifiers -Wignored-attributes -Wincompatible-pointer-types @gol
-Wimplicit -Wimplicit-fallthrough -Wimplicit-fallthrough=@var{n} @gol
-Wimplicit-function-declaration -Wimplicit-int @gol
-Wuseless-cast -Wvariadic-macros -Wvector-operation-performance @gol
-Wvla -Wvla-larger-than=@var{byte-size} -Wvolatile-register-var @gol
-Wwrite-strings @gol
--Wzero-as-null-pointer-constant -Whsa}
+-Wzero-as-null-pointer-constant}
@item C and Objective-C-only Warning Options
@gccoptlist{-Wbad-function-cast -Wmissing-declarations @gol
-mlow-precision-recip-sqrt -mlow-precision-sqrt -mlow-precision-div @gol
-mpc-relative-literal-loads @gol
-msign-return-address=@var{scope} @gol
+-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}] @gol
-march=@var{name} -mcpu=@var{name} -mtune=@var{name} @gol
-moverride=@var{string} -mverbose-cost-dump -mtrack-speculation}
-msse4a -m3dnow -m3dnowa -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop @gol
-mlzcnt -mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp @gol
-mmwaitx -mclzero -mpku -mthreads -mgfni -mvaes -mwaitpkg @gol
--mshstk -mforce-indirect-call -mavx512vbmi2 @gol
+-mshstk -mmanual-endbr -mforce-indirect-call -mavx512vbmi2 @gol
-mvpclmulqdq -mavx512bitalg -mmovdiri -mmovdir64b -mavx512vpopcntdq @gol
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops @gol
-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol
programmer intended to use @code{strcmp}. This warning is enabled by
@option{-Wall}.
+@item -Waddress-of-packed-member
+@opindex Waddress-of-packed-member
+@opindex Wno-address-of-packed-member
+Warn when the address of packed member of struct or union is taken,
+which usually results in an unaligned pointer value. This is
+enabled by default.
+
@item -Wlogical-op
@opindex Wlogical-op
@opindex Wno-logical-op
-ftree-partial-pre @gol
-ftree-slp-vectorize @gol
-funswitch-loops @gol
--fvect-cost-model}
+-fvect-cost-model @gol
+-fversion-loops-for-strides}
@item -O0
@opindex O0
It also enables @option{-finline-functions}, causes the compiler to tune for
code size rather than execution speed, and performs further optimizations
-designed to reduce code size.
+designed to reduce code size.
@item -Ofast
@opindex Ofast
declared @code{static}, then the function is normally not output as
assembler code in its own right.
-Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}. Also enabled
+Enabled at levels @option{-O3}, @option{-Os}. Also enabled
by @option{-fprofile-use} and @option{-fauto-profile}.
@item -finline-functions-called-once
D(I) = E(I) * F
ENDDO
@end smallexample
+This flag is enabled by default at @option{-O3}.
+It is also enabled by @option{-fprofile-use} and @option{-fauto-profile}.
@item -ftree-loop-distribute-patterns
@opindex ftree-loop-distribute-patterns
ENDDO
@end smallexample
and the initialization loop is transformed into a call to memset zero.
+This flag is enabled by default at @option{-O3}.
+It is also enabled by @option{-fprofile-use} and @option{-fauto-profile}.
@item -floop-interchange
@opindex floop-interchange
c[i][j] = c[i][j] + a[i][k]*b[k][j];
@end smallexample
This flag is enabled by default at @option{-O3}.
+It is also enabled by @option{-fprofile-use} and @option{-fauto-profile}.
@item -floop-unroll-and-jam
@opindex floop-unroll-and-jam
Apply unroll and jam transformations on feasible loops. In a loop
nest this unrolls the outer loop by some factor and fuses the resulting
multiple inner loops. This flag is enabled by default at @option{-O3}.
+It is also enabled by @option{-fprofile-use} and @option{-fauto-profile}.
@item -ftree-loop-im
@opindex ftree-loop-im
Enabled by @option{-fprofile-use} and @option{-fauto-profile}.
+@item -fversion-loops-for-strides
+@opindex fversion-loops-for-strides
+If a loop iterates over an array with a variable stride, create another
+version of the loop that assumes the stride is always one. For example:
+
+@smallexample
+for (int i = 0; i < n; ++i)
+ x[i * stride] = @dots{};
+@end smallexample
+
+becomes:
+
+@smallexample
+if (stride == 1)
+ for (int i = 0; i < n; ++i)
+ x[i] = @dots{};
+else
+ for (int i = 0; i < n; ++i)
+ x[i * stride] = @dots{};
+@end smallexample
+
+This is particularly useful for assumed-shape arrays in Fortran where
+(for example) it allows better vectorization assuming contiguous accesses.
+This flag is enabled by default at @option{-O3}.
+It is also enabled by @option{-fprofile-use} and @option{-fauto-profile}.
+
@item -ffunction-sections
@itemx -fdata-sections
@opindex ffunction-sections
(more restrictive) limit compared to functions declared inline can
be applied.
+@item max-inline-insns-small
+This is bound applied to calls which are considered relevant with
+@option{-finline-small-functions}.
+
+@item max-inline-insns-size
+This is bound applied to calls which are optimized for size. Small growth
+may be desirable to anticipate optimization oppurtunities exposed by inlining.
+
+@item uninlined-function-insns
+Number of instructions accounted by inliner for function overhead such as
+function prologue and epilogue.
+
+@item uninlined-function-time
+Extra time accounted by inliner for function overhead such as time needed to
+execute function prologue and epilogue
+
+@item uninlined-thunk-insns
+@item uninlined-thunk-time
+Same as @option{--param uninlined-function-insns} and
+@option{--param uninlined-function-time} but applied to function thunks
+
@item inline-min-speedup
When estimated performance improvement of caller + callee runtime exceeds this
threshold (in percent), the function can be inlined regardless of the limit on
Number of lookahead cycles the model looks into; at '
' only enable instruction sorting heuristic.
+@item loop-versioning-max-inner-insns
+The maximum number of instructions that an inner loop can have
+before the loop versioning pass considers it too big to copy.
+
+@item loop-versioning-max-outer-insns
+The maximum number of instructions that an outer loop can have
+before the loop versioning pass considers it too big to copy,
+discounting any instructions in inner loops that directly benefit
+from versioning.
@end table
@end table
During the incremental link (by @option{-r}) the linker plugin will default to
@option{rel}. With current interfaces to GNU Binutils it is however not
possible to link incrementally LTO objects and non-LTO objects into a single
-mixed object file. In the case any of object files in incremental link can not
+mixed object file. In the case any of object files in incremental link cannot
be used for link-time optimization the linker plugin will output warning and
use @samp{nolto-rel}. To maintain the whole program optimization it is
recommended to link such objects into static library instead. Alternatively it
@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}.
The permissible values for @var{arch} are @samp{armv8-a},
-@samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a} or @samp{armv8.4-a}
-or @var{native}.
+@samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a}, @samp{armv8.4-a},
+@samp{armv8.5-a} or @var{native}.
+
+The value @samp{armv8.5-a} implies @samp{armv8.4-a} and enables compiler
+support for the ARMv8.5-A architecture extensions.
The value @samp{armv8.4-a} implies @samp{armv8.3-a} and enables compiler
support for the ARMv8.4-A architecture extensions.
@samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
@samp{cortex-a76}, @samp{ares}, @samp{exynos-m1}, @samp{emag}, @samp{falkor},
@samp{qdf24xx}, @samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan},
+@samp{octeontx}, @samp{octeontx81}, @samp{octeontx83},
@samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},
@samp{tsv110}, @samp{thunderxt83}, @samp{thunderx2t99},
@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
Permissible values are @samp{none}, which disables return address signing,
@samp{non-leaf}, which enables pointer signing for functions which are not leaf
functions, and @samp{all}, which enables pointer signing for all functions. The
-default value is @samp{none}.
+default value is @samp{none}. This option has been deprecated by
+-mbranch-protection.
+
+@item -mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}]
+@opindex mbranch-protection
+Select the branch protection features to use.
+@samp{none} is the default and turns off all types of branch protection.
+@samp{standard} turns on all types of branch protection features. If a feature
+has additional tuning options, then @samp{standard} sets it to its standard
+level.
+@samp{pac-ret[+@var{leaf}]} turns on return address signing to its standard
+level: signing functions that save the return address to memory (non-leaf
+functions will practically always do this) using the a-key. The optional
+argument @samp{leaf} can be used to extend the signing to include leaf
+functions.
+@samp{bti} turns on branch target identification mechanism.
@item -msve-vector-bits=@var{bits}
@opindex msve-vector-bits
GCC supports two forms of SVE code generation: ``vector-length
agnostic'' output that works with any size of vector register and
-``vector-length specific'' output that only works when the vector
-registers are a particular size. Replacing @var{bits} with
-@samp{scalable} selects vector-length agnostic output while
-replacing it with a number selects vector-length specific output.
-The possible lengths in the latter case are: 128, 256, 512, 1024
-and 2048. @samp{scalable} is the default.
-
-At present, @samp{-msve-vector-bits=128} produces the same output
-as @samp{-msve-vector-bits=scalable}.
-
+``vector-length specific'' output that allows GCC to make assumptions
+about the vector length when it is useful for optimization reasons.
+The possible values of @samp{bits} are: @samp{scalable}, @samp{128},
+@samp{256}, @samp{512}, @samp{1024} and @samp{2048}.
+Specifying @samp{scalable} selects vector-length agnostic
+output. At present @samp{-msve-vector-bits=128} also generates vector-length
+agnostic output. All other values generate vector-length specific code.
+The behavior of these values may change in future releases and no value except
+@samp{scalable} should be relied on for producing code that is portable across
+different hardware SVE vector lengths.
+
+The default is @samp{-msve-vector-bits=scalable}, which produces
+vector-length agnostic code.
@end table
@subsubsection @option{-march} and @option{-mcpu} Feature Modifiers
@item profile
Enable the Statistical Profiling extension. This option is only to enable the
extension at the assembler level and does not affect code generation.
+@item rng
+Enable the Armv8.5-a Random Number instructions. This option is only to
+enable the extension at the assembler level and does not affect code
+generation.
+@item memtag
+Enable the Armv8.5-a Memory Tagging Extensions. This option is only to
+enable the extension at the assembler level and does not affect code
+generation.
+@item sb
+Enable the Armv8-a Speculation Barrier instruction. This option is only to
+enable the extension at the assembler level and does not affect code
+generation. This option is enabled by default for @option{-march=armv8.5-a}.
+@item ssbs
+Enable the Armv8-a Speculative Store Bypass Safe instruction. This option
+is only to enable the extension at the assembler level and does not affect code
+generation. This option is enabled by default for @option{-march=armv8.5-a}.
+@item predres
+Enable the Armv8-a Execution and Data Prediction Restriction instructions.
+This option is only to enable the extension at the assembler level and does
+not affect code generation. This option is enabled by default for
+@option{-march=armv8.5-a}.
@end table
@item -mfixed-range=@var{register-range}
@opindex mfixed-range
Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator can not use. This is
+A fixed register is one that the register allocator cannot use. This is
useful when compiling kernel code. A register range is specified as
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction
set support.
+@item cascadelake
+Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support.
+
@item k6
AMD K6 CPU with MMX instruction set support.
when using Intel Processor Trace where it generates more precise timing
information for function calls.
+@item -mmanual-endbr
+@opindex mmanual-endbr
+Insert ENDBR instruction at function entry only via the @code{cf_check}
+function attribute. This is useful when used with the option
+@option{-fcf-protection=branch} to control ENDBR insertion at the
+function entry.
+
@item -mcall-ms2sysv-xlogues
@opindex mcall-ms2sysv-xlogues
@opindex mno-call-ms2sysv-xlogues
not be reachable in the large code model.
Note that @option{-mindirect-branch=thunk-extern} is incompatible with
-@option{-fcf-protection=branch} since the external thunk can not be modified
+@option{-fcf-protection=branch} since the external thunk cannot be modified
to disable control-flow check.
@item -mfunction-return=@var{choice}
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