-@c Copyright (C) 1988-2018 Free Software Foundation, Inc.
+@c Copyright (C) 1988-2019 Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.
-mlow-precision-recip-sqrt -mlow-precision-sqrt -mlow-precision-div @gol
-mpc-relative-literal-loads @gol
-msign-return-address=@var{scope} @gol
+-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}] @gol
-march=@var{name} -mcpu=@var{name} -mtune=@var{name} @gol
-moverride=@var{string} -mverbose-cost-dump -mtrack-speculation}
It also enables @option{-finline-functions}, causes the compiler to tune for
code size rather than execution speed, and performs further optimizations
-designed to reduce code size.
+designed to reduce code size.
@item -Ofast
@opindex Ofast
declared @code{static}, then the function is normally not output as
assembler code in its own right.
-Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}. Also enabled
+Enabled at levels @option{-O3}, @option{-Os}. Also enabled
by @option{-fprofile-use} and @option{-fauto-profile}.
@item -finline-functions-called-once
D(I) = E(I) * F
ENDDO
@end smallexample
+This flag is enabled by default at @option{-O3}.
+It is also enabled by @option{-fprofile-use} and @option{-fauto-profile}.
@item -ftree-loop-distribute-patterns
@opindex ftree-loop-distribute-patterns
ENDDO
@end smallexample
and the initialization loop is transformed into a call to memset zero.
+This flag is enabled by default at @option{-O3}.
+It is also enabled by @option{-fprofile-use} and @option{-fauto-profile}.
@item -floop-interchange
@opindex floop-interchange
c[i][j] = c[i][j] + a[i][k]*b[k][j];
@end smallexample
This flag is enabled by default at @option{-O3}.
+It is also enabled by @option{-fprofile-use} and @option{-fauto-profile}.
@item -floop-unroll-and-jam
@opindex floop-unroll-and-jam
Apply unroll and jam transformations on feasible loops. In a loop
nest this unrolls the outer loop by some factor and fuses the resulting
multiple inner loops. This flag is enabled by default at @option{-O3}.
+It is also enabled by @option{-fprofile-use} and @option{-fauto-profile}.
@item -ftree-loop-im
@opindex ftree-loop-im
This is particularly useful for assumed-shape arrays in Fortran where
(for example) it allows better vectorization assuming contiguous accesses.
+This flag is enabled by default at @option{-O3}.
+It is also enabled by @option{-fprofile-use} and @option{-fauto-profile}.
@item -ffunction-sections
@itemx -fdata-sections
(more restrictive) limit compared to functions declared inline can
be applied.
+@item max-inline-insns-small
+This is bound applied to calls which are considered relevant with
+@option{-finline-small-functions}.
+
+@item max-inline-insns-size
+This is bound applied to calls which are optimized for size. Small growth
+may be desirable to anticipate optimization oppurtunities exposed by inlining.
+
+@item uninlined-function-insns
+Number of instructions accounted by inliner for function overhead such as
+function prologue and epilogue.
+
+@item uninlined-function-time
+Extra time accounted by inliner for function overhead such as time needed to
+execute function prologue and epilogue
+
+@item uninlined-thunk-insns
+@item uninlined-thunk-time
+Same as @option{--param uninlined-function-insns} and
+@option{--param uninlined-function-time} but applied to function thunks
+
@item inline-min-speedup
When estimated performance improvement of caller + callee runtime exceeds this
threshold (in percent), the function can be inlined regardless of the limit on
During the incremental link (by @option{-r}) the linker plugin will default to
@option{rel}. With current interfaces to GNU Binutils it is however not
possible to link incrementally LTO objects and non-LTO objects into a single
-mixed object file. In the case any of object files in incremental link can not
+mixed object file. In the case any of object files in incremental link cannot
be used for link-time optimization the linker plugin will output warning and
use @samp{nolto-rel}. To maintain the whole program optimization it is
recommended to link such objects into static library instead. Alternatively it
@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}.
The permissible values for @var{arch} are @samp{armv8-a},
-@samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a} or @samp{armv8.4-a}
-or @var{native}.
+@samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a}, @samp{armv8.4-a},
+@samp{armv8.5-a} or @var{native}.
+
+The value @samp{armv8.5-a} implies @samp{armv8.4-a} and enables compiler
+support for the ARMv8.5-A architecture extensions.
The value @samp{armv8.4-a} implies @samp{armv8.3-a} and enables compiler
support for the ARMv8.4-A architecture extensions.
Permissible values are @samp{none}, which disables return address signing,
@samp{non-leaf}, which enables pointer signing for functions which are not leaf
functions, and @samp{all}, which enables pointer signing for all functions. The
-default value is @samp{none}.
+default value is @samp{none}. This option has been deprecated by
+-mbranch-protection.
+
+@item -mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}]
+@opindex mbranch-protection
+Select the branch protection features to use.
+@samp{none} is the default and turns off all types of branch protection.
+@samp{standard} turns on all types of branch protection features. If a feature
+has additional tuning options, then @samp{standard} sets it to its standard
+level.
+@samp{pac-ret[+@var{leaf}]} turns on return address signing to its standard
+level: signing functions that save the return address to memory (non-leaf
+functions will practically always do this) using the a-key. The optional
+argument @samp{leaf} can be used to extend the signing to include leaf
+functions.
+@samp{bti} turns on branch target identification mechanism.
@item -msve-vector-bits=@var{bits}
@opindex msve-vector-bits
@item profile
Enable the Statistical Profiling extension. This option is only to enable the
extension at the assembler level and does not affect code generation.
+@item rng
+Enable the Armv8.5-a Random Number instructions. This option is only to
+enable the extension at the assembler level and does not affect code
+generation.
+@item memtag
+Enable the Armv8.5-a Memory Tagging Extensions. This option is only to
+enable the extension at the assembler level and does not affect code
+generation.
+@item sb
+Enable the Armv8-a Speculation Barrier instruction. This option is only to
+enable the extension at the assembler level and does not affect code
+generation. This option is enabled by default for @option{-march=armv8.5-a}.
+@item ssbs
+Enable the Armv8-a Speculative Store Bypass Safe instruction. This option
+is only to enable the extension at the assembler level and does not affect code
+generation. This option is enabled by default for @option{-march=armv8.5-a}.
+@item predres
+Enable the Armv8-a Execution and Data Prediction Restriction instructions.
+This option is only to enable the extension at the assembler level and does
+not affect code generation. This option is enabled by default for
+@option{-march=armv8.5-a}.
@end table
@item -mfixed-range=@var{register-range}
@opindex mfixed-range
Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator can not use. This is
+A fixed register is one that the register allocator cannot use. This is
useful when compiling kernel code. A register range is specified as
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
not be reachable in the large code model.
Note that @option{-mindirect-branch=thunk-extern} is incompatible with
-@option{-fcf-protection=branch} since the external thunk can not be modified
+@option{-fcf-protection=branch} since the external thunk cannot be modified
to disable control-flow check.
@item -mfunction-return=@var{choice}
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