/* Code to analyze doloop loops in order for targets to perform late
optimizations converting doloops to other forms of hardware loops.
- Copyright (C) 2011-2014 Free Software Foundation, Inc.
+ Copyright (C) 2011-2020 Free Software Foundation, Inc.
This file is part of GCC.
#include "config.h"
#include "system.h"
#include "coretypes.h"
-#include "tm.h"
+#include "backend.h"
#include "rtl.h"
-#include "flags.h"
-#include "expr.h"
-#include "hard-reg-set.h"
-#include "regs.h"
-#include "basic-block.h"
-#include "tm_p.h"
#include "df.h"
-#include "cfgloop.h"
+#include "insn-config.h"
+#include "regs.h"
+#include "memmodel.h"
+#include "emit-rtl.h"
#include "recog.h"
-#include "target.h"
+#include "cfgrtl.h"
#include "hw-doloop.h"
#include "dumpfile.h"
-#ifdef HAVE_doloop_end
-
/* Dump information collected in LOOPS. */
static void
dump_hwloops (hwloop_info loops)
for (ix = 0; loop->blocks.iterate (ix, &bb); ix++)
{
- rtx insn;
+ rtx_insn *insn;
edge e;
edge_iterator ei;
insn != NEXT_INSN (BB_END (bb));
insn = NEXT_INSN (insn))
{
- df_ref *def_rec;
+ df_ref def;
HARD_REG_SET set_this_insn;
if (!NONDEBUG_INSN_P (insn))
loop->has_asm = true;
CLEAR_HARD_REG_SET (set_this_insn);
- for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)
+ FOR_EACH_INSN_DEF (def, insn)
{
- rtx dreg = DF_REF_REG (*def_rec);
+ rtx dreg = DF_REF_REG (def);
if (!REG_P (dreg))
continue;
CLEAR_HARD_REG_BIT (set_this_insn, REGNO (loop->iter_reg));
else if (reg_mentioned_p (loop->iter_reg, PATTERN (insn)))
loop->iter_reg_used = true;
- IOR_HARD_REG_SET (loop->regs_set_in_loop, set_this_insn);
+ loop->regs_set_in_loop |= set_this_insn;
}
}
}
the expected use; targets that call into this code usually replace the
loop counter with a different special register. */
static void
-discover_loop (hwloop_info loop, basic_block tail_bb, rtx tail_insn, rtx reg)
+discover_loop (hwloop_info loop, basic_block tail_bb, rtx_insn *tail_insn, rtx reg)
{
bool found_tail;
unsigned dwork = 0;
loop->loop_end = tail_insn;
loop->iter_reg = reg;
vec_alloc (loop->incoming, 2);
- loop->start_label = JUMP_LABEL (tail_insn);
+ loop->start_label = as_a <rtx_insn *> (JUMP_LABEL (tail_insn));
if (EDGE_COUNT (tail_bb->succs) != 2)
{
structure and add the head block to the work list. */
FOR_EACH_BB_FN (bb, cfun)
{
- rtx tail = BB_END (bb);
- rtx insn, reg;
+ rtx_insn *tail = BB_END (bb);
+ rtx_insn *insn;
+ rtx reg;
while (tail && NOTE_P (tail) && tail != BB_HEAD (bb))
tail = PREV_INSN (tail);
/* There's a degenerate case we can handle - an empty loop consisting
of only a back branch. Handle that by deleting the branch. */
- insn = JUMP_LABEL (tail);
+ insn = JUMP_LABEL_AS_INSN (tail);
while (insn && !NONDEBUG_INSN_P (insn))
insn = NEXT_INSN (insn);
if (insn == tail)
inner_depth = inner->depth;
/* The set of registers may be changed while optimizing the inner
loop. */
- IOR_HARD_REG_SET (loop->regs_set_in_loop, inner->regs_set_in_loop);
+ loop->regs_set_in_loop |= inner->regs_set_in_loop;
}
loop->depth = inner_depth + 1;
/* We can't enter cfglayout mode anymore if basic block partitioning
already happened. */
- if (do_reorder && !flag_reorder_blocks_and_partition)
+ if (do_reorder && !crtl->has_bb_partition)
{
reorder_loops (loops);
free_loops (loops);
if (dump_file)
print_rtl (dump_file, get_insns ());
}
-#endif