/* RTL simplification functions for GNU compiler.
- Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
- 2011, 2012 Free Software Foundation, Inc.
+ Copyright (C) 1987-2013 Free Software Foundation, Inc.
This file is part of GCC.
#include "tm.h"
#include "rtl.h"
#include "tree.h"
+#include "varasm.h"
#include "tm_p.h"
#include "regs.h"
#include "hard-reg-set.h"
if (width <= HOST_BITS_PER_WIDE_INT
&& CONST_INT_P (x))
val = INTVAL (x);
+#if TARGET_SUPPORTS_WIDE_INT
+ else if (CONST_WIDE_INT_P (x))
+ {
+ unsigned int i;
+ unsigned int elts = CONST_WIDE_INT_NUNITS (x);
+ if (elts != (width + HOST_BITS_PER_WIDE_INT - 1) / HOST_BITS_PER_WIDE_INT)
+ return false;
+ for (i = 0; i < elts - 1; i++)
+ if (CONST_WIDE_INT_ELT (x, i) != 0)
+ return false;
+ val = CONST_WIDE_INT_ELT (x, elts - 1);
+ width %= HOST_BITS_PER_WIDE_INT;
+ if (width == 0)
+ width = HOST_BITS_PER_WIDE_INT;
+ }
+#else
else if (width <= HOST_BITS_PER_DOUBLE_INT
&& CONST_DOUBLE_AS_INT_P (x)
&& CONST_DOUBLE_LOW (x) == 0)
val = CONST_DOUBLE_HIGH (x);
width -= HOST_BITS_PER_WIDE_INT;
}
+#endif
else
- /* FIXME: We don't yet have a representation for wider modes. */
+ /* X is not an integer constant. */
return false;
if (width < HOST_BITS_PER_WIDE_INT)
/* If we're accessing the constant in a different mode than it was
originally stored, attempt to fix that up via subreg simplifications.
If that fails we have no choice but to return the original memory. */
- if (offset != 0 || cmode != GET_MODE (x))
+ if ((offset != 0 || cmode != GET_MODE (x))
+ && offset >= 0 && offset < GET_MODE_SIZE (cmode))
{
rtx tem = simplify_subreg (GET_MODE (x), c, cmode, offset);
if (tem && CONSTANT_P (tem))
&mode, &unsignedp, &volatilep, false);
if (bitsize != GET_MODE_BITSIZE (mode)
|| (bitpos % BITS_PER_UNIT)
- || (toffset && !host_integerp (toffset, 0)))
+ || (toffset && !tree_fits_shwi_p (toffset)))
decl = NULL;
else
{
offset += bitpos / BITS_PER_UNIT;
if (toffset)
- offset += TREE_INT_CST_LOW (toffset);
+ offset += tree_to_shwi (toffset);
}
break;
}
return simplify_replace_fn_rtx (x, old_rtx, 0, new_rtx);
}
\f
+/* Try to simplify a MODE truncation of OP, which has OP_MODE.
+ Only handle cases where the truncated value is inherently an rvalue.
+
+ RTL provides two ways of truncating a value:
+
+ 1. a lowpart subreg. This form is only a truncation when both
+ the outer and inner modes (here MODE and OP_MODE respectively)
+ are scalar integers, and only then when the subreg is used as
+ an rvalue.
+
+ It is only valid to form such truncating subregs if the
+ truncation requires no action by the target. The onus for
+ proving this is on the creator of the subreg -- e.g. the
+ caller to simplify_subreg or simplify_gen_subreg -- and typically
+ involves either TRULY_NOOP_TRUNCATION_MODES_P or truncated_to_mode.
+
+ 2. a TRUNCATE. This form handles both scalar and compound integers.
+
+ The first form is preferred where valid. However, the TRUNCATE
+ handling in simplify_unary_operation turns the second form into the
+ first form when TRULY_NOOP_TRUNCATION_MODES_P or truncated_to_mode allow,
+ so it is generally safe to form rvalue truncations using:
+
+ simplify_gen_unary (TRUNCATE, ...)
+
+ and leave simplify_unary_operation to work out which representation
+ should be used.
+
+ Because of the proof requirements on (1), simplify_truncation must
+ also use simplify_gen_unary (TRUNCATE, ...) to truncate parts of OP,
+ regardless of whether the outer truncation came from a SUBREG or a
+ TRUNCATE. For example, if the caller has proven that an SImode
+ truncation of:
+
+ (and:DI X Y)
+
+ is a no-op and can be represented as a subreg, it does not follow
+ that SImode truncations of X and Y are also no-ops. On a target
+ like 64-bit MIPS that requires SImode values to be stored in
+ sign-extended form, an SImode truncation of:
+
+ (and:DI (reg:DI X) (const_int 63))
+
+ is trivially a no-op because only the lower 6 bits can be set.
+ However, X is still an arbitrary 64-bit number and so we cannot
+ assume that truncating it too is a no-op. */
+
+static rtx
+simplify_truncation (enum machine_mode mode, rtx op,
+ enum machine_mode op_mode)
+{
+ unsigned int precision = GET_MODE_UNIT_PRECISION (mode);
+ unsigned int op_precision = GET_MODE_UNIT_PRECISION (op_mode);
+ gcc_assert (precision <= op_precision);
+
+ /* Optimize truncations of zero and sign extended values. */
+ if (GET_CODE (op) == ZERO_EXTEND
+ || GET_CODE (op) == SIGN_EXTEND)
+ {
+ /* There are three possibilities. If MODE is the same as the
+ origmode, we can omit both the extension and the subreg.
+ If MODE is not larger than the origmode, we can apply the
+ truncation without the extension. Finally, if the outermode
+ is larger than the origmode, we can just extend to the appropriate
+ mode. */
+ enum machine_mode origmode = GET_MODE (XEXP (op, 0));
+ if (mode == origmode)
+ return XEXP (op, 0);
+ else if (precision <= GET_MODE_UNIT_PRECISION (origmode))
+ return simplify_gen_unary (TRUNCATE, mode,
+ XEXP (op, 0), origmode);
+ else
+ return simplify_gen_unary (GET_CODE (op), mode,
+ XEXP (op, 0), origmode);
+ }
+
+ /* Simplify (truncate:SI (op:DI (x:DI) (y:DI)))
+ to (op:SI (truncate:SI (x:DI)) (truncate:SI (x:DI))). */
+ if (GET_CODE (op) == PLUS
+ || GET_CODE (op) == MINUS
+ || GET_CODE (op) == MULT)
+ {
+ rtx op0 = simplify_gen_unary (TRUNCATE, mode, XEXP (op, 0), op_mode);
+ if (op0)
+ {
+ rtx op1 = simplify_gen_unary (TRUNCATE, mode, XEXP (op, 1), op_mode);
+ if (op1)
+ return simplify_gen_binary (GET_CODE (op), mode, op0, op1);
+ }
+ }
+
+ /* Simplify (truncate:QI (lshiftrt:SI (sign_extend:SI (x:QI)) C)) into
+ to (ashiftrt:QI (x:QI) C), where C is a suitable small constant and
+ the outer subreg is effectively a truncation to the original mode. */
+ if ((GET_CODE (op) == LSHIFTRT
+ || GET_CODE (op) == ASHIFTRT)
+ /* Ensure that OP_MODE is at least twice as wide as MODE
+ to avoid the possibility that an outer LSHIFTRT shifts by more
+ than the sign extension's sign_bit_copies and introduces zeros
+ into the high bits of the result. */
+ && 2 * precision <= op_precision
+ && CONST_INT_P (XEXP (op, 1))
+ && GET_CODE (XEXP (op, 0)) == SIGN_EXTEND
+ && GET_MODE (XEXP (XEXP (op, 0), 0)) == mode
+ && UINTVAL (XEXP (op, 1)) < precision)
+ return simplify_gen_binary (ASHIFTRT, mode,
+ XEXP (XEXP (op, 0), 0), XEXP (op, 1));
+
+ /* Likewise (truncate:QI (lshiftrt:SI (zero_extend:SI (x:QI)) C)) into
+ to (lshiftrt:QI (x:QI) C), where C is a suitable small constant and
+ the outer subreg is effectively a truncation to the original mode. */
+ if ((GET_CODE (op) == LSHIFTRT
+ || GET_CODE (op) == ASHIFTRT)
+ && CONST_INT_P (XEXP (op, 1))
+ && GET_CODE (XEXP (op, 0)) == ZERO_EXTEND
+ && GET_MODE (XEXP (XEXP (op, 0), 0)) == mode
+ && UINTVAL (XEXP (op, 1)) < precision)
+ return simplify_gen_binary (LSHIFTRT, mode,
+ XEXP (XEXP (op, 0), 0), XEXP (op, 1));
+
+ /* Likewise (truncate:QI (ashift:SI (zero_extend:SI (x:QI)) C)) into
+ to (ashift:QI (x:QI) C), where C is a suitable small constant and
+ the outer subreg is effectively a truncation to the original mode. */
+ if (GET_CODE (op) == ASHIFT
+ && CONST_INT_P (XEXP (op, 1))
+ && (GET_CODE (XEXP (op, 0)) == ZERO_EXTEND
+ || GET_CODE (XEXP (op, 0)) == SIGN_EXTEND)
+ && GET_MODE (XEXP (XEXP (op, 0), 0)) == mode
+ && UINTVAL (XEXP (op, 1)) < precision)
+ return simplify_gen_binary (ASHIFT, mode,
+ XEXP (XEXP (op, 0), 0), XEXP (op, 1));
+
+ /* Recognize a word extraction from a multi-word subreg. */
+ if ((GET_CODE (op) == LSHIFTRT
+ || GET_CODE (op) == ASHIFTRT)
+ && SCALAR_INT_MODE_P (mode)
+ && SCALAR_INT_MODE_P (op_mode)
+ && precision >= BITS_PER_WORD
+ && 2 * precision <= op_precision
+ && CONST_INT_P (XEXP (op, 1))
+ && (INTVAL (XEXP (op, 1)) & (precision - 1)) == 0
+ && UINTVAL (XEXP (op, 1)) < op_precision)
+ {
+ int byte = subreg_lowpart_offset (mode, op_mode);
+ int shifted_bytes = INTVAL (XEXP (op, 1)) / BITS_PER_UNIT;
+ return simplify_gen_subreg (mode, XEXP (op, 0), op_mode,
+ (WORDS_BIG_ENDIAN
+ ? byte - shifted_bytes
+ : byte + shifted_bytes));
+ }
+
+ /* If we have a TRUNCATE of a right shift of MEM, make a new MEM
+ and try replacing the TRUNCATE and shift with it. Don't do this
+ if the MEM has a mode-dependent address. */
+ if ((GET_CODE (op) == LSHIFTRT
+ || GET_CODE (op) == ASHIFTRT)
+ && SCALAR_INT_MODE_P (op_mode)
+ && MEM_P (XEXP (op, 0))
+ && CONST_INT_P (XEXP (op, 1))
+ && (INTVAL (XEXP (op, 1)) % GET_MODE_BITSIZE (mode)) == 0
+ && INTVAL (XEXP (op, 1)) > 0
+ && INTVAL (XEXP (op, 1)) < GET_MODE_BITSIZE (op_mode)
+ && ! mode_dependent_address_p (XEXP (XEXP (op, 0), 0),
+ MEM_ADDR_SPACE (XEXP (op, 0)))
+ && ! MEM_VOLATILE_P (XEXP (op, 0))
+ && (GET_MODE_SIZE (mode) >= UNITS_PER_WORD
+ || WORDS_BIG_ENDIAN == BYTES_BIG_ENDIAN))
+ {
+ int byte = subreg_lowpart_offset (mode, op_mode);
+ int shifted_bytes = INTVAL (XEXP (op, 1)) / BITS_PER_UNIT;
+ return adjust_address_nv (XEXP (op, 0), mode,
+ (WORDS_BIG_ENDIAN
+ ? byte - shifted_bytes
+ : byte + shifted_bytes));
+ }
+
+ /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
+ (OP:SI foo:SI) if OP is NEG or ABS. */
+ if ((GET_CODE (op) == ABS
+ || GET_CODE (op) == NEG)
+ && (GET_CODE (XEXP (op, 0)) == SIGN_EXTEND
+ || GET_CODE (XEXP (op, 0)) == ZERO_EXTEND)
+ && GET_MODE (XEXP (XEXP (op, 0), 0)) == mode)
+ return simplify_gen_unary (GET_CODE (op), mode,
+ XEXP (XEXP (op, 0), 0), mode);
+
+ /* (truncate:A (subreg:B (truncate:C X) 0)) is
+ (truncate:A X). */
+ if (GET_CODE (op) == SUBREG
+ && SCALAR_INT_MODE_P (mode)
+ && SCALAR_INT_MODE_P (op_mode)
+ && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op)))
+ && GET_CODE (SUBREG_REG (op)) == TRUNCATE
+ && subreg_lowpart_p (op))
+ {
+ rtx inner = XEXP (SUBREG_REG (op), 0);
+ if (GET_MODE_PRECISION (mode)
+ <= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op))))
+ return simplify_gen_unary (TRUNCATE, mode, inner, GET_MODE (inner));
+ else
+ /* If subreg above is paradoxical and C is narrower
+ than A, return (subreg:A (truncate:C X) 0). */
+ return simplify_gen_subreg (mode, SUBREG_REG (op),
+ GET_MODE (SUBREG_REG (op)), 0);
+ }
+
+ /* (truncate:A (truncate:B X)) is (truncate:A X). */
+ if (GET_CODE (op) == TRUNCATE)
+ return simplify_gen_unary (TRUNCATE, mode, XEXP (op, 0),
+ GET_MODE (XEXP (op, 0)));
+
+ return NULL_RTX;
+}
+\f
/* Try to simplify a unary operation CODE whose output mode is to be
MODE with input operand OP whose mode was originally OP_MODE.
Return zero if no simplification can be made. */
/* Similarly, (not (neg X)) is (plus X -1). */
if (GET_CODE (op) == NEG)
- return plus_constant (mode, XEXP (op, 0), -1);
+ return simplify_gen_binary (PLUS, mode, XEXP (op, 0),
+ CONSTM1_RTX (mode));
/* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
if (GET_CODE (op) == XOR
/* (not (ashiftrt foo C)) where C is the number of bits in FOO
minus 1 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1,
so we can perform the above simplification. */
-
if (STORE_FLAG_VALUE == -1
&& GET_CODE (op) == ASHIFTRT
&& GET_CODE (XEXP (op, 1))
simplify_gen_unary (NOT, inner_mode, const1_rtx,
inner_mode),
XEXP (SUBREG_REG (op), 1));
- return rtl_hooks.gen_lowpart_no_emit (mode, x);
+ temp = rtl_hooks.gen_lowpart_no_emit (mode, x);
+ if (temp)
+ return temp;
}
/* Apply De Morgan's laws to reduce number of patterns for machines
with negating logical insns (and-not, nand, etc.). If result has
only one NOT, put it first, since that is how the patterns are
coded. */
-
if (GET_CODE (op) == IOR || GET_CODE (op) == AND)
{
rtx in1 = XEXP (op, 0), in2 = XEXP (op, 1);
return gen_rtx_fmt_ee (GET_CODE (op) == IOR ? AND : IOR,
mode, in1, in2);
}
+
+ /* (not (bswap x)) -> (bswap (not x)). */
+ if (GET_CODE (op) == BSWAP)
+ {
+ rtx x = simplify_gen_unary (NOT, mode, XEXP (op, 0), mode);
+ return simplify_gen_unary (BSWAP, mode, x, mode);
+ }
break;
case NEG:
/* Similarly, (neg (not X)) is (plus X 1). */
if (GET_CODE (op) == NOT)
- return plus_constant (mode, XEXP (op, 0), 1);
+ return simplify_gen_binary (PLUS, mode, XEXP (op, 0),
+ CONST1_RTX (mode));
/* (neg (minus X Y)) can become (minus Y X). This transformation
isn't safe for modes with signed zeros, since if X and Y are
&& !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
{
/* (neg (plus A C)) is simplified to (minus -C A). */
- if (CONST_INT_P (XEXP (op, 1))
- || CONST_DOUBLE_P (XEXP (op, 1)))
+ if (CONST_SCALAR_INT_P (XEXP (op, 1))
+ || CONST_DOUBLE_AS_FLOAT_P (XEXP (op, 1)))
{
temp = simplify_unary_operation (NEG, mode, XEXP (op, 1), mode);
if (temp)
break;
case TRUNCATE:
- /* We can't handle truncation to a partial integer mode here
- because we don't know the real bitsize of the partial
- integer mode. */
- if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
- break;
-
- /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
- if ((GET_CODE (op) == SIGN_EXTEND
- || GET_CODE (op) == ZERO_EXTEND)
- && GET_MODE (XEXP (op, 0)) == mode)
- return XEXP (op, 0);
+ /* Don't optimize (lshiftrt (mult ...)) as it would interfere
+ with the umulXi3_highpart patterns. */
+ if (GET_CODE (op) == LSHIFTRT
+ && GET_CODE (XEXP (op, 0)) == MULT)
+ break;
- /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
- (OP:SI foo:SI) if OP is NEG or ABS. */
- if ((GET_CODE (op) == ABS
- || GET_CODE (op) == NEG)
- && (GET_CODE (XEXP (op, 0)) == SIGN_EXTEND
- || GET_CODE (XEXP (op, 0)) == ZERO_EXTEND)
- && GET_MODE (XEXP (XEXP (op, 0), 0)) == mode)
- return simplify_gen_unary (GET_CODE (op), mode,
- XEXP (XEXP (op, 0), 0), mode);
+ if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
+ {
+ if (TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (op)))
+ {
+ temp = rtl_hooks.gen_lowpart_no_emit (mode, op);
+ if (temp)
+ return temp;
+ }
+ /* We can't handle truncation to a partial integer mode here
+ because we don't know the real bitsize of the partial
+ integer mode. */
+ break;
+ }
- /* (truncate:A (subreg:B (truncate:C X) 0)) is
- (truncate:A X). */
- if (GET_CODE (op) == SUBREG
- && GET_CODE (SUBREG_REG (op)) == TRUNCATE
- && subreg_lowpart_p (op))
- return simplify_gen_unary (TRUNCATE, mode, XEXP (SUBREG_REG (op), 0),
- GET_MODE (XEXP (SUBREG_REG (op), 0)));
+ if (GET_MODE (op) != VOIDmode)
+ {
+ temp = simplify_truncation (mode, op, GET_MODE (op));
+ if (temp)
+ return temp;
+ }
/* If we know that the value is already truncated, we can
- replace the TRUNCATE with a SUBREG. Note that this is also
- valid if TRULY_NOOP_TRUNCATION is false for the corresponding
- modes we just have to apply a different definition for
- truncation. But don't do this for an (LSHIFTRT (MULT ...))
- since this will cause problems with the umulXi3_highpart
- patterns. */
- if ((TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (op))
- ? (num_sign_bit_copies (op, GET_MODE (op))
- > (unsigned int) (GET_MODE_PRECISION (GET_MODE (op))
- - GET_MODE_PRECISION (mode)))
- : truncated_to_mode (mode, op))
- && ! (GET_CODE (op) == LSHIFTRT
- && GET_CODE (XEXP (op, 0)) == MULT))
- return rtl_hooks.gen_lowpart_no_emit (mode, op);
+ replace the TRUNCATE with a SUBREG. */
+ if (GET_MODE_NUNITS (mode) == 1
+ && (TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (op))
+ || truncated_to_mode (mode, op)))
+ {
+ temp = rtl_hooks.gen_lowpart_no_emit (mode, op);
+ if (temp)
+ return temp;
+ }
/* A truncate of a comparison can be replaced with a subreg if
STORE_FLAG_VALUE permits. This is like the previous test,
if (HWI_COMPUTABLE_MODE_P (mode)
&& COMPARISON_P (op)
&& (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
- return rtl_hooks.gen_lowpart_no_emit (mode, op);
+ {
+ temp = rtl_hooks.gen_lowpart_no_emit (mode, op);
+ if (temp)
+ return temp;
+ }
/* A truncate of a memory is just loading the low part of the memory
if we are not changing the meaning of the address. */
&& !VECTOR_MODE_P (mode)
&& !MEM_VOLATILE_P (op)
&& !mode_dependent_address_p (XEXP (op, 0), MEM_ADDR_SPACE (op)))
- return rtl_hooks.gen_lowpart_no_emit (mode, op);
+ {
+ temp = rtl_hooks.gen_lowpart_no_emit (mode, op);
+ if (temp)
+ return temp;
+ }
break;
&& SUBREG_PROMOTED_VAR_P (op)
&& ! SUBREG_PROMOTED_UNSIGNED_P (op)
&& GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
- return rtl_hooks.gen_lowpart_no_emit (mode, op);
+ {
+ temp = rtl_hooks.gen_lowpart_no_emit (mode, op);
+ if (temp)
+ return temp;
+ }
/* (sign_extend:M (sign_extend:N <X>)) is (sign_extend:M <X>).
(sign_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
{
rtx inner =
rtl_hooks.gen_lowpart_no_emit (tmode, XEXP (XEXP (op, 0), 0));
- return simplify_gen_unary (GET_CODE (op) == ASHIFTRT
- ? SIGN_EXTEND : ZERO_EXTEND,
- mode, inner, tmode);
+ if (inner)
+ return simplify_gen_unary (GET_CODE (op) == ASHIFTRT
+ ? SIGN_EXTEND : ZERO_EXTEND,
+ mode, inner, tmode);
}
}
&& SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_PROMOTED_UNSIGNED_P (op) > 0
&& GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
- return rtl_hooks.gen_lowpart_no_emit (mode, op);
+ {
+ temp = rtl_hooks.gen_lowpart_no_emit (mode, op);
+ if (temp)
+ return temp;
+ }
/* Extending a widening multiplication should be canonicalized to
a wider widening multiplication. */
{
rtx inner =
rtl_hooks.gen_lowpart_no_emit (tmode, XEXP (XEXP (op, 0), 0));
- return simplify_gen_unary (ZERO_EXTEND, mode, inner, tmode);
+ if (inner)
+ return simplify_gen_unary (ZERO_EXTEND, mode, inner, tmode);
}
}
+ /* (zero_extend:M (subreg:N <X:O>)) is <X:O> (for M == O) or
+ (zero_extend:M <X:O>), if X doesn't have any non-zero bits outside
+ of mode N. E.g.
+ (zero_extend:SI (subreg:QI (and:SI (reg:SI) (const_int 63)) 0)) is
+ (and:SI (reg:SI) (const_int 63)). */
+ if (GET_CODE (op) == SUBREG
+ && GET_MODE_PRECISION (GET_MODE (op))
+ < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op)))
+ && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op)))
+ <= HOST_BITS_PER_WIDE_INT
+ && GET_MODE_PRECISION (mode)
+ >= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op)))
+ && subreg_lowpart_p (op)
+ && (nonzero_bits (SUBREG_REG (op), GET_MODE (SUBREG_REG (op)))
+ & ~GET_MODE_MASK (GET_MODE (op))) == 0)
+ {
+ if (GET_MODE_PRECISION (mode)
+ == GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op))))
+ return SUBREG_REG (op);
+ return simplify_gen_unary (ZERO_EXTEND, mode, SUBREG_REG (op),
+ GET_MODE (SUBREG_REG (op)));
+ }
+
#if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
/* As we do not know which address space the pointer is referring to,
we can do this only if the target does not support different pointer
rtx op, enum machine_mode op_mode)
{
unsigned int width = GET_MODE_PRECISION (mode);
- unsigned int op_width = GET_MODE_PRECISION (op_mode);
if (code == VEC_DUPLICATE)
{
gcc_assert (GET_MODE_INNER (mode) == GET_MODE_INNER
(GET_MODE (op)));
}
- if (CONST_INT_P (op) || CONST_DOUBLE_P (op)
+ if (CONST_SCALAR_INT_P (op) || CONST_DOUBLE_AS_FLOAT_P (op)
|| GET_CODE (op) == CONST_VECTOR)
{
int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
check the wrong mode (input vs. output) for a conversion operation,
such as FIX. At some point, this should be simplified. */
- if (code == FLOAT && (CONST_DOUBLE_AS_INT_P (op) || CONST_INT_P (op)))
+ if (code == FLOAT && CONST_SCALAR_INT_P (op))
{
- HOST_WIDE_INT hv, lv;
REAL_VALUE_TYPE d;
- if (CONST_INT_P (op))
- lv = INTVAL (op), hv = HWI_SIGN_EXTEND (lv);
- else
- lv = CONST_DOUBLE_LOW (op), hv = CONST_DOUBLE_HIGH (op);
+ if (op_mode == VOIDmode)
+ {
+ /* CONST_INT have VOIDmode as the mode. We assume that all
+ the bits of the constant are significant, though, this is
+ a dangerous assumption as many times CONST_INTs are
+ created and used with garbage in the bits outside of the
+ precision of the implied mode of the const_int. */
+ op_mode = MAX_MODE_INT;
+ }
- REAL_VALUE_FROM_INT (d, lv, hv, mode);
+ real_from_integer (&d, mode, std::make_pair (op, op_mode), SIGNED);
d = real_value_truncate (mode, d);
return CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
}
- else if (code == UNSIGNED_FLOAT
- && (CONST_DOUBLE_AS_INT_P (op) || CONST_INT_P (op)))
+ else if (code == UNSIGNED_FLOAT && CONST_SCALAR_INT_P (op))
{
- HOST_WIDE_INT hv, lv;
REAL_VALUE_TYPE d;
- if (CONST_INT_P (op))
- lv = INTVAL (op), hv = HWI_SIGN_EXTEND (lv);
- else
- lv = CONST_DOUBLE_LOW (op), hv = CONST_DOUBLE_HIGH (op);
-
- if (op_mode == VOIDmode
- || GET_MODE_PRECISION (op_mode) > HOST_BITS_PER_DOUBLE_INT)
- /* We should never get a negative number. */
- gcc_assert (hv >= 0);
- else if (GET_MODE_PRECISION (op_mode) <= HOST_BITS_PER_WIDE_INT)
- hv = 0, lv &= GET_MODE_MASK (op_mode);
+ if (op_mode == VOIDmode)
+ {
+ /* CONST_INT have VOIDmode as the mode. We assume that all
+ the bits of the constant are significant, though, this is
+ a dangerous assumption as many times CONST_INTs are
+ created and used with garbage in the bits outside of the
+ precision of the implied mode of the const_int. */
+ op_mode = MAX_MODE_INT;
+ }
- REAL_VALUE_FROM_UNSIGNED_INT (d, lv, hv, mode);
+ real_from_integer (&d, mode, std::make_pair (op, op_mode), UNSIGNED);
d = real_value_truncate (mode, d);
return CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
}
- if (CONST_INT_P (op)
- && width <= HOST_BITS_PER_WIDE_INT && width > 0)
+ if (CONST_SCALAR_INT_P (op) && width > 0)
{
- HOST_WIDE_INT arg0 = INTVAL (op);
- HOST_WIDE_INT val;
+ wide_int result;
+ enum machine_mode imode = op_mode == VOIDmode ? mode : op_mode;
+ rtx_mode_t op0 = std::make_pair (op, imode);
+
+#if TARGET_SUPPORTS_WIDE_INT == 0
+ /* This assert keeps the simplification from producing a result
+ that cannot be represented in a CONST_DOUBLE but a lot of
+ upstream callers expect that this function never fails to
+ simplify something and so you if you added this to the test
+ above the code would die later anyway. If this assert
+ happens, you just need to make the port support wide int. */
+ gcc_assert (width <= HOST_BITS_PER_DOUBLE_INT);
+#endif
switch (code)
{
case NOT:
- val = ~ arg0;
+ result = wi::bit_not (op0);
break;
case NEG:
- val = - arg0;
+ result = wi::neg (op0);
break;
case ABS:
- val = (arg0 >= 0 ? arg0 : - arg0);
+ result = wi::abs (op0);
break;
case FFS:
- arg0 &= GET_MODE_MASK (mode);
- val = ffs_hwi (arg0);
+ result = wi::shwi (wi::ffs (op0), mode);
break;
case CLZ:
- arg0 &= GET_MODE_MASK (mode);
- if (arg0 == 0 && CLZ_DEFINED_VALUE_AT_ZERO (mode, val))
- ;
- else
- val = GET_MODE_PRECISION (mode) - floor_log2 (arg0) - 1;
+ result = wi::shwi (wi::clz (op0), mode);
break;
case CLRSB:
- arg0 &= GET_MODE_MASK (mode);
- if (arg0 == 0)
- val = GET_MODE_PRECISION (mode) - 1;
- else if (arg0 >= 0)
- val = GET_MODE_PRECISION (mode) - floor_log2 (arg0) - 2;
- else if (arg0 < 0)
- val = GET_MODE_PRECISION (mode) - floor_log2 (~arg0) - 2;
- break;
-
- case CTZ:
- arg0 &= GET_MODE_MASK (mode);
- if (arg0 == 0)
- {
- /* Even if the value at zero is undefined, we have to come
- up with some replacement. Seems good enough. */
- if (! CTZ_DEFINED_VALUE_AT_ZERO (mode, val))
- val = GET_MODE_PRECISION (mode);
- }
- else
- val = ctz_hwi (arg0);
- break;
-
- case POPCOUNT:
- arg0 &= GET_MODE_MASK (mode);
- val = 0;
- while (arg0)
- val++, arg0 &= arg0 - 1;
- break;
-
- case PARITY:
- arg0 &= GET_MODE_MASK (mode);
- val = 0;
- while (arg0)
- val++, arg0 &= arg0 - 1;
- val &= 1;
- break;
-
- case BSWAP:
- {
- unsigned int s;
-
- val = 0;
- for (s = 0; s < width; s += 8)
- {
- unsigned int d = width - s - 8;
- unsigned HOST_WIDE_INT byte;
- byte = (arg0 >> s) & 0xff;
- val |= byte << d;
- }
- }
- break;
-
- case TRUNCATE:
- val = arg0;
- break;
-
- case ZERO_EXTEND:
- /* When zero-extending a CONST_INT, we need to know its
- original mode. */
- gcc_assert (op_mode != VOIDmode);
- if (op_width == HOST_BITS_PER_WIDE_INT)
- {
- /* If we were really extending the mode,
- we would have to distinguish between zero-extension
- and sign-extension. */
- gcc_assert (width == op_width);
- val = arg0;
- }
- else if (GET_MODE_BITSIZE (op_mode) < HOST_BITS_PER_WIDE_INT)
- val = arg0 & GET_MODE_MASK (op_mode);
- else
- return 0;
- break;
-
- case SIGN_EXTEND:
- if (op_mode == VOIDmode)
- op_mode = mode;
- op_width = GET_MODE_PRECISION (op_mode);
- if (op_width == HOST_BITS_PER_WIDE_INT)
- {
- /* If we were really extending the mode,
- we would have to distinguish between zero-extension
- and sign-extension. */
- gcc_assert (width == op_width);
- val = arg0;
- }
- else if (op_width < HOST_BITS_PER_WIDE_INT)
- {
- val = arg0 & GET_MODE_MASK (op_mode);
- if (val_signbit_known_set_p (op_mode, val))
- val |= ~GET_MODE_MASK (op_mode);
- }
- else
- return 0;
- break;
-
- case SQRT:
- case FLOAT_EXTEND:
- case FLOAT_TRUNCATE:
- case SS_TRUNCATE:
- case US_TRUNCATE:
- case SS_NEG:
- case US_NEG:
- case SS_ABS:
- return 0;
-
- default:
- gcc_unreachable ();
- }
-
- return gen_int_mode (val, mode);
- }
-
- /* We can do some operations on integer CONST_DOUBLEs. Also allow
- for a DImode operation on a CONST_INT. */
- else if (width <= HOST_BITS_PER_DOUBLE_INT
- && (CONST_DOUBLE_AS_INT_P (op) || CONST_INT_P (op)))
- {
- double_int first, value;
-
- if (CONST_DOUBLE_AS_INT_P (op))
- first = double_int::from_pair (CONST_DOUBLE_HIGH (op),
- CONST_DOUBLE_LOW (op));
- else
- first = double_int::from_shwi (INTVAL (op));
-
- switch (code)
- {
- case NOT:
- value = ~first;
- break;
-
- case NEG:
- value = -first;
- break;
-
- case ABS:
- if (first.is_negative ())
- value = -first;
- else
- value = first;
- break;
-
- case FFS:
- value.high = 0;
- if (first.low != 0)
- value.low = ffs_hwi (first.low);
- else if (first.high != 0)
- value.low = HOST_BITS_PER_WIDE_INT + ffs_hwi (first.high);
- else
- value.low = 0;
- break;
-
- case CLZ:
- value.high = 0;
- if (first.high != 0)
- value.low = GET_MODE_PRECISION (mode) - floor_log2 (first.high) - 1
- - HOST_BITS_PER_WIDE_INT;
- else if (first.low != 0)
- value.low = GET_MODE_PRECISION (mode) - floor_log2 (first.low) - 1;
- else if (! CLZ_DEFINED_VALUE_AT_ZERO (mode, value.low))
- value.low = GET_MODE_PRECISION (mode);
+ result = wi::shwi (wi::clrsb (op0), mode);
break;
case CTZ:
- value.high = 0;
- if (first.low != 0)
- value.low = ctz_hwi (first.low);
- else if (first.high != 0)
- value.low = HOST_BITS_PER_WIDE_INT + ctz_hwi (first.high);
- else if (! CTZ_DEFINED_VALUE_AT_ZERO (mode, value.low))
- value.low = GET_MODE_PRECISION (mode);
+ result = wi::shwi (wi::ctz (op0), mode);
break;
case POPCOUNT:
- value = double_int_zero;
- while (first.low)
- {
- value.low++;
- first.low &= first.low - 1;
- }
- while (first.high)
- {
- value.low++;
- first.high &= first.high - 1;
- }
+ result = wi::shwi (wi::popcount (op0), mode);
break;
case PARITY:
- value = double_int_zero;
- while (first.low)
- {
- value.low++;
- first.low &= first.low - 1;
- }
- while (first.high)
- {
- value.low++;
- first.high &= first.high - 1;
- }
- value.low &= 1;
+ result = wi::shwi (wi::parity (op0), mode);
break;
case BSWAP:
- {
- unsigned int s;
-
- value = double_int_zero;
- for (s = 0; s < width; s += 8)
- {
- unsigned int d = width - s - 8;
- unsigned HOST_WIDE_INT byte;
-
- if (s < HOST_BITS_PER_WIDE_INT)
- byte = (first.low >> s) & 0xff;
- else
- byte = (first.high >> (s - HOST_BITS_PER_WIDE_INT)) & 0xff;
-
- if (d < HOST_BITS_PER_WIDE_INT)
- value.low |= byte << d;
- else
- value.high |= byte << (d - HOST_BITS_PER_WIDE_INT);
- }
- }
+ result = wide_int (op0).bswap ();
break;
case TRUNCATE:
- /* This is just a change-of-mode, so do nothing. */
- value = first;
- break;
-
case ZERO_EXTEND:
- gcc_assert (op_mode != VOIDmode);
-
- if (op_width > HOST_BITS_PER_WIDE_INT)
- return 0;
-
- value = double_int::from_uhwi (first.low & GET_MODE_MASK (op_mode));
+ result = wide_int::from (op0, width, UNSIGNED);
break;
case SIGN_EXTEND:
- if (op_mode == VOIDmode
- || op_width > HOST_BITS_PER_WIDE_INT)
- return 0;
- else
- {
- value.low = first.low & GET_MODE_MASK (op_mode);
- if (val_signbit_known_set_p (op_mode, value.low))
- value.low |= ~GET_MODE_MASK (op_mode);
-
- value.high = HWI_SIGN_EXTEND (value.low);
- }
+ result = wide_int::from (op0, width, SIGNED);
break;
case SQRT:
- return 0;
-
default:
return 0;
}
- return immed_double_int_const (value, mode);
+ return immed_wide_int_const (result, mode);
}
else if (CONST_DOUBLE_AS_FLOAT_P (op)
}
return CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
}
-
else if (CONST_DOUBLE_AS_FLOAT_P (op)
&& SCALAR_FLOAT_MODE_P (GET_MODE (op))
&& GET_MODE_CLASS (mode) == MODE_INT
- && width <= HOST_BITS_PER_DOUBLE_INT && width > 0)
+ && width > 0)
{
/* Although the overflow semantics of RTL's FIX and UNSIGNED_FIX
operators are intentionally left unspecified (to ease implementation
/* This was formerly used only for non-IEEE float.
eggert@twinsun.com says it is safe for IEEE also. */
- HOST_WIDE_INT xh, xl, th, tl;
REAL_VALUE_TYPE x, t;
REAL_VALUE_FROM_CONST_DOUBLE (x, op);
+ wide_int wmax, wmin;
+ /* This is part of the abi to real_to_integer, but we check
+ things before making this call. */
+ bool fail;
+
switch (code)
{
case FIX:
return const0_rtx;
/* Test against the signed upper bound. */
- if (width > HOST_BITS_PER_WIDE_INT)
- {
- th = ((unsigned HOST_WIDE_INT) 1
- << (width - HOST_BITS_PER_WIDE_INT - 1)) - 1;
- tl = -1;
- }
- else
- {
- th = 0;
- tl = ((unsigned HOST_WIDE_INT) 1 << (width - 1)) - 1;
- }
- real_from_integer (&t, VOIDmode, tl, th, 0);
+ wmax = wi::max_value (width, SIGNED);
+ real_from_integer (&t, VOIDmode, wmax, SIGNED);
if (REAL_VALUES_LESS (t, x))
- {
- xh = th;
- xl = tl;
- break;
- }
+ return immed_wide_int_const (wmax, mode);
/* Test against the signed lower bound. */
- if (width > HOST_BITS_PER_WIDE_INT)
- {
- th = (unsigned HOST_WIDE_INT) (-1)
- << (width - HOST_BITS_PER_WIDE_INT - 1);
- tl = 0;
- }
- else
- {
- th = -1;
- tl = (unsigned HOST_WIDE_INT) (-1) << (width - 1);
- }
- real_from_integer (&t, VOIDmode, tl, th, 0);
+ wmin = wi::min_value (width, SIGNED);
+ real_from_integer (&t, VOIDmode, wmin, SIGNED);
if (REAL_VALUES_LESS (x, t))
- {
- xh = th;
- xl = tl;
- break;
- }
- REAL_VALUE_TO_INT (&xl, &xh, x);
+ return immed_wide_int_const (wmin, mode);
+
+ return immed_wide_int_const (real_to_integer (&x, &fail, width), mode);
break;
case UNSIGNED_FIX:
return const0_rtx;
/* Test against the unsigned upper bound. */
- if (width == HOST_BITS_PER_DOUBLE_INT)
- {
- th = -1;
- tl = -1;
- }
- else if (width >= HOST_BITS_PER_WIDE_INT)
- {
- th = ((unsigned HOST_WIDE_INT) 1
- << (width - HOST_BITS_PER_WIDE_INT)) - 1;
- tl = -1;
- }
- else
- {
- th = 0;
- tl = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
- }
- real_from_integer (&t, VOIDmode, tl, th, 1);
+ wmax = wi::max_value (width, UNSIGNED);
+ real_from_integer (&t, VOIDmode, wmax, UNSIGNED);
if (REAL_VALUES_LESS (t, x))
- {
- xh = th;
- xl = tl;
- break;
- }
+ return immed_wide_int_const (wmax, mode);
- REAL_VALUE_TO_INT (&xl, &xh, x);
+ return immed_wide_int_const (real_to_integer (&x, &fail, width),
+ mode);
break;
default:
gcc_unreachable ();
}
- return immed_double_const (xl, xh, mode);
}
return NULL_RTX;
}
\f
+/* Subroutine of simplify_binary_operation to simplify a binary operation
+ CODE that can commute with byte swapping, with result mode MODE and
+ operating on OP0 and OP1. CODE is currently one of AND, IOR or XOR.
+ Return zero if no simplification or canonicalization is possible. */
+
+static rtx
+simplify_byte_swapping_operation (enum rtx_code code, enum machine_mode mode,
+ rtx op0, rtx op1)
+{
+ rtx tem;
+
+ /* (op (bswap x) C1)) -> (bswap (op x C2)) with C2 swapped. */
+ if (GET_CODE (op0) == BSWAP && CONST_SCALAR_INT_P (op1))
+ {
+ tem = simplify_gen_binary (code, mode, XEXP (op0, 0),
+ simplify_gen_unary (BSWAP, mode, op1, mode));
+ return simplify_gen_unary (BSWAP, mode, tem, mode);
+ }
+
+ /* (op (bswap x) (bswap y)) -> (bswap (op x y)). */
+ if (GET_CODE (op0) == BSWAP && GET_CODE (op1) == BSWAP)
+ {
+ tem = simplify_gen_binary (code, mode, XEXP (op0, 0), XEXP (op1, 0));
+ return simplify_gen_unary (BSWAP, mode, tem, mode);
+ }
+
+ return NULL_RTX;
+}
+
/* Subroutine of simplify_binary_operation to simplify a commutative,
associative binary operation CODE with result mode MODE, operating
on OP0 and OP1. CODE is currently one of PLUS, MULT, AND, IOR, XOR,
if (SCALAR_INT_MODE_P (mode))
{
- double_int coeff0, coeff1;
rtx lhs = op0, rhs = op1;
- coeff0 = double_int_one;
- coeff1 = double_int_one;
+ wide_int coeff0 = wi::one (GET_MODE_PRECISION (mode));
+ wide_int coeff1 = wi::one (GET_MODE_PRECISION (mode));
if (GET_CODE (lhs) == NEG)
{
- coeff0 = double_int_minus_one;
+ coeff0 = wi::minus_one (GET_MODE_PRECISION (mode));
lhs = XEXP (lhs, 0);
}
else if (GET_CODE (lhs) == MULT
- && CONST_INT_P (XEXP (lhs, 1)))
+ && CONST_SCALAR_INT_P (XEXP (lhs, 1)))
{
- coeff0 = double_int::from_shwi (INTVAL (XEXP (lhs, 1)));
+ coeff0 = std::make_pair (XEXP (lhs, 1), mode);
lhs = XEXP (lhs, 0);
}
else if (GET_CODE (lhs) == ASHIFT
&& CONST_INT_P (XEXP (lhs, 1))
&& INTVAL (XEXP (lhs, 1)) >= 0
- && INTVAL (XEXP (lhs, 1)) < HOST_BITS_PER_WIDE_INT)
+ && INTVAL (XEXP (lhs, 1)) < GET_MODE_PRECISION (mode))
{
- coeff0 = double_int_zero.set_bit (INTVAL (XEXP (lhs, 1)));
+ coeff0 = wi::set_bit_in_zero (INTVAL (XEXP (lhs, 1)),
+ GET_MODE_PRECISION (mode));
lhs = XEXP (lhs, 0);
}
if (GET_CODE (rhs) == NEG)
{
- coeff1 = double_int_minus_one;
+ coeff1 = wi::minus_one (GET_MODE_PRECISION (mode));
rhs = XEXP (rhs, 0);
}
else if (GET_CODE (rhs) == MULT
&& CONST_INT_P (XEXP (rhs, 1)))
{
- coeff1 = double_int::from_shwi (INTVAL (XEXP (rhs, 1)));
+ coeff1 = std::make_pair (XEXP (rhs, 1), mode);
rhs = XEXP (rhs, 0);
}
else if (GET_CODE (rhs) == ASHIFT
&& CONST_INT_P (XEXP (rhs, 1))
&& INTVAL (XEXP (rhs, 1)) >= 0
- && INTVAL (XEXP (rhs, 1)) < HOST_BITS_PER_WIDE_INT)
+ && INTVAL (XEXP (rhs, 1)) < GET_MODE_PRECISION (mode))
{
- coeff1 = double_int_zero.set_bit (INTVAL (XEXP (rhs, 1)));
+ coeff1 = wi::set_bit_in_zero (INTVAL (XEXP (rhs, 1)),
+ GET_MODE_PRECISION (mode));
rhs = XEXP (rhs, 0);
}
{
rtx orig = gen_rtx_PLUS (mode, op0, op1);
rtx coeff;
- double_int val;
bool speed = optimize_function_for_speed_p (cfun);
- val = coeff0 + coeff1;
- coeff = immed_double_int_const (val, mode);
+ coeff = immed_wide_int_const (coeff0 + coeff1, mode);
tem = simplify_gen_binary (MULT, mode, lhs, coeff);
return set_src_cost (tem, speed) <= set_src_cost (orig, speed)
}
/* (plus (xor X C1) C2) is (xor X (C1^C2)) if C2 is signbit. */
- if ((CONST_INT_P (op1) || CONST_DOUBLE_AS_INT_P (op1))
+ if (CONST_SCALAR_INT_P (op1)
&& GET_CODE (op0) == XOR
- && (CONST_INT_P (XEXP (op0, 1))
- || CONST_DOUBLE_AS_INT_P (XEXP (op0, 1)))
+ && CONST_SCALAR_INT_P (XEXP (op0, 1))
&& mode_signbit_p (mode, op1))
return simplify_gen_binary (XOR, mode, XEXP (op0, 0),
simplify_gen_binary (XOR, mode, op1,
if (SCALAR_INT_MODE_P (mode))
{
- double_int coeff0, negcoeff1;
rtx lhs = op0, rhs = op1;
- coeff0 = double_int_one;
- negcoeff1 = double_int_minus_one;
+ wide_int coeff0 = wi::one (GET_MODE_PRECISION (mode));
+ wide_int negcoeff1 = wi::minus_one (GET_MODE_PRECISION (mode));
if (GET_CODE (lhs) == NEG)
{
- coeff0 = double_int_minus_one;
+ coeff0 = wi::minus_one (GET_MODE_PRECISION (mode));
lhs = XEXP (lhs, 0);
}
else if (GET_CODE (lhs) == MULT
- && CONST_INT_P (XEXP (lhs, 1)))
+ && CONST_SCALAR_INT_P (XEXP (lhs, 1)))
{
- coeff0 = double_int::from_shwi (INTVAL (XEXP (lhs, 1)));
+ coeff0 = std::make_pair (XEXP (lhs, 1), mode);
lhs = XEXP (lhs, 0);
}
else if (GET_CODE (lhs) == ASHIFT
&& CONST_INT_P (XEXP (lhs, 1))
&& INTVAL (XEXP (lhs, 1)) >= 0
- && INTVAL (XEXP (lhs, 1)) < HOST_BITS_PER_WIDE_INT)
+ && INTVAL (XEXP (lhs, 1)) < GET_MODE_PRECISION (mode))
{
- coeff0 = double_int_zero.set_bit (INTVAL (XEXP (lhs, 1)));
+ coeff0 = wi::set_bit_in_zero (INTVAL (XEXP (lhs, 1)),
+ GET_MODE_PRECISION (mode));
lhs = XEXP (lhs, 0);
}
if (GET_CODE (rhs) == NEG)
{
- negcoeff1 = double_int_one;
+ negcoeff1 = wi::one (GET_MODE_PRECISION (mode));
rhs = XEXP (rhs, 0);
}
else if (GET_CODE (rhs) == MULT
&& CONST_INT_P (XEXP (rhs, 1)))
{
- negcoeff1 = double_int::from_shwi (-INTVAL (XEXP (rhs, 1)));
+ negcoeff1 = wi::neg (std::make_pair (XEXP (rhs, 1), mode));
rhs = XEXP (rhs, 0);
}
else if (GET_CODE (rhs) == ASHIFT
&& CONST_INT_P (XEXP (rhs, 1))
&& INTVAL (XEXP (rhs, 1)) >= 0
- && INTVAL (XEXP (rhs, 1)) < HOST_BITS_PER_WIDE_INT)
+ && INTVAL (XEXP (rhs, 1)) < GET_MODE_PRECISION (mode))
{
- negcoeff1 = double_int_zero.set_bit (INTVAL (XEXP (rhs, 1)));
+ negcoeff1 = wi::set_bit_in_zero (INTVAL (XEXP (rhs, 1)),
+ GET_MODE_PRECISION (mode));
negcoeff1 = -negcoeff1;
rhs = XEXP (rhs, 0);
}
{
rtx orig = gen_rtx_MINUS (mode, op0, op1);
rtx coeff;
- double_int val;
bool speed = optimize_function_for_speed_p (cfun);
- val = coeff0 + negcoeff1;
- coeff = immed_double_int_const (val, mode);
+ coeff = immed_wide_int_const (coeff0 + negcoeff1, mode);
tem = simplify_gen_binary (MULT, mode, lhs, coeff);
return set_src_cost (tem, speed) <= set_src_cost (orig, speed)
/* (-x - c) may be simplified as (-c - x). */
if (GET_CODE (op0) == NEG
- && (CONST_INT_P (op1) || CONST_DOUBLE_P (op1)))
+ && (CONST_SCALAR_INT_P (op1) || CONST_DOUBLE_AS_FLOAT_P (op1)))
{
tem = simplify_unary_operation (NEG, mode, op1, mode);
if (tem)
&& trueop1 == CONST1_RTX (mode))
return op0;
- /* Convert multiply by constant power of two into shift unless
- we are still generating RTL. This test is a kludge. */
- if (CONST_INT_P (trueop1)
- && (val = exact_log2 (UINTVAL (trueop1))) >= 0
- /* If the mode is larger than the host word size, and the
- uppermost bit is set, then this isn't a power of two due
- to implicit sign extension. */
- && (width <= HOST_BITS_PER_WIDE_INT
- || val != HOST_BITS_PER_WIDE_INT - 1))
- return simplify_gen_binary (ASHIFT, mode, op0, GEN_INT (val));
-
- /* Likewise for multipliers wider than a word. */
- if (CONST_DOUBLE_AS_INT_P (trueop1)
- && GET_MODE (op0) == mode
- && CONST_DOUBLE_LOW (trueop1) == 0
- && (val = exact_log2 (CONST_DOUBLE_HIGH (trueop1))) >= 0
- && (val < HOST_BITS_PER_DOUBLE_INT - 1
- || GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_DOUBLE_INT))
- return simplify_gen_binary (ASHIFT, mode, op0,
- GEN_INT (val + HOST_BITS_PER_WIDE_INT));
+ /* Convert multiply by constant power of two into shift. */
+ if (CONST_SCALAR_INT_P (trueop1))
+ {
+ val = wi::exact_log2 (std::make_pair (trueop1, mode));
+ if (val >= 0)
+ return simplify_gen_binary (ASHIFT, mode, op0, GEN_INT (val));
+ }
/* x*2 is x+x and x*(-1) is -x */
if (CONST_DOUBLE_AS_FLOAT_P (trueop1)
&& CONST_INT_P (XEXP (op0, 1))
&& CONST_INT_P (op1)
&& (UINTVAL (XEXP (op0, 1)) & UINTVAL (op1)) != 0)
- return simplify_gen_binary (IOR, mode,
- simplify_gen_binary
- (AND, mode, XEXP (op0, 0),
- GEN_INT (UINTVAL (XEXP (op0, 1))
- & ~UINTVAL (op1))),
- op1);
+ {
+ rtx tmp = simplify_gen_binary (AND, mode, XEXP (op0, 0),
+ gen_int_mode (UINTVAL (XEXP (op0, 1))
+ & ~UINTVAL (op1),
+ mode));
+ return simplify_gen_binary (IOR, mode, tmp, op1);
+ }
/* If OP0 is (ashiftrt (plus ...) C), it might actually be
a (sign_extend (plus ...)). Then check if OP1 is a CONST_INT and
HOST_WIDE_INT mask = INTVAL (trueop1) << count;
if (mask >> count == INTVAL (trueop1)
+ && trunc_int_for_mode (mask, mode) == mask
&& (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
return simplify_gen_binary (ASHIFTRT, mode,
plus_constant (mode, XEXP (op0, 0),
XEXP (op0, 1));
}
+ tem = simplify_byte_swapping_operation (code, mode, op0, op1);
+ if (tem)
+ return tem;
+
tem = simplify_associative_operation (code, mode, op0, op1);
if (tem)
return tem;
return CONST0_RTX (mode);
/* Canonicalize XOR of the most significant bit to PLUS. */
- if ((CONST_INT_P (op1) || CONST_DOUBLE_AS_INT_P (op1))
+ if (CONST_SCALAR_INT_P (op1)
&& mode_signbit_p (mode, op1))
return simplify_gen_binary (PLUS, mode, op0, op1);
/* (xor (plus X C1) C2) is (xor X (C1^C2)) if C1 is signbit. */
- if ((CONST_INT_P (op1) || CONST_DOUBLE_AS_INT_P (op1))
+ if (CONST_SCALAR_INT_P (op1)
&& GET_CODE (op0) == PLUS
- && (CONST_INT_P (XEXP (op0, 1))
- || CONST_DOUBLE_AS_INT_P (XEXP (op0, 1)))
+ && CONST_SCALAR_INT_P (XEXP (op0, 1))
&& mode_signbit_p (mode, XEXP (op0, 1)))
return simplify_gen_binary (XOR, mode, XEXP (op0, 0),
simplify_gen_binary (XOR, mode, op1,
/* Try to simplify ~A&C | ~B&C. */
if (na_c != NULL_RTX)
return simplify_gen_binary (IOR, mode, na_c,
- GEN_INT (~bval & cval));
+ gen_int_mode (~bval & cval, mode));
}
else
{
if (na_c == const0_rtx)
{
rtx a_nc_b = simplify_gen_binary (AND, mode, a,
- GEN_INT (~cval & bval));
+ gen_int_mode (~cval & bval,
+ mode));
return simplify_gen_binary (IOR, mode, a_nc_b,
- GEN_INT (~bval & cval));
+ gen_int_mode (~bval & cval,
+ mode));
}
}
}
&& (reversed = reversed_comparison (op0, mode)))
return reversed;
+ tem = simplify_byte_swapping_operation (code, mode, op0, op1);
+ if (tem)
+ return tem;
+
tem = simplify_associative_operation (code, mode, op0, op1);
if (tem)
return tem;
&& op1 == XEXP (XEXP (op0, 0), 0))
return simplify_gen_binary (AND, mode, op1, XEXP (op0, 1));
+ tem = simplify_byte_swapping_operation (code, mode, op0, op1);
+ if (tem)
+ return tem;
+
tem = simplify_associative_operation (code, mode, op0, op1);
if (tem)
return tem;
}
/* x/1 is x. */
if (trueop1 == CONST1_RTX (mode))
- return rtl_hooks.gen_lowpart_no_emit (mode, op0);
+ {
+ tem = rtl_hooks.gen_lowpart_no_emit (mode, op0);
+ if (tem)
+ return tem;
+ }
/* Convert divide by power of two into shift. */
if (CONST_INT_P (trueop1)
&& (val = exact_log2 (UINTVAL (trueop1))) > 0)
}
/* x/1 is x. */
if (trueop1 == CONST1_RTX (mode))
- return rtl_hooks.gen_lowpart_no_emit (mode, op0);
+ {
+ tem = rtl_hooks.gen_lowpart_no_emit (mode, op0);
+ if (tem)
+ return tem;
+ }
/* x/-1 is -x. */
if (trueop1 == constm1_rtx)
{
rtx x = rtl_hooks.gen_lowpart_no_emit (mode, op0);
- return simplify_gen_unary (NEG, mode, x, mode);
+ if (x)
+ return simplify_gen_unary (NEG, mode, x, mode);
}
}
break;
if (CONST_INT_P (trueop1)
&& exact_log2 (UINTVAL (trueop1)) > 0)
return simplify_gen_binary (AND, mode, op0,
- GEN_INT (INTVAL (op1) - 1));
+ gen_int_mode (INTVAL (op1) - 1, mode));
break;
case MOD:
case ROTATERT:
case ROTATE:
+ /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
+ prefer left rotation, if op1 is from bitsize / 2 + 1 to
+ bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
+ amount instead. */
+ if (CONST_INT_P (trueop1)
+ && IN_RANGE (INTVAL (trueop1),
+ GET_MODE_BITSIZE (mode) / 2 + (code == ROTATE),
+ GET_MODE_BITSIZE (mode) - 1))
+ return simplify_gen_binary (code == ROTATE ? ROTATERT : ROTATE,
+ mode, op0, GEN_INT (GET_MODE_BITSIZE (mode)
+ - INTVAL (trueop1)));
+ /* FALLTHRU */
case ASHIFTRT:
if (trueop1 == CONST0_RTX (mode))
return op0;
return vec;
}
+ /* If we select elements in a vec_merge that all come from the same
+ operand, select from that operand directly. */
+ if (GET_CODE (op0) == VEC_MERGE)
+ {
+ rtx trueop02 = avoid_constant_pool_reference (XEXP (op0, 2));
+ if (CONST_INT_P (trueop02))
+ {
+ unsigned HOST_WIDE_INT sel = UINTVAL (trueop02);
+ bool all_operand0 = true;
+ bool all_operand1 = true;
+ for (int i = 0; i < XVECLEN (trueop1, 0); i++)
+ {
+ rtx j = XVECEXP (trueop1, 0, i);
+ if (sel & (1 << UINTVAL (j)))
+ all_operand1 = false;
+ else
+ all_operand0 = false;
+ }
+ if (all_operand0 && !side_effects_p (XEXP (op0, 1)))
+ return simplify_gen_binary (VEC_SELECT, mode, XEXP (op0, 0), op1);
+ if (all_operand1 && !side_effects_p (XEXP (op0, 0)))
+ return simplify_gen_binary (VEC_SELECT, mode, XEXP (op0, 1), op1);
+ }
+ }
+
return 0;
case VEC_CONCAT:
{
gcc_assert (GET_MODE_INNER (mode) == op1_mode);
if ((GET_CODE (trueop0) == CONST_VECTOR
- || CONST_INT_P (trueop0) || CONST_DOUBLE_P (trueop0))
+ || CONST_SCALAR_INT_P (trueop0)
+ || CONST_DOUBLE_AS_FLOAT_P (trueop0))
&& (GET_CODE (trueop1) == CONST_VECTOR
- || CONST_INT_P (trueop1) || CONST_DOUBLE_P (trueop1)))
+ || CONST_SCALAR_INT_P (trueop1)
+ || CONST_DOUBLE_AS_FLOAT_P (trueop1)))
{
int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
return gen_rtx_CONST_VECTOR (mode, v);
}
- /* Try to merge VEC_SELECTs from the same vector into a single one. */
+ /* Try to merge two VEC_SELECTs from the same vector into a single one.
+ Restrict the transformation to avoid generating a VEC_SELECT with a
+ mode unrelated to its operand. */
if (GET_CODE (trueop0) == VEC_SELECT
&& GET_CODE (trueop1) == VEC_SELECT
- && rtx_equal_p (XEXP (trueop0, 0), XEXP (trueop1, 0)))
+ && rtx_equal_p (XEXP (trueop0, 0), XEXP (trueop1, 0))
+ && GET_MODE (XEXP (trueop0, 0)) == mode)
{
rtx par0 = XEXP (trueop0, 1);
rtx par1 = XEXP (trueop1, 1);
simplify_const_binary_operation (enum rtx_code code, enum machine_mode mode,
rtx op0, rtx op1)
{
- HOST_WIDE_INT arg0, arg1, arg0s, arg1s;
- HOST_WIDE_INT val;
unsigned int width = GET_MODE_PRECISION (mode);
if (VECTOR_MODE_P (mode)
if (VECTOR_MODE_P (mode)
&& code == VEC_CONCAT
- && (CONST_INT_P (op0)
+ && (CONST_SCALAR_INT_P (op0)
|| GET_CODE (op0) == CONST_FIXED
- || CONST_DOUBLE_P (op0))
- && (CONST_INT_P (op1)
- || CONST_DOUBLE_P (op1)
+ || CONST_DOUBLE_AS_FLOAT_P (op0))
+ && (CONST_SCALAR_INT_P (op1)
+ || CONST_DOUBLE_AS_FLOAT_P (op1)
|| GET_CODE (op1) == CONST_FIXED))
{
unsigned n_elts = GET_MODE_NUNITS (mode);
return 0;
default:
break;
- }
- }
-
- if (code == MULT && MODE_HAS_INFINITIES (mode) && HONOR_NANS (mode)
- && flag_trapping_math
- && ((REAL_VALUE_ISINF (f0) && REAL_VALUES_EQUAL (f1, dconst0))
- || (REAL_VALUE_ISINF (f1)
- && REAL_VALUES_EQUAL (f0, dconst0))))
- /* Inf * 0 = NaN plus exception. */
- return 0;
-
- inexact = real_arithmetic (&value, rtx_to_tree_code (code),
- &f0, &f1);
- real_convert (&result, mode, &value);
-
- /* Don't constant fold this floating point operation if
- the result has overflowed and flag_trapping_math. */
-
- if (flag_trapping_math
- && MODE_HAS_INFINITIES (mode)
- && REAL_VALUE_ISINF (result)
- && !REAL_VALUE_ISINF (f0)
- && !REAL_VALUE_ISINF (f1))
- /* Overflow plus exception. */
- return 0;
-
- /* Don't constant fold this floating point operation if the
- result may dependent upon the run-time rounding mode and
- flag_rounding_math is set, or if GCC's software emulation
- is unable to accurately represent the result. */
-
- if ((flag_rounding_math
- || (MODE_COMPOSITE_P (mode) && !flag_unsafe_math_optimizations))
- && (inexact || !real_identical (&result, &value)))
- return NULL_RTX;
-
- return CONST_DOUBLE_FROM_REAL_VALUE (result, mode);
- }
- }
-
- /* We can fold some multi-word operations. */
- if (GET_MODE_CLASS (mode) == MODE_INT
- && width == HOST_BITS_PER_DOUBLE_INT
- && (CONST_DOUBLE_AS_INT_P (op0) || CONST_INT_P (op0))
- && (CONST_DOUBLE_AS_INT_P (op1) || CONST_INT_P (op1)))
- {
- double_int o0, o1, res, tmp;
- bool overflow;
-
- o0 = rtx_to_double_int (op0);
- o1 = rtx_to_double_int (op1);
-
- switch (code)
- {
- case MINUS:
- /* A - B == A + (-B). */
- o1 = -o1;
-
- /* Fall through.... */
-
- case PLUS:
- res = o0 + o1;
- break;
-
- case MULT:
- res = o0 * o1;
- break;
-
- case DIV:
- res = o0.divmod_with_overflow (o1, false, TRUNC_DIV_EXPR,
- &tmp, &overflow);
- if (overflow)
- return 0;
- break;
-
- case MOD:
- tmp = o0.divmod_with_overflow (o1, false, TRUNC_DIV_EXPR,
- &res, &overflow);
- if (overflow)
- return 0;
- break;
-
- case UDIV:
- res = o0.divmod_with_overflow (o1, true, TRUNC_DIV_EXPR,
- &tmp, &overflow);
- if (overflow)
- return 0;
- break;
-
- case UMOD:
- tmp = o0.divmod_with_overflow (o1, true, TRUNC_DIV_EXPR,
- &res, &overflow);
- if (overflow)
- return 0;
- break;
-
- case AND:
- res = o0 & o1;
- break;
-
- case IOR:
- res = o0 | o1;
- break;
-
- case XOR:
- res = o0 ^ o1;
- break;
-
- case SMIN:
- res = o0.smin (o1);
- break;
-
- case SMAX:
- res = o0.smax (o1);
- break;
-
- case UMIN:
- res = o0.umin (o1);
- break;
-
- case UMAX:
- res = o0.umax (o1);
- break;
-
- case LSHIFTRT: case ASHIFTRT:
- case ASHIFT:
- case ROTATE: case ROTATERT:
- {
- unsigned HOST_WIDE_INT cnt;
-
- if (SHIFT_COUNT_TRUNCATED)
- {
- o1.high = 0;
- o1.low &= GET_MODE_PRECISION (mode) - 1;
- }
-
- if (!o1.fits_uhwi ()
- || o1.to_uhwi () >= GET_MODE_PRECISION (mode))
- return 0;
-
- cnt = o1.to_uhwi ();
- unsigned short prec = GET_MODE_PRECISION (mode);
-
- if (code == LSHIFTRT || code == ASHIFTRT)
- res = o0.rshift (cnt, prec, code == ASHIFTRT);
- else if (code == ASHIFT)
- res = o0.alshift (cnt, prec);
- else if (code == ROTATE)
- res = o0.lrotate (cnt, prec);
- else /* code == ROTATERT */
- res = o0.rrotate (cnt, prec);
- }
- break;
+ }
+ }
- default:
- return 0;
- }
+ if (code == MULT && MODE_HAS_INFINITIES (mode) && HONOR_NANS (mode)
+ && flag_trapping_math
+ && ((REAL_VALUE_ISINF (f0) && REAL_VALUES_EQUAL (f1, dconst0))
+ || (REAL_VALUE_ISINF (f1)
+ && REAL_VALUES_EQUAL (f0, dconst0))))
+ /* Inf * 0 = NaN plus exception. */
+ return 0;
- return immed_double_int_const (res, mode);
- }
+ inexact = real_arithmetic (&value, rtx_to_tree_code (code),
+ &f0, &f1);
+ real_convert (&result, mode, &value);
- if (CONST_INT_P (op0) && CONST_INT_P (op1)
- && width <= HOST_BITS_PER_WIDE_INT && width != 0)
- {
- /* Get the integer argument values in two forms:
- zero-extended in ARG0, ARG1 and sign-extended in ARG0S, ARG1S. */
+ /* Don't constant fold this floating point operation if
+ the result has overflowed and flag_trapping_math. */
- arg0 = INTVAL (op0);
- arg1 = INTVAL (op1);
+ if (flag_trapping_math
+ && MODE_HAS_INFINITIES (mode)
+ && REAL_VALUE_ISINF (result)
+ && !REAL_VALUE_ISINF (f0)
+ && !REAL_VALUE_ISINF (f1))
+ /* Overflow plus exception. */
+ return 0;
- if (width < HOST_BITS_PER_WIDE_INT)
- {
- arg0 &= GET_MODE_MASK (mode);
- arg1 &= GET_MODE_MASK (mode);
+ /* Don't constant fold this floating point operation if the
+ result may dependent upon the run-time rounding mode and
+ flag_rounding_math is set, or if GCC's software emulation
+ is unable to accurately represent the result. */
- arg0s = arg0;
- if (val_signbit_known_set_p (mode, arg0s))
- arg0s |= ~GET_MODE_MASK (mode);
+ if ((flag_rounding_math
+ || (MODE_COMPOSITE_P (mode) && !flag_unsafe_math_optimizations))
+ && (inexact || !real_identical (&result, &value)))
+ return NULL_RTX;
- arg1s = arg1;
- if (val_signbit_known_set_p (mode, arg1s))
- arg1s |= ~GET_MODE_MASK (mode);
- }
- else
- {
- arg0s = arg0;
- arg1s = arg1;
+ return CONST_DOUBLE_FROM_REAL_VALUE (result, mode);
}
+ }
- /* Compute the value of the arithmetic. */
-
+ /* We can fold some multi-word operations. */
+ if (GET_MODE_CLASS (mode) == MODE_INT
+ && CONST_SCALAR_INT_P (op0)
+ && CONST_SCALAR_INT_P (op1))
+ {
+ wide_int result;
+ bool overflow;
+ rtx_mode_t pop0 = std::make_pair (op0, mode);
+ rtx_mode_t pop1 = std::make_pair (op1, mode);
+
+#if TARGET_SUPPORTS_WIDE_INT == 0
+ /* This assert keeps the simplification from producing a result
+ that cannot be represented in a CONST_DOUBLE but a lot of
+ upstream callers expect that this function never fails to
+ simplify something and so you if you added this to the test
+ above the code would die later anyway. If this assert
+ happens, you just need to make the port support wide int. */
+ gcc_assert (width <= HOST_BITS_PER_DOUBLE_INT);
+#endif
switch (code)
{
- case PLUS:
- val = arg0s + arg1s;
+ case MINUS:
+ result = wi::sub (pop0, pop1);
break;
- case MINUS:
- val = arg0s - arg1s;
+ case PLUS:
+ result = wi::add (pop0, pop1);
break;
case MULT:
- val = arg0s * arg1s;
+ result = wi::mul (pop0, pop1);
break;
case DIV:
- if (arg1s == 0
- || ((unsigned HOST_WIDE_INT) arg0s
- == (unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
- && arg1s == -1))
- return 0;
- val = arg0s / arg1s;
+ result = wi::div_trunc (pop0, pop1, SIGNED, &overflow);
+ if (overflow)
+ return NULL_RTX;
break;
-
+
case MOD:
- if (arg1s == 0
- || ((unsigned HOST_WIDE_INT) arg0s
- == (unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
- && arg1s == -1))
- return 0;
- val = arg0s % arg1s;
+ result = wi::mod_trunc (pop0, pop1, SIGNED, &overflow);
+ if (overflow)
+ return NULL_RTX;
break;
case UDIV:
- if (arg1 == 0
- || ((unsigned HOST_WIDE_INT) arg0s
- == (unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
- && arg1s == -1))
- return 0;
- val = (unsigned HOST_WIDE_INT) arg0 / arg1;
+ result = wi::div_trunc (pop0, pop1, UNSIGNED, &overflow);
+ if (overflow)
+ return NULL_RTX;
break;
case UMOD:
- if (arg1 == 0
- || ((unsigned HOST_WIDE_INT) arg0s
- == (unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)
- && arg1s == -1))
- return 0;
- val = (unsigned HOST_WIDE_INT) arg0 % arg1;
+ result = wi::mod_trunc (pop0, pop1, UNSIGNED, &overflow);
+ if (overflow)
+ return NULL_RTX;
break;
case AND:
- val = arg0 & arg1;
+ result = wi::bit_and (pop0, pop1);
break;
case IOR:
- val = arg0 | arg1;
+ result = wi::bit_or (pop0, pop1);
break;
case XOR:
- val = arg0 ^ arg1;
- break;
-
- case LSHIFTRT:
- case ASHIFT:
- case ASHIFTRT:
- /* Truncate the shift if SHIFT_COUNT_TRUNCATED, otherwise make sure
- the value is in range. We can't return any old value for
- out-of-range arguments because either the middle-end (via
- shift_truncation_mask) or the back-end might be relying on
- target-specific knowledge. Nor can we rely on
- shift_truncation_mask, since the shift might not be part of an
- ashlM3, lshrM3 or ashrM3 instruction. */
- if (SHIFT_COUNT_TRUNCATED)
- arg1 = (unsigned HOST_WIDE_INT) arg1 % width;
- else if (arg1 < 0 || arg1 >= GET_MODE_BITSIZE (mode))
- return 0;
-
- val = (code == ASHIFT
- ? ((unsigned HOST_WIDE_INT) arg0) << arg1
- : ((unsigned HOST_WIDE_INT) arg0) >> arg1);
-
- /* Sign-extend the result for arithmetic right shifts. */
- if (code == ASHIFTRT && arg0s < 0 && arg1 > 0)
- val |= ((unsigned HOST_WIDE_INT) (-1)) << (width - arg1);
- break;
-
- case ROTATERT:
- if (arg1 < 0)
- return 0;
-
- arg1 %= width;
- val = ((((unsigned HOST_WIDE_INT) arg0) << (width - arg1))
- | (((unsigned HOST_WIDE_INT) arg0) >> arg1));
- break;
-
- case ROTATE:
- if (arg1 < 0)
- return 0;
-
- arg1 %= width;
- val = ((((unsigned HOST_WIDE_INT) arg0) << arg1)
- | (((unsigned HOST_WIDE_INT) arg0) >> (width - arg1)));
+ result = wi::bit_xor (pop0, pop1);
break;
- case COMPARE:
- /* Do nothing here. */
- return 0;
-
case SMIN:
- val = arg0s <= arg1s ? arg0s : arg1s;
+ result = wi::smin (pop0, pop1);
break;
- case UMIN:
- val = ((unsigned HOST_WIDE_INT) arg0
- <= (unsigned HOST_WIDE_INT) arg1 ? arg0 : arg1);
+ case SMAX:
+ result = wi::smax (pop0, pop1);
break;
- case SMAX:
- val = arg0s > arg1s ? arg0s : arg1s;
+ case UMIN:
+ result = wi::umin (pop0, pop1);
break;
case UMAX:
- val = ((unsigned HOST_WIDE_INT) arg0
- > (unsigned HOST_WIDE_INT) arg1 ? arg0 : arg1);
+ result = wi::umax (pop0, pop1);
break;
- case SS_PLUS:
- case US_PLUS:
- case SS_MINUS:
- case US_MINUS:
- case SS_MULT:
- case US_MULT:
- case SS_DIV:
- case US_DIV:
- case SS_ASHIFT:
- case US_ASHIFT:
- /* ??? There are simplifications that can be done. */
- return 0;
+ case LSHIFTRT:
+ case ASHIFTRT:
+ case ASHIFT:
+ {
+ wide_int wop1 = pop1;
+ if (SHIFT_COUNT_TRUNCATED)
+ wop1 = wi::umod_trunc (wop1, width);
+ else if (wi::geu_p (wop1, width))
+ return NULL_RTX;
+
+ switch (code)
+ {
+ case LSHIFTRT:
+ result = wi::lrshift (pop0, wop1);
+ break;
+
+ case ASHIFTRT:
+ result = wi::arshift (pop0, wop1);
+ break;
+
+ case ASHIFT:
+ result = wi::lshift (pop0, wop1);
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+ break;
+ }
+ case ROTATE:
+ case ROTATERT:
+ {
+ if (wi::neg_p (pop1))
+ return NULL_RTX;
+
+ switch (code)
+ {
+ case ROTATE:
+ result = wi::lrotate (pop0, pop1);
+ break;
+
+ case ROTATERT:
+ result = wi::rrotate (pop0, pop1);
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ break;
+ }
default:
- gcc_unreachable ();
+ return NULL_RTX;
}
-
- return gen_int_mode (val, mode);
+ return immed_wide_int_const (result, mode);
}
return NULL_RTX;
&& GET_CODE (op0) == PLUS
&& CONST_INT_P (XEXP (op0, 1))
&& (rtx_equal_p (op1, XEXP (op0, 0))
- || rtx_equal_p (op1, XEXP (op0, 1))))
+ || rtx_equal_p (op1, XEXP (op0, 1)))
+ /* (LTU/GEU (PLUS a 0) 0) is not the same as (GEU/LTU a 0). */
+ && XEXP (op0, 1) != const0_rtx)
{
rtx new_cmp
= simplify_gen_unary (NEG, cmp_mode, XEXP (op0, 1), cmp_mode);
/* (eq/ne (xor x C1) C2) simplifies to (eq/ne x (C1^C2)). */
if ((code == EQ || code == NE)
&& op0code == XOR
- && (CONST_INT_P (op1) || CONST_DOUBLE_AS_INT_P (op1))
- && (CONST_INT_P (XEXP (op0, 1))
- || CONST_DOUBLE_AS_INT_P (XEXP (op0, 1))))
+ && CONST_SCALAR_INT_P (op1)
+ && CONST_SCALAR_INT_P (XEXP (op0, 1)))
return simplify_gen_relational (code, mode, cmp_mode, XEXP (op0, 0),
simplify_gen_binary (XOR, cmp_mode,
XEXP (op0, 1), op1));
+ /* (eq/ne (bswap x) C1) simplifies to (eq/ne x C2) with C2 swapped. */
+ if ((code == EQ || code == NE)
+ && GET_CODE (op0) == BSWAP
+ && CONST_SCALAR_INT_P (op1))
+ return simplify_gen_relational (code, mode, cmp_mode, XEXP (op0, 0),
+ simplify_gen_unary (BSWAP, cmp_mode,
+ op1, cmp_mode));
+
+ /* (eq/ne (bswap x) (bswap y)) simplifies to (eq/ne x y). */
+ if ((code == EQ || code == NE)
+ && GET_CODE (op0) == BSWAP
+ && GET_CODE (op1) == BSWAP)
+ return simplify_gen_relational (code, mode, cmp_mode,
+ XEXP (op0, 0), XEXP (op1, 0));
+
if (op0code == POPCOUNT && op1 == const0_rtx)
switch (code)
{
}
}
-/* Check if the given comparison (done in the given MODE) is actually a
- tautology or a contradiction.
- If no simplification is possible, this function returns zero.
- Otherwise, it returns either const_true_rtx or const0_rtx. */
+/* Check if the given comparison (done in the given MODE) is actually
+ a tautology or a contradiction. If the mode is VOID_mode, the
+ comparison is done in "infinite precision". If no simplification
+ is possible, this function returns zero. Otherwise, it returns
+ either const_true_rtx or const0_rtx. */
rtx
simplify_const_relational_operation (enum rtx_code code,
/* Otherwise, see if the operands are both integers. */
if ((GET_MODE_CLASS (mode) == MODE_INT || mode == VOIDmode)
- && (CONST_DOUBLE_AS_INT_P (trueop0) || CONST_INT_P (trueop0))
- && (CONST_DOUBLE_AS_INT_P (trueop1) || CONST_INT_P (trueop1)))
+ && CONST_SCALAR_INT_P (trueop0) && CONST_SCALAR_INT_P (trueop1))
{
- int width = GET_MODE_PRECISION (mode);
- HOST_WIDE_INT l0s, h0s, l1s, h1s;
- unsigned HOST_WIDE_INT l0u, h0u, l1u, h1u;
-
- /* Get the two words comprising each integer constant. */
- if (CONST_DOUBLE_AS_INT_P (trueop0))
- {
- l0u = l0s = CONST_DOUBLE_LOW (trueop0);
- h0u = h0s = CONST_DOUBLE_HIGH (trueop0);
- }
- else
- {
- l0u = l0s = INTVAL (trueop0);
- h0u = h0s = HWI_SIGN_EXTEND (l0s);
- }
-
- if (CONST_DOUBLE_AS_INT_P (trueop1))
- {
- l1u = l1s = CONST_DOUBLE_LOW (trueop1);
- h1u = h1s = CONST_DOUBLE_HIGH (trueop1);
- }
- else
- {
- l1u = l1s = INTVAL (trueop1);
- h1u = h1s = HWI_SIGN_EXTEND (l1s);
- }
-
- /* If WIDTH is nonzero and smaller than HOST_BITS_PER_WIDE_INT,
- we have to sign or zero-extend the values. */
- if (width != 0 && width < HOST_BITS_PER_WIDE_INT)
- {
- l0u &= GET_MODE_MASK (mode);
- l1u &= GET_MODE_MASK (mode);
-
- if (val_signbit_known_set_p (mode, l0s))
- l0s |= ~GET_MODE_MASK (mode);
-
- if (val_signbit_known_set_p (mode, l1s))
- l1s |= ~GET_MODE_MASK (mode);
- }
- if (width != 0 && width <= HOST_BITS_PER_WIDE_INT)
- h0u = h1u = 0, h0s = HWI_SIGN_EXTEND (l0s), h1s = HWI_SIGN_EXTEND (l1s);
-
- if (h0u == h1u && l0u == l1u)
+ /* It would be nice if we really had a mode here. However, the
+ largest int representable on the target is as good as
+ infinite. */
+ enum machine_mode cmode = (mode == VOIDmode) ? MAX_MODE_INT : mode;
+ rtx_mode_t ptrueop0 = std::make_pair (trueop0, cmode);
+ rtx_mode_t ptrueop1 = std::make_pair (trueop1, cmode);
+
+ if (wi::eq_p (ptrueop0, ptrueop1))
return comparison_result (code, CMP_EQ);
else
{
- int cr;
- cr = (h0s < h1s || (h0s == h1s && l0u < l1u)) ? CMP_LT : CMP_GT;
- cr |= (h0u < h1u || (h0u == h1u && l0u < l1u)) ? CMP_LTU : CMP_GTU;
+ int cr = wi::lts_p (ptrueop0, ptrueop1) ? CMP_LT : CMP_GT;
+ cr |= wi::ltu_p (ptrueop0, ptrueop1) ? CMP_LTU : CMP_GTU;
return comparison_result (code, cr);
}
}
{
unsigned int width = GET_MODE_PRECISION (mode);
bool any_change = false;
- rtx tem;
+ rtx tem, trueop2;
/* VOIDmode means "infinite" precision. */
if (width == 0)
gcc_assert (GET_MODE (op0) == mode);
gcc_assert (GET_MODE (op1) == mode);
gcc_assert (VECTOR_MODE_P (mode));
- op2 = avoid_constant_pool_reference (op2);
- if (CONST_INT_P (op2))
+ trueop2 = avoid_constant_pool_reference (op2);
+ if (CONST_INT_P (trueop2))
{
- int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
+ int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode));
unsigned n_elts = (GET_MODE_SIZE (mode) / elt_size);
- int mask = (1 << n_elts) - 1;
+ unsigned HOST_WIDE_INT sel = UINTVAL (trueop2);
+ unsigned HOST_WIDE_INT mask;
+ if (n_elts == HOST_BITS_PER_WIDE_INT)
+ mask = -1;
+ else
+ mask = ((unsigned HOST_WIDE_INT) 1 << n_elts) - 1;
- if (!(INTVAL (op2) & mask))
+ if (!(sel & mask) && !side_effects_p (op0))
return op1;
- if ((INTVAL (op2) & mask) == mask)
+ if ((sel & mask) == mask && !side_effects_p (op1))
return op0;
- op0 = avoid_constant_pool_reference (op0);
- op1 = avoid_constant_pool_reference (op1);
- if (GET_CODE (op0) == CONST_VECTOR
- && GET_CODE (op1) == CONST_VECTOR)
+ rtx trueop0 = avoid_constant_pool_reference (op0);
+ rtx trueop1 = avoid_constant_pool_reference (op1);
+ if (GET_CODE (trueop0) == CONST_VECTOR
+ && GET_CODE (trueop1) == CONST_VECTOR)
{
rtvec v = rtvec_alloc (n_elts);
unsigned int i;
for (i = 0; i < n_elts; i++)
- RTVEC_ELT (v, i) = (INTVAL (op2) & (1 << i)
- ? CONST_VECTOR_ELT (op0, i)
- : CONST_VECTOR_ELT (op1, i));
+ RTVEC_ELT (v, i) = ((sel & ((unsigned HOST_WIDE_INT) 1 << i))
+ ? CONST_VECTOR_ELT (trueop0, i)
+ : CONST_VECTOR_ELT (trueop1, i));
return gen_rtx_CONST_VECTOR (mode, v);
}
+
+ /* Replace (vec_merge (vec_merge a b m) c n) with (vec_merge b c n)
+ if no element from a appears in the result. */
+ if (GET_CODE (op0) == VEC_MERGE)
+ {
+ tem = avoid_constant_pool_reference (XEXP (op0, 2));
+ if (CONST_INT_P (tem))
+ {
+ unsigned HOST_WIDE_INT sel0 = UINTVAL (tem);
+ if (!(sel & sel0 & mask) && !side_effects_p (XEXP (op0, 0)))
+ return simplify_gen_ternary (code, mode, mode,
+ XEXP (op0, 1), op1, op2);
+ if (!(sel & ~sel0 & mask) && !side_effects_p (XEXP (op0, 1)))
+ return simplify_gen_ternary (code, mode, mode,
+ XEXP (op0, 0), op1, op2);
+ }
+ }
+ if (GET_CODE (op1) == VEC_MERGE)
+ {
+ tem = avoid_constant_pool_reference (XEXP (op1, 2));
+ if (CONST_INT_P (tem))
+ {
+ unsigned HOST_WIDE_INT sel1 = UINTVAL (tem);
+ if (!(~sel & sel1 & mask) && !side_effects_p (XEXP (op1, 0)))
+ return simplify_gen_ternary (code, mode, mode,
+ op0, XEXP (op1, 1), op2);
+ if (!(~sel & ~sel1 & mask) && !side_effects_p (XEXP (op1, 1)))
+ return simplify_gen_ternary (code, mode, mode,
+ op0, XEXP (op1, 0), op2);
+ }
+ }
}
+
+ if (rtx_equal_p (op0, op1)
+ && !side_effects_p (op2) && !side_effects_p (op1))
+ return op0;
+
break;
default:
return 0;
}
-/* Evaluate a SUBREG of a CONST_INT or CONST_DOUBLE or CONST_FIXED
- or CONST_VECTOR,
- returning another CONST_INT or CONST_DOUBLE or CONST_FIXED or CONST_VECTOR.
+/* Evaluate a SUBREG of a CONST_INT or CONST_WIDE_INT or CONST_DOUBLE
+ or CONST_FIXED or CONST_VECTOR, returning another CONST_INT or
+ CONST_WIDE_INT or CONST_DOUBLE or CONST_FIXED or CONST_VECTOR.
Works by unpacking OP into a collection of 8-bit values
represented as a little-endian array of 'unsigned char', selecting by BYTE,
simplify_immed_subreg (enum machine_mode outermode, rtx op,
enum machine_mode innermode, unsigned int byte)
{
- /* We support up to 512-bit values (for V8DFmode). */
enum {
- max_bitsize = 512,
value_bit = 8,
value_mask = (1 << value_bit) - 1
};
- unsigned char value[max_bitsize / value_bit];
+ unsigned char value[MAX_BITSIZE_MODE_ANY_MODE / value_bit];
int value_start;
int i;
int elem;
rtvec result_v = NULL;
enum mode_class outer_class;
enum machine_mode outer_submode;
+ int max_bitsize;
/* Some ports misuse CCmode. */
if (GET_MODE_CLASS (outermode) == MODE_CC && CONST_INT_P (op))
if (COMPLEX_MODE_P (outermode))
return NULL_RTX;
+ /* We support any size mode. */
+ max_bitsize = MAX (GET_MODE_BITSIZE (outermode),
+ GET_MODE_BITSIZE (innermode));
+
/* Unpack the value. */
if (GET_CODE (op) == CONST_VECTOR)
*vp++ = INTVAL (el) < 0 ? -1 : 0;
break;
+ case CONST_WIDE_INT:
+ {
+ rtx_mode_t val = std::make_pair (el, innermode);
+ unsigned char extend = wi::sign_mask (val);
+
+ for (i = 0; i < elem_bitsize; i += value_bit)
+ *vp++ = wi::extract_uhwi (val, i, value_bit);
+ for (; i < elem_bitsize; i += value_bit)
+ *vp++ = extend;
+ }
+ break;
+
case CONST_DOUBLE:
- if (GET_MODE (el) == VOIDmode)
+ if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (el) == VOIDmode)
{
unsigned char extend = 0;
/* If this triggers, someone should have generated a
}
else
{
- long tmp[max_bitsize / 32];
+ /* This is big enough for anything on the platform. */
+ long tmp[MAX_BITSIZE_MODE_ANY_MODE / 32];
int bitsize = GET_MODE_BITSIZE (GET_MODE (el));
gcc_assert (SCALAR_FLOAT_MODE_P (GET_MODE (el)));
case MODE_INT:
case MODE_PARTIAL_INT:
{
- unsigned HOST_WIDE_INT hi = 0, lo = 0;
-
- for (i = 0;
- i < HOST_BITS_PER_WIDE_INT && i < elem_bitsize;
- i += value_bit)
- lo |= (unsigned HOST_WIDE_INT)(*vp++ & value_mask) << i;
- for (; i < elem_bitsize; i += value_bit)
- hi |= (unsigned HOST_WIDE_INT)(*vp++ & value_mask)
- << (i - HOST_BITS_PER_WIDE_INT);
-
- /* immed_double_const doesn't call trunc_int_for_mode. I don't
- know why. */
- if (elem_bitsize <= HOST_BITS_PER_WIDE_INT)
- elems[elem] = gen_int_mode (lo, outer_submode);
- else if (elem_bitsize <= HOST_BITS_PER_DOUBLE_INT)
- elems[elem] = immed_double_const (lo, hi, outer_submode);
- else
- return NULL_RTX;
+ int u;
+ int base = 0;
+ int units
+ = (GET_MODE_BITSIZE (outer_submode) + HOST_BITS_PER_WIDE_INT - 1)
+ / HOST_BITS_PER_WIDE_INT;
+ HOST_WIDE_INT tmp[MAX_BITSIZE_MODE_ANY_INT / HOST_BITS_PER_WIDE_INT];
+ wide_int r;
+
+ for (u = 0; u < units; u++)
+ {
+ unsigned HOST_WIDE_INT buf = 0;
+ for (i = 0;
+ i < HOST_BITS_PER_WIDE_INT && base + i < elem_bitsize;
+ i += value_bit)
+ buf |= (unsigned HOST_WIDE_INT)(*vp++ & value_mask) << i;
+
+ tmp[u] = buf;
+ base += HOST_BITS_PER_WIDE_INT;
+ }
+ r = wide_int::from_array (tmp, units,
+ GET_MODE_PRECISION (outer_submode));
+ elems[elem] = immed_wide_int_const (r, outer_submode);
}
break;
case MODE_DECIMAL_FLOAT:
{
REAL_VALUE_TYPE r;
- long tmp[max_bitsize / 32];
+ long tmp[MAX_BITSIZE_MODE_ANY_INT / 32];
/* real_from_target wants its input in words affected by
FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
gcc_assert (GET_MODE (op) == innermode
|| GET_MODE (op) == VOIDmode);
- gcc_assert ((byte % GET_MODE_SIZE (outermode)) == 0);
- gcc_assert (byte < GET_MODE_SIZE (innermode));
+ if ((byte % GET_MODE_SIZE (outermode)) != 0)
+ return NULL_RTX;
+
+ if (byte >= GET_MODE_SIZE (innermode))
+ return NULL_RTX;
if (outermode == innermode && !byte)
return op;
- if (CONST_INT_P (op)
- || CONST_DOUBLE_P (op)
+ if (CONST_SCALAR_INT_P (op)
+ || CONST_DOUBLE_AS_FLOAT_P (op)
|| GET_CODE (op) == CONST_FIXED
|| GET_CODE (op) == CONST_VECTOR)
return simplify_immed_subreg (outermode, op, innermode, byte);
return NULL_RTX;
}
- /* Merge implicit and explicit truncations. */
-
- if (GET_CODE (op) == TRUNCATE
- && GET_MODE_SIZE (outermode) < GET_MODE_SIZE (innermode)
- && subreg_lowpart_offset (outermode, innermode) == byte)
- return simplify_gen_unary (TRUNCATE, outermode, XEXP (op, 0),
- GET_MODE (XEXP (op, 0)));
-
/* SUBREG of a hard register => just change the register number
and/or mode. If the hard register is not valid in that mode,
suppress this simplification. If the hard register is the stack,
return NULL_RTX;
}
- /* Optimize SUBREG truncations of zero and sign extended values. */
- if ((GET_CODE (op) == ZERO_EXTEND
- || GET_CODE (op) == SIGN_EXTEND)
- && SCALAR_INT_MODE_P (innermode)
- && GET_MODE_PRECISION (outermode) < GET_MODE_PRECISION (innermode))
+ /* A SUBREG resulting from a zero extension may fold to zero if
+ it extracts higher bits that the ZERO_EXTEND's source bits. */
+ if (GET_CODE (op) == ZERO_EXTEND && SCALAR_INT_MODE_P (innermode))
{
unsigned int bitpos = subreg_lsb_1 (outermode, innermode, byte);
-
- /* If we're requesting the lowpart of a zero or sign extension,
- there are three possibilities. If the outermode is the same
- as the origmode, we can omit both the extension and the subreg.
- If the outermode is not larger than the origmode, we can apply
- the truncation without the extension. Finally, if the outermode
- is larger than the origmode, but both are integer modes, we
- can just extend to the appropriate mode. */
- if (bitpos == 0)
- {
- enum machine_mode origmode = GET_MODE (XEXP (op, 0));
- if (outermode == origmode)
- return XEXP (op, 0);
- if (GET_MODE_PRECISION (outermode) <= GET_MODE_PRECISION (origmode))
- return simplify_gen_subreg (outermode, XEXP (op, 0), origmode,
- subreg_lowpart_offset (outermode,
- origmode));
- if (SCALAR_INT_MODE_P (outermode))
- return simplify_gen_unary (GET_CODE (op), outermode,
- XEXP (op, 0), origmode);
- }
-
- /* A SUBREG resulting from a zero extension may fold to zero if
- it extracts higher bits that the ZERO_EXTEND's source bits. */
- if (GET_CODE (op) == ZERO_EXTEND
- && bitpos >= GET_MODE_PRECISION (GET_MODE (XEXP (op, 0))))
+ if (bitpos >= GET_MODE_PRECISION (GET_MODE (XEXP (op, 0))))
return CONST0_RTX (outermode);
}
- /* Simplify (subreg:SI (op:DI ((x:DI) (y:DI)), 0)
- to (op:SI (subreg:SI (x:DI) 0) (subreg:SI (x:DI) 0)), where
- the outer subreg is effectively a truncation to the original mode. */
- if ((GET_CODE (op) == PLUS
- || GET_CODE (op) == MINUS
- || GET_CODE (op) == MULT)
- && SCALAR_INT_MODE_P (outermode)
- && SCALAR_INT_MODE_P (innermode)
- && GET_MODE_PRECISION (outermode) < GET_MODE_PRECISION (innermode)
- && byte == subreg_lowpart_offset (outermode, innermode))
- {
- rtx op0 = simplify_gen_subreg (outermode, XEXP (op, 0),
- innermode, byte);
- if (op0)
- {
- rtx op1 = simplify_gen_subreg (outermode, XEXP (op, 1),
- innermode, byte);
- if (op1)
- return simplify_gen_binary (GET_CODE (op), outermode, op0, op1);
- }
- }
-
- /* Simplify (subreg:QI (lshiftrt:SI (sign_extend:SI (x:QI)) C), 0) into
- to (ashiftrt:QI (x:QI) C), where C is a suitable small constant and
- the outer subreg is effectively a truncation to the original mode. */
- if ((GET_CODE (op) == LSHIFTRT
- || GET_CODE (op) == ASHIFTRT)
- && SCALAR_INT_MODE_P (outermode)
- && SCALAR_INT_MODE_P (innermode)
- /* Ensure that OUTERMODE is at least twice as wide as the INNERMODE
- to avoid the possibility that an outer LSHIFTRT shifts by more
- than the sign extension's sign_bit_copies and introduces zeros
- into the high bits of the result. */
- && (2 * GET_MODE_PRECISION (outermode)) <= GET_MODE_PRECISION (innermode)
- && CONST_INT_P (XEXP (op, 1))
- && GET_CODE (XEXP (op, 0)) == SIGN_EXTEND
- && GET_MODE (XEXP (XEXP (op, 0), 0)) == outermode
- && INTVAL (XEXP (op, 1)) < GET_MODE_PRECISION (outermode)
- && subreg_lsb_1 (outermode, innermode, byte) == 0)
- return simplify_gen_binary (ASHIFTRT, outermode,
- XEXP (XEXP (op, 0), 0), XEXP (op, 1));
-
- /* Likewise (subreg:QI (lshiftrt:SI (zero_extend:SI (x:QI)) C), 0) into
- to (lshiftrt:QI (x:QI) C), where C is a suitable small constant and
- the outer subreg is effectively a truncation to the original mode. */
- if ((GET_CODE (op) == LSHIFTRT
- || GET_CODE (op) == ASHIFTRT)
- && SCALAR_INT_MODE_P (outermode)
- && SCALAR_INT_MODE_P (innermode)
- && GET_MODE_PRECISION (outermode) < GET_MODE_PRECISION (innermode)
- && CONST_INT_P (XEXP (op, 1))
- && GET_CODE (XEXP (op, 0)) == ZERO_EXTEND
- && GET_MODE (XEXP (XEXP (op, 0), 0)) == outermode
- && INTVAL (XEXP (op, 1)) < GET_MODE_PRECISION (outermode)
- && subreg_lsb_1 (outermode, innermode, byte) == 0)
- return simplify_gen_binary (LSHIFTRT, outermode,
- XEXP (XEXP (op, 0), 0), XEXP (op, 1));
-
- /* Likewise (subreg:QI (ashift:SI (zero_extend:SI (x:QI)) C), 0) into
- to (ashift:QI (x:QI) C), where C is a suitable small constant and
- the outer subreg is effectively a truncation to the original mode. */
- if (GET_CODE (op) == ASHIFT
- && SCALAR_INT_MODE_P (outermode)
+ if (SCALAR_INT_MODE_P (outermode)
&& SCALAR_INT_MODE_P (innermode)
&& GET_MODE_PRECISION (outermode) < GET_MODE_PRECISION (innermode)
- && CONST_INT_P (XEXP (op, 1))
- && (GET_CODE (XEXP (op, 0)) == ZERO_EXTEND
- || GET_CODE (XEXP (op, 0)) == SIGN_EXTEND)
- && GET_MODE (XEXP (XEXP (op, 0), 0)) == outermode
- && INTVAL (XEXP (op, 1)) < GET_MODE_PRECISION (outermode)
- && subreg_lsb_1 (outermode, innermode, byte) == 0)
- return simplify_gen_binary (ASHIFT, outermode,
- XEXP (XEXP (op, 0), 0), XEXP (op, 1));
-
- /* Recognize a word extraction from a multi-word subreg. */
- if ((GET_CODE (op) == LSHIFTRT
- || GET_CODE (op) == ASHIFTRT)
- && SCALAR_INT_MODE_P (innermode)
- && GET_MODE_PRECISION (outermode) >= BITS_PER_WORD
- && GET_MODE_PRECISION (innermode) >= (2 * GET_MODE_PRECISION (outermode))
- && CONST_INT_P (XEXP (op, 1))
- && (INTVAL (XEXP (op, 1)) & (GET_MODE_PRECISION (outermode) - 1)) == 0
- && INTVAL (XEXP (op, 1)) >= 0
- && INTVAL (XEXP (op, 1)) < GET_MODE_PRECISION (innermode)
&& byte == subreg_lowpart_offset (outermode, innermode))
{
- int shifted_bytes = INTVAL (XEXP (op, 1)) / BITS_PER_UNIT;
- return simplify_gen_subreg (outermode, XEXP (op, 0), innermode,
- (WORDS_BIG_ENDIAN
- ? byte - shifted_bytes
- : byte + shifted_bytes));
- }
-
- /* If we have a lowpart SUBREG of a right shift of MEM, make a new MEM
- and try replacing the SUBREG and shift with it. Don't do this if
- the MEM has a mode-dependent address or if we would be widening it. */
-
- if ((GET_CODE (op) == LSHIFTRT
- || GET_CODE (op) == ASHIFTRT)
- && SCALAR_INT_MODE_P (innermode)
- && MEM_P (XEXP (op, 0))
- && CONST_INT_P (XEXP (op, 1))
- && GET_MODE_SIZE (outermode) < GET_MODE_SIZE (GET_MODE (op))
- && (INTVAL (XEXP (op, 1)) % GET_MODE_BITSIZE (outermode)) == 0
- && INTVAL (XEXP (op, 1)) > 0
- && INTVAL (XEXP (op, 1)) < GET_MODE_BITSIZE (innermode)
- && ! mode_dependent_address_p (XEXP (XEXP (op, 0), 0),
- MEM_ADDR_SPACE (XEXP (op, 0)))
- && ! MEM_VOLATILE_P (XEXP (op, 0))
- && byte == subreg_lowpart_offset (outermode, innermode)
- && (GET_MODE_SIZE (outermode) >= UNITS_PER_WORD
- || WORDS_BIG_ENDIAN == BYTES_BIG_ENDIAN))
- {
- int shifted_bytes = INTVAL (XEXP (op, 1)) / BITS_PER_UNIT;
- return adjust_address_nv (XEXP (op, 0), outermode,
- (WORDS_BIG_ENDIAN
- ? byte - shifted_bytes
- : byte + shifted_bytes));
+ rtx tem = simplify_truncation (outermode, op, innermode);
+ if (tem)
+ return tem;
}
return NULL_RTX;
projects / thirdparty / gcc.git / blobdiff