aarch64: Treat p12-p15 as call-preserved in SVE PCS functions

[thirdparty/gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / pcs / saves_2_be_nowrap.c

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c
index 05aa18b3c949e171a90e11c410edb5fc3b7988e7..7c4884d0e59b26945589efcbc9a5eae94fd3ef29 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c
@@ -9,7 +9,7 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void);
 ** calls_standard:
 **     stp     x29, x30, \[sp, -16\]!
 **     mov     x29, sp
-**     addvl   sp, sp, #-17
+**     addvl   sp, sp, #-18
 **     str     p4, \[sp\]
 **     str     p5, \[sp, #1, mul vl\]
 **     str     p6, \[sp, #2, mul vl\]
@@ -18,43 +18,47 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void);
 **     str     p9, \[sp, #5, mul vl\]
 **     str     p10, \[sp, #6, mul vl\]
 **     str     p11, \[sp, #7, mul vl\]
+**     str     p12, \[sp, #8, mul vl\]
+**     str     p13, \[sp, #9, mul vl\]
+**     str     p14, \[sp, #10, mul vl\]
+**     str     p15, \[sp, #11, mul vl\]
 **     ptrue   p0\.b, all
-**     st1d    z8\.d, p0, \[sp, #1, mul vl\]
-**     st1d    z9\.d, p0, \[sp, #2, mul vl\]
-**     st1d    z10\.d, p0, \[sp, #3, mul vl\]
-**     st1d    z11\.d, p0, \[sp, #4, mul vl\]
-**     st1d    z12\.d, p0, \[sp, #5, mul vl\]
-**     st1d    z13\.d, p0, \[sp, #6, mul vl\]
-**     st1d    z14\.d, p0, \[sp, #7, mul vl\]
+**     st1d    z8\.d, p0, \[sp, #2, mul vl\]
+**     st1d    z9\.d, p0, \[sp, #3, mul vl\]
+**     st1d    z10\.d, p0, \[sp, #4, mul vl\]
+**     st1d    z11\.d, p0, \[sp, #5, mul vl\]
+**     st1d    z12\.d, p0, \[sp, #6, mul vl\]
+**     st1d    z13\.d, p0, \[sp, #7, mul vl\]
 **     addvl   x11, sp, #16
-**     st1d    z15\.d, p0, \[x11, #-8, mul vl\]
-**     str     z16, \[sp, #9, mul vl\]
-**     str     z17, \[sp, #10, mul vl\]
-**     str     z18, \[sp, #11, mul vl\]
-**     str     z19, \[sp, #12, mul vl\]
-**     str     z20, \[sp, #13, mul vl\]
-**     str     z21, \[sp, #14, mul vl\]
-**     str     z22, \[sp, #15, mul vl\]
-**     str     z23, \[sp, #16, mul vl\]
+**     st1d    z14\.d, p0, \[x11, #-8, mul vl\]
+**     st1d    z15\.d, p0, \[x11, #-7, mul vl\]
+**     str     z16, \[sp, #10, mul vl\]
+**     str     z17, \[sp, #11, mul vl\]
+**     str     z18, \[sp, #12, mul vl\]
+**     str     z19, \[sp, #13, mul vl\]
+**     str     z20, \[sp, #14, mul vl\]
+**     str     z21, \[sp, #15, mul vl\]
+**     str     z22, \[sp, #16, mul vl\]
+**     str     z23, \[sp, #17, mul vl\]
 **     bl      standard_callee
 **     ptrue   p0\.b, all
-**     ld1d    z8\.d, p0/z, \[sp, #1, mul vl\]
-**     ld1d    z9\.d, p0/z, \[sp, #2, mul vl\]
-**     ld1d    z10\.d, p0/z, \[sp, #3, mul vl\]
-**     ld1d    z11\.d, p0/z, \[sp, #4, mul vl\]
-**     ld1d    z12\.d, p0/z, \[sp, #5, mul vl\]
-**     ld1d    z13\.d, p0/z, \[sp, #6, mul vl\]
-**     ld1d    z14\.d, p0/z, \[sp, #7, mul vl\]
+**     ld1d    z8\.d, p0/z, \[sp, #2, mul vl\]
+**     ld1d    z9\.d, p0/z, \[sp, #3, mul vl\]
+**     ld1d    z10\.d, p0/z, \[sp, #4, mul vl\]
+**     ld1d    z11\.d, p0/z, \[sp, #5, mul vl\]
+**     ld1d    z12\.d, p0/z, \[sp, #6, mul vl\]
+**     ld1d    z13\.d, p0/z, \[sp, #7, mul vl\]
 **     addvl   x11, sp, #16
-**     ld1d    z15\.d, p0/z, \[x11, #-8, mul vl\]
-**     ldr     z16, \[sp, #9, mul vl\]
-**     ldr     z17, \[sp, #10, mul vl\]
-**     ldr     z18, \[sp, #11, mul vl\]
-**     ldr     z19, \[sp, #12, mul vl\]
-**     ldr     z20, \[sp, #13, mul vl\]
-**     ldr     z21, \[sp, #14, mul vl\]
-**     ldr     z22, \[sp, #15, mul vl\]
-**     ldr     z23, \[sp, #16, mul vl\]
+**     ld1d    z14\.d, p0/z, \[x11, #-8, mul vl\]
+**     ld1d    z15\.d, p0/z, \[x11, #-7, mul vl\]
+**     ldr     z16, \[sp, #10, mul vl\]
+**     ldr     z17, \[sp, #11, mul vl\]
+**     ldr     z18, \[sp, #12, mul vl\]
+**     ldr     z19, \[sp, #13, mul vl\]
+**     ldr     z20, \[sp, #14, mul vl\]
+**     ldr     z21, \[sp, #15, mul vl\]
+**     ldr     z22, \[sp, #16, mul vl\]
+**     ldr     z23, \[sp, #17, mul vl\]
 **     ldr     p4, \[sp\]
 **     ldr     p5, \[sp, #1, mul vl\]
 **     ldr     p6, \[sp, #2, mul vl\]
@@ -63,7 +67,11 @@ __attribute__((aarch64_vector_pcs)) void vpcs_callee (void);
 **     ldr     p9, \[sp, #5, mul vl\]
 **     ldr     p10, \[sp, #6, mul vl\]
 **     ldr     p11, \[sp, #7, mul vl\]
-**     addvl   sp, sp, #17
+**     ldr     p12, \[sp, #8, mul vl\]
+**     ldr     p13, \[sp, #9, mul vl\]
+**     ldr     p14, \[sp, #10, mul vl\]
+**     ldr     p15, \[sp, #11, mul vl\]
+**     addvl   sp, sp, #18
 **     ldp     x29, x30, \[sp\], 16
 **     ret
 */
@@ -73,7 +81,7 @@ void calls_standard (__SVInt8_t x) { standard_callee (); }
 ** calls_vpcs:
 **     stp     x29, x30, \[sp, -16\]!
 **     mov     x29, sp
-**     addvl   sp, sp, #-17
+**     addvl   sp, sp, #-18
 **     str     p4, \[sp\]
 **     str     p5, \[sp, #1, mul vl\]
 **     str     p6, \[sp, #2, mul vl\]
@@ -82,43 +90,47 @@ void calls_standard (__SVInt8_t x) { standard_callee (); }
 **     str     p9, \[sp, #5, mul vl\]
 **     str     p10, \[sp, #6, mul vl\]
 **     str     p11, \[sp, #7, mul vl\]
+**     str     p12, \[sp, #8, mul vl\]
+**     str     p13, \[sp, #9, mul vl\]
+**     str     p14, \[sp, #10, mul vl\]
+**     str     p15, \[sp, #11, mul vl\]
 **     ptrue   p0\.b, all
-**     st1d    z8\.d, p0, \[sp, #1, mul vl\]
-**     st1d    z9\.d, p0, \[sp, #2, mul vl\]
-**     st1d    z10\.d, p0, \[sp, #3, mul vl\]
-**     st1d    z11\.d, p0, \[sp, #4, mul vl\]
-**     st1d    z12\.d, p0, \[sp, #5, mul vl\]
-**     st1d    z13\.d, p0, \[sp, #6, mul vl\]
-**     st1d    z14\.d, p0, \[sp, #7, mul vl\]
+**     st1d    z8\.d, p0, \[sp, #2, mul vl\]
+**     st1d    z9\.d, p0, \[sp, #3, mul vl\]
+**     st1d    z10\.d, p0, \[sp, #4, mul vl\]
+**     st1d    z11\.d, p0, \[sp, #5, mul vl\]
+**     st1d    z12\.d, p0, \[sp, #6, mul vl\]
+**     st1d    z13\.d, p0, \[sp, #7, mul vl\]
 **     addvl   x11, sp, #16
-**     st1d    z15\.d, p0, \[x11, #-8, mul vl\]
-**     str     z16, \[sp, #9, mul vl\]
-**     str     z17, \[sp, #10, mul vl\]
-**     str     z18, \[sp, #11, mul vl\]
-**     str     z19, \[sp, #12, mul vl\]
-**     str     z20, \[sp, #13, mul vl\]
-**     str     z21, \[sp, #14, mul vl\]
-**     str     z22, \[sp, #15, mul vl\]
-**     str     z23, \[sp, #16, mul vl\]
+**     st1d    z14\.d, p0, \[x11, #-8, mul vl\]
+**     st1d    z15\.d, p0, \[x11, #-7, mul vl\]
+**     str     z16, \[sp, #10, mul vl\]
+**     str     z17, \[sp, #11, mul vl\]
+**     str     z18, \[sp, #12, mul vl\]
+**     str     z19, \[sp, #13, mul vl\]
+**     str     z20, \[sp, #14, mul vl\]
+**     str     z21, \[sp, #15, mul vl\]
+**     str     z22, \[sp, #16, mul vl\]
+**     str     z23, \[sp, #17, mul vl\]
 **     bl      vpcs_callee
 **     ptrue   p0\.b, all
-**     ld1d    z8\.d, p0/z, \[sp, #1, mul vl\]
-**     ld1d    z9\.d, p0/z, \[sp, #2, mul vl\]
-**     ld1d    z10\.d, p0/z, \[sp, #3, mul vl\]
-**     ld1d    z11\.d, p0/z, \[sp, #4, mul vl\]
-**     ld1d    z12\.d, p0/z, \[sp, #5, mul vl\]
-**     ld1d    z13\.d, p0/z, \[sp, #6, mul vl\]
-**     ld1d    z14\.d, p0/z, \[sp, #7, mul vl\]
+**     ld1d    z8\.d, p0/z, \[sp, #2, mul vl\]
+**     ld1d    z9\.d, p0/z, \[sp, #3, mul vl\]
+**     ld1d    z10\.d, p0/z, \[sp, #4, mul vl\]
+**     ld1d    z11\.d, p0/z, \[sp, #5, mul vl\]
+**     ld1d    z12\.d, p0/z, \[sp, #6, mul vl\]
+**     ld1d    z13\.d, p0/z, \[sp, #7, mul vl\]
 **     addvl   x11, sp, #16
-**     ld1d    z15\.d, p0/z, \[x11, #-8, mul vl\]
-**     ldr     z16, \[sp, #9, mul vl\]
-**     ldr     z17, \[sp, #10, mul vl\]
-**     ldr     z18, \[sp, #11, mul vl\]
-**     ldr     z19, \[sp, #12, mul vl\]
-**     ldr     z20, \[sp, #13, mul vl\]
-**     ldr     z21, \[sp, #14, mul vl\]
-**     ldr     z22, \[sp, #15, mul vl\]
-**     ldr     z23, \[sp, #16, mul vl\]
+**     ld1d    z14\.d, p0/z, \[x11, #-8, mul vl\]
+**     ld1d    z15\.d, p0/z, \[x11, #-7, mul vl\]
+**     ldr     z16, \[sp, #10, mul vl\]
+**     ldr     z17, \[sp, #11, mul vl\]
+**     ldr     z18, \[sp, #12, mul vl\]
+**     ldr     z19, \[sp, #13, mul vl\]
+**     ldr     z20, \[sp, #14, mul vl\]
+**     ldr     z21, \[sp, #15, mul vl\]
+**     ldr     z22, \[sp, #16, mul vl\]
+**     ldr     z23, \[sp, #17, mul vl\]
 **     ldr     p4, \[sp\]
 **     ldr     p5, \[sp, #1, mul vl\]
 **     ldr     p6, \[sp, #2, mul vl\]
@@ -127,7 +139,11 @@ void calls_standard (__SVInt8_t x) { standard_callee (); }
 **     ldr     p9, \[sp, #5, mul vl\]
 **     ldr     p10, \[sp, #6, mul vl\]
 **     ldr     p11, \[sp, #7, mul vl\]
-**     addvl   sp, sp, #17
+**     ldr     p12, \[sp, #8, mul vl\]
+**     ldr     p13, \[sp, #9, mul vl\]
+**     ldr     p14, \[sp, #10, mul vl\]
+**     ldr     p15, \[sp, #11, mul vl\]
+**     addvl   sp, sp, #18
 **     ldp     x29, x30, \[sp\], 16
 **     ret
 */
@@ -137,7 +153,7 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); }
 ** calls_standard_ptr:
 **     stp     x29, x30, \[sp, -16\]!
 **     mov     x29, sp
-**     addvl   sp, sp, #-17
+**     addvl   sp, sp, #-18
 **     str     p4, \[sp\]
 **     str     p5, \[sp, #1, mul vl\]
 **     str     p6, \[sp, #2, mul vl\]
@@ -146,43 +162,47 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); }
 **     str     p9, \[sp, #5, mul vl\]
 **     str     p10, \[sp, #6, mul vl\]
 **     str     p11, \[sp, #7, mul vl\]
+**     str     p12, \[sp, #8, mul vl\]
+**     str     p13, \[sp, #9, mul vl\]
+**     str     p14, \[sp, #10, mul vl\]
+**     str     p15, \[sp, #11, mul vl\]
 **     ptrue   p0\.b, all
-**     st1d    z8\.d, p0, \[sp, #1, mul vl\]
-**     st1d    z9\.d, p0, \[sp, #2, mul vl\]
-**     st1d    z10\.d, p0, \[sp, #3, mul vl\]
-**     st1d    z11\.d, p0, \[sp, #4, mul vl\]
-**     st1d    z12\.d, p0, \[sp, #5, mul vl\]
-**     st1d    z13\.d, p0, \[sp, #6, mul vl\]
-**     st1d    z14\.d, p0, \[sp, #7, mul vl\]
+**     st1d    z8\.d, p0, \[sp, #2, mul vl\]
+**     st1d    z9\.d, p0, \[sp, #3, mul vl\]
+**     st1d    z10\.d, p0, \[sp, #4, mul vl\]
+**     st1d    z11\.d, p0, \[sp, #5, mul vl\]
+**     st1d    z12\.d, p0, \[sp, #6, mul vl\]
+**     st1d    z13\.d, p0, \[sp, #7, mul vl\]
 **     addvl   x11, sp, #16
-**     st1d    z15\.d, p0, \[x11, #-8, mul vl\]
-**     str     z16, \[sp, #9, mul vl\]
-**     str     z17, \[sp, #10, mul vl\]
-**     str     z18, \[sp, #11, mul vl\]
-**     str     z19, \[sp, #12, mul vl\]
-**     str     z20, \[sp, #13, mul vl\]
-**     str     z21, \[sp, #14, mul vl\]
-**     str     z22, \[sp, #15, mul vl\]
-**     str     z23, \[sp, #16, mul vl\]
+**     st1d    z14\.d, p0, \[x11, #-8, mul vl\]
+**     st1d    z15\.d, p0, \[x11, #-7, mul vl\]
+**     str     z16, \[sp, #10, mul vl\]
+**     str     z17, \[sp, #11, mul vl\]
+**     str     z18, \[sp, #12, mul vl\]
+**     str     z19, \[sp, #13, mul vl\]
+**     str     z20, \[sp, #14, mul vl\]
+**     str     z21, \[sp, #15, mul vl\]
+**     str     z22, \[sp, #16, mul vl\]
+**     str     z23, \[sp, #17, mul vl\]
 **     blr     x0
 **     ptrue   p0\.b, all
-**     ld1d    z8\.d, p0/z, \[sp, #1, mul vl\]
-**     ld1d    z9\.d, p0/z, \[sp, #2, mul vl\]
-**     ld1d    z10\.d, p0/z, \[sp, #3, mul vl\]
-**     ld1d    z11\.d, p0/z, \[sp, #4, mul vl\]
-**     ld1d    z12\.d, p0/z, \[sp, #5, mul vl\]
-**     ld1d    z13\.d, p0/z, \[sp, #6, mul vl\]
-**     ld1d    z14\.d, p0/z, \[sp, #7, mul vl\]
+**     ld1d    z8\.d, p0/z, \[sp, #2, mul vl\]
+**     ld1d    z9\.d, p0/z, \[sp, #3, mul vl\]
+**     ld1d    z10\.d, p0/z, \[sp, #4, mul vl\]
+**     ld1d    z11\.d, p0/z, \[sp, #5, mul vl\]
+**     ld1d    z12\.d, p0/z, \[sp, #6, mul vl\]
+**     ld1d    z13\.d, p0/z, \[sp, #7, mul vl\]
 **     addvl   x11, sp, #16
-**     ld1d    z15\.d, p0/z, \[x11, #-8, mul vl\]
-**     ldr     z16, \[sp, #9, mul vl\]
-**     ldr     z17, \[sp, #10, mul vl\]
-**     ldr     z18, \[sp, #11, mul vl\]
-**     ldr     z19, \[sp, #12, mul vl\]
-**     ldr     z20, \[sp, #13, mul vl\]
-**     ldr     z21, \[sp, #14, mul vl\]
-**     ldr     z22, \[sp, #15, mul vl\]
-**     ldr     z23, \[sp, #16, mul vl\]
+**     ld1d    z14\.d, p0/z, \[x11, #-8, mul vl\]
+**     ld1d    z15\.d, p0/z, \[x11, #-7, mul vl\]
+**     ldr     z16, \[sp, #10, mul vl\]
+**     ldr     z17, \[sp, #11, mul vl\]
+**     ldr     z18, \[sp, #12, mul vl\]
+**     ldr     z19, \[sp, #13, mul vl\]
+**     ldr     z20, \[sp, #14, mul vl\]
+**     ldr     z21, \[sp, #15, mul vl\]
+**     ldr     z22, \[sp, #16, mul vl\]
+**     ldr     z23, \[sp, #17, mul vl\]
 **     ldr     p4, \[sp\]
 **     ldr     p5, \[sp, #1, mul vl\]
 **     ldr     p6, \[sp, #2, mul vl\]
@@ -191,7 +211,11 @@ void calls_vpcs (__SVInt8_t x) { vpcs_callee (); }
 **     ldr     p9, \[sp, #5, mul vl\]
 **     ldr     p10, \[sp, #6, mul vl\]
 **     ldr     p11, \[sp, #7, mul vl\]
-**     addvl   sp, sp, #17
+**     ldr     p12, \[sp, #8, mul vl\]
+**     ldr     p13, \[sp, #9, mul vl\]
+**     ldr     p14, \[sp, #10, mul vl\]
+**     ldr     p15, \[sp, #11, mul vl\]
+**     addvl   sp, sp, #18
 **     ldp     x29, x30, \[sp\], 16
 **     ret
 */
@@ -205,7 +229,7 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void))
 ** calls_vpcs_ptr:
 **     stp     x29, x30, \[sp, -16\]!
 **     mov     x29, sp
-**     addvl   sp, sp, #-17
+**     addvl   sp, sp, #-18
 **     str     p4, \[sp\]
 **     str     p5, \[sp, #1, mul vl\]
 **     str     p6, \[sp, #2, mul vl\]
@@ -214,43 +238,47 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void))
 **     str     p9, \[sp, #5, mul vl\]
 **     str     p10, \[sp, #6, mul vl\]
 **     str     p11, \[sp, #7, mul vl\]
+**     str     p12, \[sp, #8, mul vl\]
+**     str     p13, \[sp, #9, mul vl\]
+**     str     p14, \[sp, #10, mul vl\]
+**     str     p15, \[sp, #11, mul vl\]
 **     ptrue   p0\.b, all
-**     st1d    z8\.d, p0, \[sp, #1, mul vl\]
-**     st1d    z9\.d, p0, \[sp, #2, mul vl\]
-**     st1d    z10\.d, p0, \[sp, #3, mul vl\]
-**     st1d    z11\.d, p0, \[sp, #4, mul vl\]
-**     st1d    z12\.d, p0, \[sp, #5, mul vl\]
-**     st1d    z13\.d, p0, \[sp, #6, mul vl\]
-**     st1d    z14\.d, p0, \[sp, #7, mul vl\]
+**     st1d    z8\.d, p0, \[sp, #2, mul vl\]
+**     st1d    z9\.d, p0, \[sp, #3, mul vl\]
+**     st1d    z10\.d, p0, \[sp, #4, mul vl\]
+**     st1d    z11\.d, p0, \[sp, #5, mul vl\]
+**     st1d    z12\.d, p0, \[sp, #6, mul vl\]
+**     st1d    z13\.d, p0, \[sp, #7, mul vl\]
 **     addvl   x11, sp, #16
-**     st1d    z15\.d, p0, \[x11, #-8, mul vl\]
-**     str     z16, \[sp, #9, mul vl\]
-**     str     z17, \[sp, #10, mul vl\]
-**     str     z18, \[sp, #11, mul vl\]
-**     str     z19, \[sp, #12, mul vl\]
-**     str     z20, \[sp, #13, mul vl\]
-**     str     z21, \[sp, #14, mul vl\]
-**     str     z22, \[sp, #15, mul vl\]
-**     str     z23, \[sp, #16, mul vl\]
+**     st1d    z14\.d, p0, \[x11, #-8, mul vl\]
+**     st1d    z15\.d, p0, \[x11, #-7, mul vl\]
+**     str     z16, \[sp, #10, mul vl\]
+**     str     z17, \[sp, #11, mul vl\]
+**     str     z18, \[sp, #12, mul vl\]
+**     str     z19, \[sp, #13, mul vl\]
+**     str     z20, \[sp, #14, mul vl\]
+**     str     z21, \[sp, #15, mul vl\]
+**     str     z22, \[sp, #16, mul vl\]
+**     str     z23, \[sp, #17, mul vl\]
 **     blr     x0
 **     ptrue   p0\.b, all
-**     ld1d    z8\.d, p0/z, \[sp, #1, mul vl\]
-**     ld1d    z9\.d, p0/z, \[sp, #2, mul vl\]
-**     ld1d    z10\.d, p0/z, \[sp, #3, mul vl\]
-**     ld1d    z11\.d, p0/z, \[sp, #4, mul vl\]
-**     ld1d    z12\.d, p0/z, \[sp, #5, mul vl\]
-**     ld1d    z13\.d, p0/z, \[sp, #6, mul vl\]
-**     ld1d    z14\.d, p0/z, \[sp, #7, mul vl\]
+**     ld1d    z8\.d, p0/z, \[sp, #2, mul vl\]
+**     ld1d    z9\.d, p0/z, \[sp, #3, mul vl\]
+**     ld1d    z10\.d, p0/z, \[sp, #4, mul vl\]
+**     ld1d    z11\.d, p0/z, \[sp, #5, mul vl\]
+**     ld1d    z12\.d, p0/z, \[sp, #6, mul vl\]
+**     ld1d    z13\.d, p0/z, \[sp, #7, mul vl\]
 **     addvl   x11, sp, #16
-**     ld1d    z15\.d, p0/z, \[x11, #-8, mul vl\]
-**     ldr     z16, \[sp, #9, mul vl\]
-**     ldr     z17, \[sp, #10, mul vl\]
-**     ldr     z18, \[sp, #11, mul vl\]
-**     ldr     z19, \[sp, #12, mul vl\]
-**     ldr     z20, \[sp, #13, mul vl\]
-**     ldr     z21, \[sp, #14, mul vl\]
-**     ldr     z22, \[sp, #15, mul vl\]
-**     ldr     z23, \[sp, #16, mul vl\]
+**     ld1d    z14\.d, p0/z, \[x11, #-8, mul vl\]
+**     ld1d    z15\.d, p0/z, \[x11, #-7, mul vl\]
+**     ldr     z16, \[sp, #10, mul vl\]
+**     ldr     z17, \[sp, #11, mul vl\]
+**     ldr     z18, \[sp, #12, mul vl\]
+**     ldr     z19, \[sp, #13, mul vl\]
+**     ldr     z20, \[sp, #14, mul vl\]
+**     ldr     z21, \[sp, #15, mul vl\]
+**     ldr     z22, \[sp, #16, mul vl\]
+**     ldr     z23, \[sp, #17, mul vl\]
 **     ldr     p4, \[sp\]
 **     ldr     p5, \[sp, #1, mul vl\]
 **     ldr     p6, \[sp, #2, mul vl\]
@@ -259,7 +287,11 @@ calls_standard_ptr (__SVInt8_t x, void (*fn) (void))
 **     ldr     p9, \[sp, #5, mul vl\]
 **     ldr     p10, \[sp, #6, mul vl\]
 **     ldr     p11, \[sp, #7, mul vl\]
-**     addvl   sp, sp, #17
+**     ldr     p12, \[sp, #8, mul vl\]
+**     ldr     p13, \[sp, #9, mul vl\]
+**     ldr     p14, \[sp, #10, mul vl\]
+**     ldr     p15, \[sp, #11, mul vl\]
+**     addvl   sp, sp, #18
 **     ldp     x29, x30, \[sp\], 16
 **     ret
 */