Fix __atomic to not implement atomic loads with CAS.

[thirdparty/gcc.git] / gcc / testsuite / lib / target-supports.exp

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 12dbf475e31933cff781c2f9e9c1cfbe2ce108bb..7a260085405c850ef4042faffc4ad71fdb25c830 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -252,6 +252,20 @@ proc check_runtime {prop args} {
     }]
 }
 
+# Return 1 if GCC was configured with $pattern.
+proc check_configured_with { pattern } {
+    global tool
+
+    set gcc_output [${tool}_target_compile "-v" "" "none" ""]
+    if { [ regexp "Configured with: \[^\n\]*$pattern" $gcc_output ] } {
+        verbose "Matched: $pattern" 2
+        return 1
+    }
+
+    verbose "Failed to match: $pattern" 2
+    return 0
+}
+
 ###############################
 # proc check_weak_available { }
 ###############################
@@ -3817,6 +3831,12 @@ proc add_options_for_arm_arch_v7ve { flags } {
     return "$flags -march=armv7ve"
 }
 
+# Return 1 if GCC was configured with --with-mode=
+proc check_effective_target_default_mode { } {
+
+    return [check_configured_with "with-mode="]
+}
+
 # Return 1 if this is an ARM target where -marm causes ARM to be
 # used (not Thumb)
 
@@ -5732,6 +5752,9 @@ proc check_effective_target_vect_hw_misalign { } {
             || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) } {
          set et_vect_hw_misalign_saved($et_index) 1
        }
+       if { [istarget arm*-*-*] } {
+           set et_vect_hw_misalign_saved($et_index) [check_effective_target_arm_vect_no_misalign]
+       }
     }
     verbose "check_effective_target_vect_hw_misalign:\
             returning $et_vect_hw_misalign_saved($et_index)" 2
@@ -6491,9 +6514,7 @@ proc check_effective_target_section_anchors { } {
 # Return 1 if the target supports atomic operations on "int_128" values.
 
 proc check_effective_target_sync_int_128 { } {
-    if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
-         && ![is-effective-target ia32])
-        || [istarget spu-*-*] } {
+    if { [istarget spu-*-*] } {
        return 1
     } else {
        return 0
@@ -6502,23 +6523,10 @@ proc check_effective_target_sync_int_128 { } {
 
 # Return 1 if the target supports atomic operations on "int_128" values
 # and can execute them.
+# This requires support for both compare-and-swap and true atomic loads.
 
 proc check_effective_target_sync_int_128_runtime { } {
-    if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
-         && ![is-effective-target ia32]
-         && [check_cached_effective_target sync_int_128_available {
-             check_runtime_nocache sync_int_128_available {
-                 #include "cpuid.h"
-                 int main ()
-                 {
-                     unsigned int eax, ebx, ecx, edx;
-                     if (__get_cpuid (1, &eax, &ebx, &ecx, &edx))
-                       return !(ecx & bit_CMPXCHG16B);
-                     return 1;
-                 }
-             } ""
-         }])
-        || [istarget spu-*-*] } {
+    if { [istarget spu-*-*] } {
        return 1
     } else {
        return 0