Cleanup (PPC4xx is AMCC now)

[people/ms/u-boot.git] / include / configs / PMC405.h

diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index 11d6fa767c962208ed52ce6c1cb69f3b58d23abb..8bcab0b0f378ea0571aabc9a3c8b8f8f6fd30975 100644 (file)
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -183,14 +183,17 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_FLASH_CFI          1       /* Flash is CFI conformant              */
-#define CFG_MAX_FLASH_SECT     128     /* max number of sectors on one chip    */
-#define CFG_MAX_FLASH_BANKS    2       /* max number of memory banks           */
-#undef CFG_FLASH_PROTECTION            /* don't use hardware protection        */
-#define CFG_FLASH_USE_BUFFER_WRITE 1   /* use buffered writes (20x faster)     */
 #define CFG_FLASH_BASE         0xFE000000
 #define CFG_FLASH_INCREMENT    0x01000000
 
+#define CFG_FLASH_CFI         1       /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER  1       /* Use the common driver */
+#define CFG_FLASH_PROTECTION  1       /* don't use hardware protection        */
+#define CFG_FLASH_USE_BUFFER_WRITE 1  /* use buffered writes (20x faster)     */
+#define CFG_MAX_FLASH_BANKS   2       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_FLASH_INCREMENT }
+#define CFG_MAX_FLASH_SECT    128     /* max num of sects on one chip */
+
 #define CFG_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
 
 /*
@@ -200,8 +203,8 @@
 /* No command line, one static partition, whole device */
 #undef CONFIG_JFFS2_CMDLINE
 #define CONFIG_JFFS2_DEV               "nor0"
-#define CONFIG_JFFS2_PART_SIZE         0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET       0x00000000
+#define CONFIG_JFFS2_PART_SIZE         0x01b00000
+#define CONFIG_JFFS2_PART_OFFSET       0x00400000
 
 /* mtdparts command line support */
 /* Note: fake mtd_id used, no linux mtd map file */
@@ -242,7 +245,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE                16384   /* For IBM 405 CPUs, older 405 ppc's    */
+#define CFG_DCACHE_SIZE                16384   /* For AMCC 405 CPUs, older 405 ppc's   */
                                        /* have only 8kB, 16kB is save here     */
 #define CFG_CACHELINE_SIZE     32      /* ...                  */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)